47 /* #define PACKETBUF_MEMSIZE	0x40 */
82 module_param_array(options, int, NULL, 0);
83 module_param_array(full_duplex, int, NULL, 0);
106 	FORCE_FDX = 0x20,
107 	REALTEK_FDX = 0x40, HOLTEK_FDX = 0x80,
108 	STOP_PG_0x60 = 0x100,
112 	CH_RealTek_RTL_8029 = 0,
131 	{"Winbond 89C940", 0},
132 	{"Compex RL2000", 0},
133 	{"KTI ET32P2", 0},
134 	{"NetVin NV5000SC", 0},
136 	{"SureCom NE34", 0},
137 	{"Winbond W89C940F", 0},
140 	{"Winbond W89C940(misprogrammed)", 0},
146 	{ 0x10ec, 0x8029, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_RealTek_RTL_8029 },
147 	{ 0x1050, 0x0940, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_Winbond_89C940 },
148 	{ 0x11f6, 0x1401, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_Compex_RL2000 },
149 	{ 0x8e2e, 0x3000, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_KTI_ET32P2 },
150 	{ 0x4a14, 0x5000, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_NetVin_NV5000SC },
151 	{ 0x1106, 0x0926, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_Via_86C926 },
152 	{ 0x10bd, 0x0e34, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_SureCom_NE34 },
153 	{ 0x1050, 0x5a5a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_Winbond_W89C940F },
154 	{ 0x12c3, 0x0058, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_Holtek_HT80232 },
155 	{ 0x12c3, 0x5598, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_Holtek_HT80229 },
156 	{ 0x8c4a, 0x1980, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_Winbond_89C940_8c4a },
157 	{ 0, }
166 #define NE_CMD		0x00
167 #define NE_DATAPORT	0x10	/* NatSemi-defined port window offset. */
168 #define NE_RESET	0x1f	/* Issue a read to reset, a write to clear. */
169 #define NE_IO_EXTENT	0x20
171 #define NESM_START_PG	0x40	/* First page of TX buffer */
172 #define NESM_STOP_PG	0x80	/* Last page +1 of RX ring */
190  * buffer memory space.  By-the-spec NE2000 clones have 0x57,0x57 in bytes
191  * 0x0e,0x0f of the SAPROM, while other supposed NE2000 clones must be
234 	ioaddr = pci_resource_start(pdev, 0);  in ne2k_pci_init_one()
237 	if (!ioaddr || ((pci_resource_flags(pdev, 0) & IORESOURCE_IO) == 0)) {  in ne2k_pci_init_one()
238 		dev_err(&pdev->dev, "no I/O resource at PCI BAR #0\n");  in ne2k_pci_init_one()
243 		dev_err(&pdev->dev, "I/O resource 0x%x @ 0x%lx busy\n",  in ne2k_pci_init_one()
249 	if (reg0 == 0xFF)  in ne2k_pci_init_one()
257 		regd = inb(ioaddr + 0x0d);  in ne2k_pci_init_one()
258 		outb(0xff, ioaddr + 0x0d);  in ne2k_pci_init_one()
262 		if (inb(ioaddr + EN0_COUNTER0) != 0) {  in ne2k_pci_init_one()
265 			outb(regd, ioaddr + 0x0d);  in ne2k_pci_init_one()
291 		while ((inb(ioaddr + EN0_ISR) & ENISR_RESET) == 0)  in ne2k_pci_init_one()
299 		outb(0xff, ioaddr + EN0_ISR);  in ne2k_pci_init_one()
304 	 * to NS8390_init(eifdev, 0).  in ne2k_pci_init_one()
310 			/* Select page 0 */  in ne2k_pci_init_one()
313 			{0x49,	EN0_DCFG},  in ne2k_pci_init_one()
315 			{0x00,	EN0_RCNTLO},  in ne2k_pci_init_one()
317 			{0x00,	EN0_RCNTHI},  in ne2k_pci_init_one()
318 			{0x00,	EN0_IMR},  in ne2k_pci_init_one()
319 			{0xFF,	EN0_ISR},  in ne2k_pci_init_one()
320 			/* 0x20 Set to monitor */  in ne2k_pci_init_one()
322 			/* 0x02 and loopback mode */  in ne2k_pci_init_one()
325 			{0x00,	EN0_RCNTHI},  in ne2k_pci_init_one()
326 			/* DMA starting at 0x0000 */  in ne2k_pci_init_one()
327 			{0x00,	EN0_RSARLO},  in ne2k_pci_init_one()
328 			{0x00,	EN0_RSARHI},  in ne2k_pci_init_one()
331 		for (i = 0; i < ARRAY_SIZE(program_seq); i++)  in ne2k_pci_init_one()
341 		for (i = 0; i < 4 ; i++)  in ne2k_pci_init_one()
344 		for (i = 0; i < 32 /* sizeof(SA_prom )*/; i++)  in ne2k_pci_init_one()
348 	outb(0x49, ioaddr + EN0_DCFG);  in ne2k_pci_init_one()
351 	stop_page = flags & STOP_PG_0x60 ? 0x60 : NESM_STOP_PG;  in ne2k_pci_init_one()
364 		if (full_duplex[fnd_cnt] > 0 || (options[fnd_cnt] & FORCE_FDX))  in ne2k_pci_init_one()
381 	NS8390_init(dev, 0);  in ne2k_pci_init_one()
393 	return 0;  in ne2k_pci_init_one()
410 	outb(0xC0 + E8390_NODMA, ioaddr + NE_CMD); /* Page 3 */  in set_realtek_fdx()
411 	outb(0xC0, ioaddr + 0x01); /* Enable writes to CONFIG3 */  in set_realtek_fdx()
412 	outb(0x40, ioaddr + 0x06); /* Enable full duplex */  in set_realtek_fdx()
413 	outb(0x00, ioaddr + 0x01); /* Disable writes to CONFIG3 */  in set_realtek_fdx()
414 	outb(E8390_PAGE0 + E8390_NODMA, ioaddr + NE_CMD); /* Page 0 */  in set_realtek_fdx()
415 	return 0;  in set_realtek_fdx()
422 	outb(inb(ioaddr + 0x20) | 0x80, ioaddr + 0x20);  in set_holtek_fdx()
423 	return 0;  in set_holtek_fdx()
448 	return 0;  in ne2k_pci_open()
455 	return 0;  in ne2k_pci_close()
471 	ei_status.txing = 0;  in ne2k_pci_reset_8390()
472 	ei_status.dmaing = 0;  in ne2k_pci_reset_8390()
475 	while ((inb(NE_BASE+EN0_ISR) & ENISR_RESET) == 0)  in ne2k_pci_reset_8390()
503 	ei_status.dmaing |= 0x01;  in ne2k_pci_get_8390_hdr()
506 	outb(0, nic_base + EN0_RCNTHI);  in ne2k_pci_get_8390_hdr()
507 	outb(0, nic_base + EN0_RSARLO);		/* On page boundary */  in ne2k_pci_get_8390_hdr()
520 	ei_status.dmaing &= ~0x01;  in ne2k_pci_get_8390_hdr()
543 	ei_status.dmaing |= 0x01;  in ne2k_pci_block_input()
545 		count = (count + 3) & 0xFFFC;  in ne2k_pci_block_input()
547 	outb(count & 0xff, nic_base + EN0_RCNTLO);  in ne2k_pci_block_input()
549 	outb(ring_offset & 0xff, nic_base + EN0_RSARLO);  in ne2k_pci_block_input()
555 		if (count & 0x01)  in ne2k_pci_block_input()
573 	ei_status.dmaing &= ~0x01;  in ne2k_pci_block_input()
586 		count = (count + 3) & 0xFFFC;  in ne2k_pci_block_output()
588 		if (count & 0x01)  in ne2k_pci_block_output()
599 	ei_status.dmaing |= 0x01;  in ne2k_pci_block_output()
600 	/* We should already be in page 0, but to be safe... */  in ne2k_pci_block_output()
609 	outb(0x42, nic_base + EN0_RCNTLO);  in ne2k_pci_block_output()
610 	outb(0x00, nic_base + EN0_RCNTHI);  in ne2k_pci_block_output()
611 	outb(0x42, nic_base + EN0_RSARLO);  in ne2k_pci_block_output()
612 	outb(0x00, nic_base + EN0_RSARHI);  in ne2k_pci_block_output()
618 	outb(count & 0xff, nic_base + EN0_RCNTLO);  in ne2k_pci_block_output()
620 	outb(0x00, nic_base + EN0_RSARLO);  in ne2k_pci_block_output()
640 	while ((inb(nic_base + EN0_ISR) & ENISR_RDC) == 0)  in ne2k_pci_block_output()
650 	ei_status.dmaing &= ~0x01;  in ne2k_pci_block_output()
701 	return 0;  in ne2k_pci_suspend()
711 	return 0;  in ne2k_pci_resume()