Lines Matching +full:port +full:- +full:mapping +full:- +full:mode
1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Marvell 88E6xxx Switch Port Registers support
7 * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
20 #include "port.h"
23 int mv88e6xxx_port_read(struct mv88e6xxx_chip *chip, int port, int reg, in mv88e6xxx_port_read() argument
26 int addr = chip->info->port_base_addr + port; in mv88e6xxx_port_read()
31 int mv88e6xxx_port_wait_bit(struct mv88e6xxx_chip *chip, int port, int reg, in mv88e6xxx_port_wait_bit() argument
34 int addr = chip->info->port_base_addr + port; in mv88e6xxx_port_wait_bit()
39 int mv88e6xxx_port_write(struct mv88e6xxx_chip *chip, int port, int reg, in mv88e6xxx_port_write() argument
42 int addr = chip->info->port_base_addr + port; in mv88e6xxx_port_write()
52 int mv88e6185_port_set_pause(struct mv88e6xxx_chip *chip, int port, in mv88e6185_port_set_pause() argument
58 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®); in mv88e6185_port_set_pause()
67 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_STS, reg); in mv88e6185_port_set_pause()
74 * For port's MAC speed, ForceSpd (or SpdValue) bits 1:0 program the value.
79 static int mv88e6xxx_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port, in mv88e6xxx_port_set_rgmii_delay() argument
80 phy_interface_t mode) in mv88e6xxx_port_set_rgmii_delay() argument
85 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_MAC_CTL, ®); in mv88e6xxx_port_set_rgmii_delay()
92 switch (mode) { in mv88e6xxx_port_set_rgmii_delay()
109 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_MAC_CTL, reg); in mv88e6xxx_port_set_rgmii_delay()
113 dev_dbg(chip->dev, "p%d: delay RXCLK %s, TXCLK %s\n", port, in mv88e6xxx_port_set_rgmii_delay()
120 int mv88e6352_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port, in mv88e6352_port_set_rgmii_delay() argument
121 phy_interface_t mode) in mv88e6352_port_set_rgmii_delay() argument
123 if (port < 5) in mv88e6352_port_set_rgmii_delay()
124 return -EOPNOTSUPP; in mv88e6352_port_set_rgmii_delay()
126 return mv88e6xxx_port_set_rgmii_delay(chip, port, mode); in mv88e6352_port_set_rgmii_delay()
129 int mv88e6390_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port, in mv88e6390_port_set_rgmii_delay() argument
130 phy_interface_t mode) in mv88e6390_port_set_rgmii_delay() argument
132 if (port != 0) in mv88e6390_port_set_rgmii_delay()
133 return -EOPNOTSUPP; in mv88e6390_port_set_rgmii_delay()
135 return mv88e6xxx_port_set_rgmii_delay(chip, port, mode); in mv88e6390_port_set_rgmii_delay()
138 int mv88e6320_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port, in mv88e6320_port_set_rgmii_delay() argument
139 phy_interface_t mode) in mv88e6320_port_set_rgmii_delay() argument
141 if (port != 2 && port != 5 && port != 6) in mv88e6320_port_set_rgmii_delay()
142 return -EOPNOTSUPP; in mv88e6320_port_set_rgmii_delay()
144 return mv88e6xxx_port_set_rgmii_delay(chip, port, mode); in mv88e6320_port_set_rgmii_delay()
147 int mv88e6xxx_port_set_link(struct mv88e6xxx_chip *chip, int port, int link) in mv88e6xxx_port_set_link() argument
152 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_MAC_CTL, ®); in mv88e6xxx_port_set_link()
171 return -EINVAL; in mv88e6xxx_port_set_link()
174 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_MAC_CTL, reg); in mv88e6xxx_port_set_link()
178 dev_dbg(chip->dev, "p%d: %s link %s\n", port, in mv88e6xxx_port_set_link()
185 int mv88e6xxx_port_sync_link(struct mv88e6xxx_chip *chip, int port, unsigned int mode, bool isup) in mv88e6xxx_port_sync_link() argument
187 const struct mv88e6xxx_ops *ops = chip->info->ops; in mv88e6xxx_port_sync_link()
196 if (ops->port_set_link) in mv88e6xxx_port_sync_link()
197 err = ops->port_set_link(chip, port, link); in mv88e6xxx_port_sync_link()
202 int mv88e6185_port_sync_link(struct mv88e6xxx_chip *chip, int port, unsigned int mode, bool isup) in mv88e6185_port_sync_link() argument
204 const struct mv88e6xxx_ops *ops = chip->info->ops; in mv88e6185_port_sync_link()
208 if (mode == MLO_AN_INBAND) in mv88e6185_port_sync_link()
215 if (ops->port_set_link) in mv88e6185_port_sync_link()
216 err = ops->port_set_link(chip, port, link); in mv88e6185_port_sync_link()
222 int port, int speed, bool alt_bit, in mv88e6xxx_port_set_speed_duplex() argument
258 return -EOPNOTSUPP; in mv88e6xxx_port_set_speed_duplex()
273 return -EOPNOTSUPP; in mv88e6xxx_port_set_speed_duplex()
276 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_MAC_CTL, ®); in mv88e6xxx_port_set_speed_duplex()
293 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_MAC_CTL, reg); in mv88e6xxx_port_set_speed_duplex()
298 dev_dbg(chip->dev, "p%d: Speed set to %d Mbps\n", port, speed); in mv88e6xxx_port_set_speed_duplex()
300 dev_dbg(chip->dev, "p%d: Speed unforced\n", port); in mv88e6xxx_port_set_speed_duplex()
301 dev_dbg(chip->dev, "p%d: %s %s duplex\n", port, in mv88e6xxx_port_set_speed_duplex()
309 int mv88e6185_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port, in mv88e6185_port_set_speed_duplex() argument
313 return -EOPNOTSUPP; in mv88e6185_port_set_speed_duplex()
315 return mv88e6xxx_port_set_speed_duplex(chip, port, speed, false, false, in mv88e6185_port_set_speed_duplex()
320 int mv88e6250_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port, in mv88e6250_port_set_speed_duplex() argument
324 return -EOPNOTSUPP; in mv88e6250_port_set_speed_duplex()
326 return mv88e6xxx_port_set_speed_duplex(chip, port, speed, false, false, in mv88e6250_port_set_speed_duplex()
331 int mv88e6341_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port, in mv88e6341_port_set_speed_duplex() argument
335 return -EOPNOTSUPP; in mv88e6341_port_set_speed_duplex()
337 if (speed == 200 && port != 0) in mv88e6341_port_set_speed_duplex()
338 return -EOPNOTSUPP; in mv88e6341_port_set_speed_duplex()
340 if (speed == 2500 && port < 5) in mv88e6341_port_set_speed_duplex()
341 return -EOPNOTSUPP; in mv88e6341_port_set_speed_duplex()
343 return mv88e6xxx_port_set_speed_duplex(chip, port, speed, !port, true, in mv88e6341_port_set_speed_duplex()
348 int port) in mv88e6341_port_max_speed_mode() argument
350 if (port == 5) in mv88e6341_port_max_speed_mode()
357 int mv88e6352_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port, in mv88e6352_port_set_speed_duplex() argument
361 return -EOPNOTSUPP; in mv88e6352_port_set_speed_duplex()
363 if (speed == 200 && port < 5) in mv88e6352_port_set_speed_duplex()
364 return -EOPNOTSUPP; in mv88e6352_port_set_speed_duplex()
366 return mv88e6xxx_port_set_speed_duplex(chip, port, speed, true, false, in mv88e6352_port_set_speed_duplex()
371 int mv88e6390_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port, in mv88e6390_port_set_speed_duplex() argument
375 return -EOPNOTSUPP; in mv88e6390_port_set_speed_duplex()
377 if (speed == 200 && port != 0) in mv88e6390_port_set_speed_duplex()
378 return -EOPNOTSUPP; in mv88e6390_port_set_speed_duplex()
380 if (speed == 2500 && port < 9) in mv88e6390_port_set_speed_duplex()
381 return -EOPNOTSUPP; in mv88e6390_port_set_speed_duplex()
383 return mv88e6xxx_port_set_speed_duplex(chip, port, speed, true, true, in mv88e6390_port_set_speed_duplex()
388 int port) in mv88e6390_port_max_speed_mode() argument
390 if (port == 9 || port == 10) in mv88e6390_port_max_speed_mode()
397 int mv88e6390x_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port, in mv88e6390x_port_set_speed_duplex() argument
400 if (speed == 200 && port != 0) in mv88e6390x_port_set_speed_duplex()
401 return -EOPNOTSUPP; in mv88e6390x_port_set_speed_duplex()
403 if (speed >= 2500 && port < 9) in mv88e6390x_port_set_speed_duplex()
404 return -EOPNOTSUPP; in mv88e6390x_port_set_speed_duplex()
406 return mv88e6xxx_port_set_speed_duplex(chip, port, speed, true, true, in mv88e6390x_port_set_speed_duplex()
411 int port) in mv88e6390x_port_max_speed_mode() argument
413 if (port == 9 || port == 10) in mv88e6390x_port_max_speed_mode()
423 int mv88e6393x_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port, in mv88e6393x_port_set_speed_duplex() argument
429 if (chip->info->prod_num == MV88E6XXX_PORT_SWITCH_ID_PROD_6361 && in mv88e6393x_port_set_speed_duplex()
431 return -EOPNOTSUPP; in mv88e6393x_port_set_speed_duplex()
433 if (speed == 200 && port != 0) in mv88e6393x_port_set_speed_duplex()
434 return -EOPNOTSUPP; in mv88e6393x_port_set_speed_duplex()
436 if (speed >= 2500 && port > 0 && port < 9) in mv88e6393x_port_set_speed_duplex()
437 return -EOPNOTSUPP; in mv88e6393x_port_set_speed_duplex()
466 return -EOPNOTSUPP; in mv88e6393x_port_set_speed_duplex()
481 return -EOPNOTSUPP; in mv88e6393x_port_set_speed_duplex()
484 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_MAC_CTL, ®); in mv88e6393x_port_set_speed_duplex()
497 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_MAC_CTL, reg); in mv88e6393x_port_set_speed_duplex()
502 dev_dbg(chip->dev, "p%d: Speed set to %d Mbps\n", port, speed); in mv88e6393x_port_set_speed_duplex()
504 dev_dbg(chip->dev, "p%d: Speed unforced\n", port); in mv88e6393x_port_set_speed_duplex()
505 dev_dbg(chip->dev, "p%d: %s %s duplex\n", port, in mv88e6393x_port_set_speed_duplex()
513 int port) in mv88e6393x_port_max_speed_mode() argument
516 if (port != 0 && port != 9 && port != 10) in mv88e6393x_port_max_speed_mode()
519 if (chip->info->prod_num == MV88E6XXX_PORT_SWITCH_ID_PROD_6361) in mv88e6393x_port_max_speed_mode()
525 static int mv88e6xxx_port_set_cmode(struct mv88e6xxx_chip *chip, int port, in mv88e6xxx_port_set_cmode() argument
526 phy_interface_t mode, bool force) in mv88e6xxx_port_set_cmode() argument
532 /* Default to a slow mode, so freeing up SERDES interfaces for in mv88e6xxx_port_set_cmode()
535 if (mode == PHY_INTERFACE_MODE_NA) in mv88e6xxx_port_set_cmode()
536 mode = PHY_INTERFACE_MODE_1000BASEX; in mv88e6xxx_port_set_cmode()
538 switch (mode) { in mv88e6xxx_port_set_cmode()
578 if (cmode == chip->ports[port].cmode && !force) in mv88e6xxx_port_set_cmode()
581 chip->ports[port].cmode = 0; in mv88e6xxx_port_set_cmode()
584 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®); in mv88e6xxx_port_set_cmode()
591 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_STS, reg); in mv88e6xxx_port_set_cmode()
595 chip->ports[port].cmode = cmode; in mv88e6xxx_port_set_cmode()
601 int mv88e6390x_port_set_cmode(struct mv88e6xxx_chip *chip, int port, in mv88e6390x_port_set_cmode() argument
602 phy_interface_t mode) in mv88e6390x_port_set_cmode() argument
604 if (port != 9 && port != 10) in mv88e6390x_port_set_cmode()
605 return -EOPNOTSUPP; in mv88e6390x_port_set_cmode()
607 return mv88e6xxx_port_set_cmode(chip, port, mode, false); in mv88e6390x_port_set_cmode()
610 int mv88e6390_port_set_cmode(struct mv88e6xxx_chip *chip, int port, in mv88e6390_port_set_cmode() argument
611 phy_interface_t mode) in mv88e6390_port_set_cmode() argument
613 if (port != 9 && port != 10) in mv88e6390_port_set_cmode()
614 return -EOPNOTSUPP; in mv88e6390_port_set_cmode()
616 switch (mode) { in mv88e6390_port_set_cmode()
622 return -EINVAL; in mv88e6390_port_set_cmode()
627 return mv88e6xxx_port_set_cmode(chip, port, mode, false); in mv88e6390_port_set_cmode()
630 int mv88e6393x_port_set_cmode(struct mv88e6xxx_chip *chip, int port, in mv88e6393x_port_set_cmode() argument
631 phy_interface_t mode) in mv88e6393x_port_set_cmode() argument
636 if (port != 0 && port != 9 && port != 10) in mv88e6393x_port_set_cmode()
637 return -EOPNOTSUPP; in mv88e6393x_port_set_cmode()
639 if (port == 9 || port == 10) { in mv88e6393x_port_set_cmode()
640 switch (mode) { in mv88e6393x_port_set_cmode()
646 return -EINVAL; in mv88e6393x_port_set_cmode()
653 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_MAC_CTL, ®); in mv88e6393x_port_set_cmode()
659 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_MAC_CTL, reg); in mv88e6393x_port_set_cmode()
663 return mv88e6xxx_port_set_cmode(chip, port, mode, false); in mv88e6393x_port_set_cmode()
667 int port) in mv88e6341_port_set_cmode_writable() argument
672 if (port != 5) in mv88e6341_port_set_cmode_writable()
673 return -EOPNOTSUPP; in mv88e6341_port_set_cmode_writable()
675 addr = chip->info->port_base_addr + port; in mv88e6341_port_set_cmode_writable()
691 int mv88e6341_port_set_cmode(struct mv88e6xxx_chip *chip, int port, in mv88e6341_port_set_cmode() argument
692 phy_interface_t mode) in mv88e6341_port_set_cmode() argument
696 if (port != 5) in mv88e6341_port_set_cmode()
697 return -EOPNOTSUPP; in mv88e6341_port_set_cmode()
699 switch (mode) { in mv88e6341_port_set_cmode()
705 return -EINVAL; in mv88e6341_port_set_cmode()
710 err = mv88e6341_port_set_cmode_writable(chip, port); in mv88e6341_port_set_cmode()
714 return mv88e6xxx_port_set_cmode(chip, port, mode, true); in mv88e6341_port_set_cmode()
717 int mv88e6185_port_get_cmode(struct mv88e6xxx_chip *chip, int port, u8 *cmode) in mv88e6185_port_get_cmode() argument
722 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®); in mv88e6185_port_get_cmode()
731 int mv88e6352_port_get_cmode(struct mv88e6xxx_chip *chip, int port, u8 *cmode) in mv88e6352_port_get_cmode() argument
736 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®); in mv88e6352_port_get_cmode()
747 * Do not limit the period of time that this port can be paused for by
748 * the remote end or the period of time that this port can pause the
751 int mv88e6097_port_pause_limit(struct mv88e6xxx_chip *chip, int port, u8 in, in mv88e6097_port_pause_limit() argument
754 return mv88e6xxx_port_write(chip, port, MV88E6097_PORT_JAM_CTL, in mv88e6097_port_pause_limit()
758 int mv88e6390_port_pause_limit(struct mv88e6xxx_chip *chip, int port, u8 in, in mv88e6390_port_pause_limit() argument
763 err = mv88e6xxx_port_write(chip, port, MV88E6390_PORT_FLOW_CTL, in mv88e6390_port_pause_limit()
769 return mv88e6xxx_port_write(chip, port, MV88E6390_PORT_FLOW_CTL, in mv88e6390_port_pause_limit()
774 /* Offset 0x04: Port Control Register */
783 int mv88e6xxx_port_set_state(struct mv88e6xxx_chip *chip, int port, u8 state) in mv88e6xxx_port_set_state() argument
788 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®); in mv88e6xxx_port_set_state()
809 return -EINVAL; in mv88e6xxx_port_set_state()
814 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); in mv88e6xxx_port_set_state()
818 dev_dbg(chip->dev, "p%d: PortState set to %s\n", port, in mv88e6xxx_port_set_state()
824 int mv88e6xxx_port_set_egress_mode(struct mv88e6xxx_chip *chip, int port, in mv88e6xxx_port_set_egress_mode() argument
825 enum mv88e6xxx_egress_mode mode) in mv88e6xxx_port_set_egress_mode() argument
830 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®); in mv88e6xxx_port_set_egress_mode()
836 switch (mode) { in mv88e6xxx_port_set_egress_mode()
850 return -EINVAL; in mv88e6xxx_port_set_egress_mode()
853 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); in mv88e6xxx_port_set_egress_mode()
856 int mv88e6085_port_set_frame_mode(struct mv88e6xxx_chip *chip, int port, in mv88e6085_port_set_frame_mode() argument
857 enum mv88e6xxx_frame_mode mode) in mv88e6085_port_set_frame_mode() argument
862 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®); in mv88e6085_port_set_frame_mode()
868 switch (mode) { in mv88e6085_port_set_frame_mode()
876 return -EINVAL; in mv88e6085_port_set_frame_mode()
879 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); in mv88e6085_port_set_frame_mode()
882 int mv88e6351_port_set_frame_mode(struct mv88e6xxx_chip *chip, int port, in mv88e6351_port_set_frame_mode() argument
883 enum mv88e6xxx_frame_mode mode) in mv88e6351_port_set_frame_mode() argument
888 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®); in mv88e6351_port_set_frame_mode()
894 switch (mode) { in mv88e6351_port_set_frame_mode()
908 return -EINVAL; in mv88e6351_port_set_frame_mode()
911 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); in mv88e6351_port_set_frame_mode()
915 int port, bool unicast) in mv88e6185_port_set_forward_unknown() argument
920 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®); in mv88e6185_port_set_forward_unknown()
929 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); in mv88e6185_port_set_forward_unknown()
932 int mv88e6352_port_set_ucast_flood(struct mv88e6xxx_chip *chip, int port, in mv88e6352_port_set_ucast_flood() argument
938 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®); in mv88e6352_port_set_ucast_flood()
947 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); in mv88e6352_port_set_ucast_flood()
950 int mv88e6352_port_set_mcast_flood(struct mv88e6xxx_chip *chip, int port, in mv88e6352_port_set_mcast_flood() argument
956 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®); in mv88e6352_port_set_mcast_flood()
965 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); in mv88e6352_port_set_mcast_flood()
968 /* Offset 0x05: Port Control 1 */
970 int mv88e6xxx_port_set_message_port(struct mv88e6xxx_chip *chip, int port, in mv88e6xxx_port_set_message_port() argument
976 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL1, &val); in mv88e6xxx_port_set_message_port()
985 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL1, val); in mv88e6xxx_port_set_message_port()
988 int mv88e6xxx_port_set_trunk(struct mv88e6xxx_chip *chip, int port, in mv88e6xxx_port_set_trunk() argument
994 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL1, &val); in mv88e6xxx_port_set_trunk()
1006 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL1, val); in mv88e6xxx_port_set_trunk()
1009 /* Offset 0x06: Port Based VLAN Map */
1011 int mv88e6xxx_port_set_vlan_map(struct mv88e6xxx_chip *chip, int port, u16 map) in mv88e6xxx_port_set_vlan_map() argument
1017 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_BASE_VLAN, ®); in mv88e6xxx_port_set_vlan_map()
1024 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_BASE_VLAN, reg); in mv88e6xxx_port_set_vlan_map()
1028 dev_dbg(chip->dev, "p%d: VLANTable set to %.3x\n", port, map); in mv88e6xxx_port_set_vlan_map()
1033 int mv88e6xxx_port_get_fid(struct mv88e6xxx_chip *chip, int port, u16 *fid) in mv88e6xxx_port_get_fid() argument
1035 const u16 upper_mask = (mv88e6xxx_num_databases(chip) - 1) >> 4; in mv88e6xxx_port_get_fid()
1039 /* Port's default FID lower 4 bits are located in reg 0x06, offset 12 */ in mv88e6xxx_port_get_fid()
1040 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_BASE_VLAN, ®); in mv88e6xxx_port_get_fid()
1046 /* Port's default FID upper bits are located in reg 0x05, offset 0 */ in mv88e6xxx_port_get_fid()
1048 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL1, in mv88e6xxx_port_get_fid()
1059 int mv88e6xxx_port_set_fid(struct mv88e6xxx_chip *chip, int port, u16 fid) in mv88e6xxx_port_set_fid() argument
1061 const u16 upper_mask = (mv88e6xxx_num_databases(chip) - 1) >> 4; in mv88e6xxx_port_set_fid()
1066 return -EINVAL; in mv88e6xxx_port_set_fid()
1068 /* Port's default FID lower 4 bits are located in reg 0x06, offset 12 */ in mv88e6xxx_port_set_fid()
1069 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_BASE_VLAN, ®); in mv88e6xxx_port_set_fid()
1076 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_BASE_VLAN, reg); in mv88e6xxx_port_set_fid()
1080 /* Port's default FID upper bits are located in reg 0x05, offset 0 */ in mv88e6xxx_port_set_fid()
1082 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL1, in mv88e6xxx_port_set_fid()
1090 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL1, in mv88e6xxx_port_set_fid()
1096 dev_dbg(chip->dev, "p%d: FID set to %u\n", port, fid); in mv88e6xxx_port_set_fid()
1101 /* Offset 0x07: Default Port VLAN ID & Priority */
1103 int mv88e6xxx_port_get_pvid(struct mv88e6xxx_chip *chip, int port, u16 *pvid) in mv88e6xxx_port_get_pvid() argument
1108 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, in mv88e6xxx_port_get_pvid()
1118 int mv88e6xxx_port_set_pvid(struct mv88e6xxx_chip *chip, int port, u16 pvid) in mv88e6xxx_port_set_pvid() argument
1123 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, in mv88e6xxx_port_set_pvid()
1131 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, in mv88e6xxx_port_set_pvid()
1136 dev_dbg(chip->dev, "p%d: DefaultVID set to %u\n", port, pvid); in mv88e6xxx_port_set_pvid()
1141 /* Offset 0x08: Port Control 2 Register */
1151 int port, bool multicast) in mv88e6185_port_set_default_forward() argument
1156 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®); in mv88e6185_port_set_default_forward()
1165 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg); in mv88e6185_port_set_default_forward()
1168 int mv88e6095_port_set_upstream_port(struct mv88e6xxx_chip *chip, int port, in mv88e6095_port_set_upstream_port() argument
1174 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®); in mv88e6095_port_set_upstream_port()
1181 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg); in mv88e6095_port_set_upstream_port()
1184 int mv88e6xxx_port_set_mirror(struct mv88e6xxx_chip *chip, int port, in mv88e6xxx_port_set_mirror() argument
1193 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®); in mv88e6xxx_port_set_mirror()
1200 mirror_port = &chip->ports[port].mirror_ingress; in mv88e6xxx_port_set_mirror()
1204 mirror_port = &chip->ports[port].mirror_egress; in mv88e6xxx_port_set_mirror()
1207 return -EINVAL; in mv88e6xxx_port_set_mirror()
1214 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg); in mv88e6xxx_port_set_mirror()
1221 int mv88e6xxx_port_set_lock(struct mv88e6xxx_chip *chip, int port, in mv88e6xxx_port_set_lock() argument
1227 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®); in mv88e6xxx_port_set_lock()
1235 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); in mv88e6xxx_port_set_lock()
1239 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR, ®); in mv88e6xxx_port_set_lock()
1247 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR, reg); in mv88e6xxx_port_set_lock()
1250 int mv88e6xxx_port_set_8021q_mode(struct mv88e6xxx_chip *chip, int port, in mv88e6xxx_port_set_8021q_mode() argument
1251 u16 mode) in mv88e6xxx_port_set_8021q_mode() argument
1256 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®); in mv88e6xxx_port_set_8021q_mode()
1261 reg |= mode & MV88E6XXX_PORT_CTL2_8021Q_MODE_MASK; in mv88e6xxx_port_set_8021q_mode()
1263 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg); in mv88e6xxx_port_set_8021q_mode()
1267 dev_dbg(chip->dev, "p%d: 802.1QMode set to %s\n", port, in mv88e6xxx_port_set_8021q_mode()
1268 mv88e6xxx_port_8021q_mode_names[mode]); in mv88e6xxx_port_set_8021q_mode()
1273 int mv88e6xxx_port_drop_untagged(struct mv88e6xxx_chip *chip, int port, in mv88e6xxx_port_drop_untagged() argument
1279 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, &old); in mv88e6xxx_port_drop_untagged()
1291 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, new); in mv88e6xxx_port_drop_untagged()
1294 int mv88e6xxx_port_set_map_da(struct mv88e6xxx_chip *chip, int port, bool map) in mv88e6xxx_port_set_map_da() argument
1299 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®); in mv88e6xxx_port_set_map_da()
1308 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg); in mv88e6xxx_port_set_map_da()
1311 int mv88e6165_port_set_jumbo_size(struct mv88e6xxx_chip *chip, int port, in mv88e6165_port_set_jumbo_size() argument
1319 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®); in mv88e6165_port_set_jumbo_size()
1332 return -ERANGE; in mv88e6165_port_set_jumbo_size()
1334 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg); in mv88e6165_port_set_jumbo_size()
1337 /* Offset 0x09: Port Rate Control */
1339 int mv88e6095_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port) in mv88e6095_port_egress_rate_limiting() argument
1341 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL1, in mv88e6095_port_egress_rate_limiting()
1345 int mv88e6097_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port) in mv88e6097_port_egress_rate_limiting() argument
1347 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL1, in mv88e6097_port_egress_rate_limiting()
1351 /* Offset 0x0B: Port Association Vector */
1353 int mv88e6xxx_port_set_assoc_vector(struct mv88e6xxx_chip *chip, int port, in mv88e6xxx_port_set_assoc_vector() argument
1359 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR, in mv88e6xxx_port_set_assoc_vector()
1368 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR, in mv88e6xxx_port_set_assoc_vector()
1372 /* Offset 0x0C: Port ATU Control */
1374 int mv88e6xxx_port_disable_learn_limit(struct mv88e6xxx_chip *chip, int port) in mv88e6xxx_port_disable_learn_limit() argument
1376 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ATU_CTL, 0); in mv88e6xxx_port_disable_learn_limit()
1381 int mv88e6xxx_port_disable_pri_override(struct mv88e6xxx_chip *chip, int port) in mv88e6xxx_port_disable_pri_override() argument
1383 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_PRI_OVERRIDE, 0); in mv88e6xxx_port_disable_pri_override()
1388 static int mv88e6393x_port_policy_read(struct mv88e6xxx_chip *chip, int port, in mv88e6393x_port_policy_read() argument
1394 err = mv88e6xxx_port_write(chip, port, MV88E6393X_PORT_POLICY_MGMT_CTL, in mv88e6393x_port_policy_read()
1399 err = mv88e6xxx_port_read(chip, port, MV88E6393X_PORT_POLICY_MGMT_CTL, in mv88e6393x_port_policy_read()
1409 static int mv88e6393x_port_policy_write(struct mv88e6xxx_chip *chip, int port, in mv88e6393x_port_policy_write() argument
1416 return mv88e6xxx_port_write(chip, port, MV88E6393X_PORT_POLICY_MGMT_CTL, in mv88e6393x_port_policy_write()
1423 int err, port; in mv88e6393x_port_policy_write_all() local
1425 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { in mv88e6393x_port_policy_write_all()
1426 if (dsa_is_unused_port(chip->ds, port)) in mv88e6393x_port_policy_write_all()
1429 err = mv88e6393x_port_policy_write(chip, port, pointer, data); in mv88e6393x_port_policy_write_all()
1439 int port) in mv88e6393x_set_egress_port() argument
1447 err = mv88e6393x_port_policy_write_all(chip, ptr, port); in mv88e6393x_set_egress_port()
1453 err = mv88e6xxx_g2_write(chip, ptr, port); in mv88e6393x_set_egress_port()
1462 int mv88e6393x_port_set_upstream_port(struct mv88e6xxx_chip *chip, int port, in mv88e6393x_port_set_upstream_port() argument
1469 return mv88e6393x_port_policy_write(chip, port, ptr, data); in mv88e6393x_port_set_upstream_port()
1506 static int mv88e6393x_port_epc_wait_ready(struct mv88e6xxx_chip *chip, int port) in mv88e6393x_port_epc_wait_ready() argument
1510 return mv88e6xxx_port_wait_bit(chip, port, MV88E6393X_PORT_EPC_CMD, bit, 0); in mv88e6393x_port_epc_wait_ready()
1513 /* Port Ether type for 6393X family */
1515 int mv88e6393x_port_set_ether_type(struct mv88e6xxx_chip *chip, int port, in mv88e6393x_port_set_ether_type() argument
1521 err = mv88e6393x_port_epc_wait_ready(chip, port); in mv88e6393x_port_set_ether_type()
1525 err = mv88e6xxx_port_write(chip, port, MV88E6393X_PORT_EPC_DATA, etype); in mv88e6393x_port_set_ether_type()
1533 return mv88e6xxx_port_write(chip, port, MV88E6393X_PORT_EPC_CMD, val); in mv88e6393x_port_set_ether_type()
1536 /* Offset 0x0f: Port Ether type */
1538 int mv88e6351_port_set_ether_type(struct mv88e6xxx_chip *chip, int port, in mv88e6351_port_set_ether_type() argument
1541 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ETH_TYPE, etype); in mv88e6351_port_set_ether_type()
1544 /* Offset 0x18: Port IEEE Priority Remapping Registers [0-3]
1545 * Offset 0x19: Port IEEE Priority Remapping Registers [4-7]
1548 int mv88e6095_port_tag_remap(struct mv88e6xxx_chip *chip, int port) in mv88e6095_port_tag_remap() argument
1552 /* Use a direct priority mapping for all IEEE tagged frames */ in mv88e6095_port_tag_remap()
1553 err = mv88e6xxx_port_write(chip, port, in mv88e6095_port_tag_remap()
1559 return mv88e6xxx_port_write(chip, port, in mv88e6095_port_tag_remap()
1565 int port, u16 table, u8 ptr, u16 data) in mv88e6xxx_port_ieeepmt_write() argument
1573 return mv88e6xxx_port_write(chip, port, in mv88e6xxx_port_ieeepmt_write()
1577 int mv88e6390_port_tag_remap(struct mv88e6xxx_chip *chip, int port) in mv88e6390_port_tag_remap() argument
1584 err = mv88e6xxx_port_ieeepmt_write(chip, port, table, i, in mv88e6390_port_tag_remap()
1590 err = mv88e6xxx_port_ieeepmt_write(chip, port, table, i, i); in mv88e6390_port_tag_remap()
1595 err = mv88e6xxx_port_ieeepmt_write(chip, port, table, i, i); in mv88e6390_port_tag_remap()
1600 err = mv88e6xxx_port_ieeepmt_write(chip, port, table, i, i); in mv88e6390_port_tag_remap()
1611 mv88e6xxx_port_policy_mapping_get_pos(enum mv88e6xxx_policy_mapping mapping, in mv88e6xxx_port_policy_mapping_get_pos() argument
1615 switch (mapping) { in mv88e6xxx_port_policy_mapping_get_pos()
1649 return -EOPNOTSUPP; in mv88e6xxx_port_policy_mapping_get_pos()
1666 return -EOPNOTSUPP; in mv88e6xxx_port_policy_mapping_get_pos()
1672 int mv88e6352_port_set_policy(struct mv88e6xxx_chip *chip, int port, in mv88e6352_port_set_policy() argument
1673 enum mv88e6xxx_policy_mapping mapping, in mv88e6352_port_set_policy() argument
1680 err = mv88e6xxx_port_policy_mapping_get_pos(mapping, action, &mask, in mv88e6352_port_set_policy()
1685 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_POLICY_CTL, ®); in mv88e6352_port_set_policy()
1692 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_POLICY_CTL, reg); in mv88e6352_port_set_policy()
1695 int mv88e6393x_port_set_policy(struct mv88e6xxx_chip *chip, int port, in mv88e6393x_port_set_policy() argument
1696 enum mv88e6xxx_policy_mapping mapping, in mv88e6393x_port_set_policy() argument
1705 err = mv88e6xxx_port_policy_mapping_get_pos(mapping, action, &mask, in mv88e6393x_port_set_policy()
1710 /* The 16-bit Port Policy CTL register from older chips is on 6393x in mv88e6393x_port_set_policy()
1711 * changed to Port Policy MGMT CTL, which can access more data, but in mv88e6393x_port_set_policy()
1712 * indirectly. The original 16-bit value is divided into two 8-bit in mv88e6393x_port_set_policy()
1720 err = mv88e6393x_port_policy_read(chip, port, ptr, ®); in mv88e6393x_port_set_policy()
1727 return mv88e6393x_port_policy_write(chip, port, ptr, reg); in mv88e6393x_port_set_policy()