Lines Matching +full:mode +full:- +full:reg
1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
23 int mv88e6xxx_port_read(struct mv88e6xxx_chip *chip, int port, int reg, in mv88e6xxx_port_read() argument
26 int addr = chip->info->port_base_addr + port; in mv88e6xxx_port_read()
28 return mv88e6xxx_read(chip, addr, reg, val); in mv88e6xxx_port_read()
31 int mv88e6xxx_port_wait_bit(struct mv88e6xxx_chip *chip, int port, int reg, in mv88e6xxx_port_wait_bit() argument
34 int addr = chip->info->port_base_addr + port; in mv88e6xxx_port_wait_bit()
36 return mv88e6xxx_wait_bit(chip, addr, reg, bit, val); in mv88e6xxx_port_wait_bit()
39 int mv88e6xxx_port_write(struct mv88e6xxx_chip *chip, int port, int reg, in mv88e6xxx_port_write() argument
42 int addr = chip->info->port_base_addr + port; in mv88e6xxx_port_write()
44 return mv88e6xxx_write(chip, addr, reg, val); in mv88e6xxx_port_write()
55 u16 reg; in mv88e6185_port_set_pause() local
58 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®); in mv88e6185_port_set_pause()
63 reg |= MV88E6XXX_PORT_STS_MY_PAUSE; in mv88e6185_port_set_pause()
65 reg &= ~MV88E6XXX_PORT_STS_MY_PAUSE; in mv88e6185_port_set_pause()
67 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_STS, reg); in mv88e6185_port_set_pause()
80 phy_interface_t mode) in mv88e6xxx_port_set_rgmii_delay() argument
82 u16 reg; in mv88e6xxx_port_set_rgmii_delay() local
85 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_MAC_CTL, ®); in mv88e6xxx_port_set_rgmii_delay()
89 reg &= ~(MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK | in mv88e6xxx_port_set_rgmii_delay()
92 switch (mode) { in mv88e6xxx_port_set_rgmii_delay()
94 reg |= MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK; in mv88e6xxx_port_set_rgmii_delay()
97 reg |= MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_TXCLK; in mv88e6xxx_port_set_rgmii_delay()
100 reg |= MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK | in mv88e6xxx_port_set_rgmii_delay()
109 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_MAC_CTL, reg); in mv88e6xxx_port_set_rgmii_delay()
113 dev_dbg(chip->dev, "p%d: delay RXCLK %s, TXCLK %s\n", port, in mv88e6xxx_port_set_rgmii_delay()
114 reg & MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK ? "yes" : "no", in mv88e6xxx_port_set_rgmii_delay()
115 reg & MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_TXCLK ? "yes" : "no"); in mv88e6xxx_port_set_rgmii_delay()
121 phy_interface_t mode) in mv88e6352_port_set_rgmii_delay() argument
124 return -EOPNOTSUPP; in mv88e6352_port_set_rgmii_delay()
126 return mv88e6xxx_port_set_rgmii_delay(chip, port, mode); in mv88e6352_port_set_rgmii_delay()
130 phy_interface_t mode) in mv88e6390_port_set_rgmii_delay() argument
133 return -EOPNOTSUPP; in mv88e6390_port_set_rgmii_delay()
135 return mv88e6xxx_port_set_rgmii_delay(chip, port, mode); in mv88e6390_port_set_rgmii_delay()
139 phy_interface_t mode) in mv88e6320_port_set_rgmii_delay() argument
142 return -EOPNOTSUPP; in mv88e6320_port_set_rgmii_delay()
144 return mv88e6xxx_port_set_rgmii_delay(chip, port, mode); in mv88e6320_port_set_rgmii_delay()
149 u16 reg; in mv88e6xxx_port_set_link() local
152 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_MAC_CTL, ®); in mv88e6xxx_port_set_link()
156 reg &= ~(MV88E6XXX_PORT_MAC_CTL_FORCE_LINK | in mv88e6xxx_port_set_link()
161 reg |= MV88E6XXX_PORT_MAC_CTL_FORCE_LINK; in mv88e6xxx_port_set_link()
164 reg |= MV88E6XXX_PORT_MAC_CTL_FORCE_LINK | in mv88e6xxx_port_set_link()
171 return -EINVAL; in mv88e6xxx_port_set_link()
174 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_MAC_CTL, reg); in mv88e6xxx_port_set_link()
178 dev_dbg(chip->dev, "p%d: %s link %s\n", port, in mv88e6xxx_port_set_link()
179 reg & MV88E6XXX_PORT_MAC_CTL_FORCE_LINK ? "Force" : "Unforce", in mv88e6xxx_port_set_link()
180 str_up_down(reg & MV88E6XXX_PORT_MAC_CTL_LINK_UP)); in mv88e6xxx_port_set_link()
185 int mv88e6xxx_port_sync_link(struct mv88e6xxx_chip *chip, int port, unsigned int mode, bool isup) in mv88e6xxx_port_sync_link() argument
187 const struct mv88e6xxx_ops *ops = chip->info->ops; in mv88e6xxx_port_sync_link()
196 if (ops->port_set_link) in mv88e6xxx_port_sync_link()
197 err = ops->port_set_link(chip, port, link); in mv88e6xxx_port_sync_link()
202 int mv88e6185_port_sync_link(struct mv88e6xxx_chip *chip, int port, unsigned int mode, bool isup) in mv88e6185_port_sync_link() argument
204 const struct mv88e6xxx_ops *ops = chip->info->ops; in mv88e6185_port_sync_link()
208 if (mode == MLO_AN_INBAND) in mv88e6185_port_sync_link()
215 if (ops->port_set_link) in mv88e6185_port_sync_link()
216 err = ops->port_set_link(chip, port, link); in mv88e6185_port_sync_link()
225 u16 reg, ctrl; in mv88e6xxx_port_set_speed_duplex() local
258 return -EOPNOTSUPP; in mv88e6xxx_port_set_speed_duplex()
273 return -EOPNOTSUPP; in mv88e6xxx_port_set_speed_duplex()
276 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_MAC_CTL, ®); in mv88e6xxx_port_set_speed_duplex()
280 reg &= ~(MV88E6XXX_PORT_MAC_CTL_SPEED_MASK | in mv88e6xxx_port_set_speed_duplex()
285 reg &= ~MV88E6390_PORT_MAC_CTL_ALTSPEED; in mv88e6xxx_port_set_speed_duplex()
287 reg &= ~MV88E6390_PORT_MAC_CTL_FORCE_SPEED; in mv88e6xxx_port_set_speed_duplex()
291 reg |= ctrl; in mv88e6xxx_port_set_speed_duplex()
293 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_MAC_CTL, reg); in mv88e6xxx_port_set_speed_duplex()
298 dev_dbg(chip->dev, "p%d: Speed set to %d Mbps\n", port, speed); in mv88e6xxx_port_set_speed_duplex()
300 dev_dbg(chip->dev, "p%d: Speed unforced\n", port); in mv88e6xxx_port_set_speed_duplex()
301 dev_dbg(chip->dev, "p%d: %s %s duplex\n", port, in mv88e6xxx_port_set_speed_duplex()
302 reg & MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX ? "Force" : "Unforce", in mv88e6xxx_port_set_speed_duplex()
303 reg & MV88E6XXX_PORT_MAC_CTL_DUPLEX_FULL ? "full" : "half"); in mv88e6xxx_port_set_speed_duplex()
313 return -EOPNOTSUPP; in mv88e6185_port_set_speed_duplex()
324 return -EOPNOTSUPP; in mv88e6250_port_set_speed_duplex()
335 return -EOPNOTSUPP; in mv88e6341_port_set_speed_duplex()
338 return -EOPNOTSUPP; in mv88e6341_port_set_speed_duplex()
341 return -EOPNOTSUPP; in mv88e6341_port_set_speed_duplex()
361 return -EOPNOTSUPP; in mv88e6352_port_set_speed_duplex()
364 return -EOPNOTSUPP; in mv88e6352_port_set_speed_duplex()
375 return -EOPNOTSUPP; in mv88e6390_port_set_speed_duplex()
378 return -EOPNOTSUPP; in mv88e6390_port_set_speed_duplex()
381 return -EOPNOTSUPP; in mv88e6390_port_set_speed_duplex()
401 return -EOPNOTSUPP; in mv88e6390x_port_set_speed_duplex()
404 return -EOPNOTSUPP; in mv88e6390x_port_set_speed_duplex()
426 u16 reg, ctrl; in mv88e6393x_port_set_speed_duplex() local
429 if (chip->info->prod_num == MV88E6XXX_PORT_SWITCH_ID_PROD_6361 && in mv88e6393x_port_set_speed_duplex()
431 return -EOPNOTSUPP; in mv88e6393x_port_set_speed_duplex()
434 return -EOPNOTSUPP; in mv88e6393x_port_set_speed_duplex()
437 return -EOPNOTSUPP; in mv88e6393x_port_set_speed_duplex()
466 return -EOPNOTSUPP; in mv88e6393x_port_set_speed_duplex()
481 return -EOPNOTSUPP; in mv88e6393x_port_set_speed_duplex()
484 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_MAC_CTL, ®); in mv88e6393x_port_set_speed_duplex()
488 reg &= ~(MV88E6XXX_PORT_MAC_CTL_SPEED_MASK | in mv88e6393x_port_set_speed_duplex()
493 reg |= MV88E6390_PORT_MAC_CTL_FORCE_SPEED; in mv88e6393x_port_set_speed_duplex()
495 reg |= ctrl; in mv88e6393x_port_set_speed_duplex()
497 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_MAC_CTL, reg); in mv88e6393x_port_set_speed_duplex()
502 dev_dbg(chip->dev, "p%d: Speed set to %d Mbps\n", port, speed); in mv88e6393x_port_set_speed_duplex()
504 dev_dbg(chip->dev, "p%d: Speed unforced\n", port); in mv88e6393x_port_set_speed_duplex()
505 dev_dbg(chip->dev, "p%d: %s %s duplex\n", port, in mv88e6393x_port_set_speed_duplex()
506 reg & MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX ? "Force" : "Unforce", in mv88e6393x_port_set_speed_duplex()
507 reg & MV88E6XXX_PORT_MAC_CTL_DUPLEX_FULL ? "full" : "half"); in mv88e6393x_port_set_speed_duplex()
519 if (chip->info->prod_num == MV88E6XXX_PORT_SWITCH_ID_PROD_6361) in mv88e6393x_port_max_speed_mode()
526 phy_interface_t mode, bool force) in mv88e6xxx_port_set_cmode() argument
529 u16 reg; in mv88e6xxx_port_set_cmode() local
532 /* Default to a slow mode, so freeing up SERDES interfaces for in mv88e6xxx_port_set_cmode()
535 if (mode == PHY_INTERFACE_MODE_NA) in mv88e6xxx_port_set_cmode()
536 mode = PHY_INTERFACE_MODE_1000BASEX; in mv88e6xxx_port_set_cmode()
538 switch (mode) { in mv88e6xxx_port_set_cmode()
578 if (cmode == chip->ports[port].cmode && !force) in mv88e6xxx_port_set_cmode()
581 chip->ports[port].cmode = 0; in mv88e6xxx_port_set_cmode()
584 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®); in mv88e6xxx_port_set_cmode()
588 reg &= ~MV88E6XXX_PORT_STS_CMODE_MASK; in mv88e6xxx_port_set_cmode()
589 reg |= cmode; in mv88e6xxx_port_set_cmode()
591 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_STS, reg); in mv88e6xxx_port_set_cmode()
595 chip->ports[port].cmode = cmode; in mv88e6xxx_port_set_cmode()
602 phy_interface_t mode) in mv88e6390x_port_set_cmode() argument
605 return -EOPNOTSUPP; in mv88e6390x_port_set_cmode()
607 return mv88e6xxx_port_set_cmode(chip, port, mode, false); in mv88e6390x_port_set_cmode()
611 phy_interface_t mode) in mv88e6390_port_set_cmode() argument
614 return -EOPNOTSUPP; in mv88e6390_port_set_cmode()
616 switch (mode) { in mv88e6390_port_set_cmode()
622 return -EINVAL; in mv88e6390_port_set_cmode()
627 return mv88e6xxx_port_set_cmode(chip, port, mode, false); in mv88e6390_port_set_cmode()
631 phy_interface_t mode) in mv88e6393x_port_set_cmode() argument
634 u16 reg; in mv88e6393x_port_set_cmode() local
637 return -EOPNOTSUPP; in mv88e6393x_port_set_cmode()
640 switch (mode) { in mv88e6393x_port_set_cmode()
646 return -EINVAL; in mv88e6393x_port_set_cmode()
653 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_MAC_CTL, ®); in mv88e6393x_port_set_cmode()
657 reg &= ~MV88E6XXX_PORT_MAC_CTL_EEE; in mv88e6393x_port_set_cmode()
658 reg |= MV88E6XXX_PORT_MAC_CTL_FORCE_EEE; in mv88e6393x_port_set_cmode()
659 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_MAC_CTL, reg); in mv88e6393x_port_set_cmode()
663 return mv88e6xxx_port_set_cmode(chip, port, mode, false); in mv88e6393x_port_set_cmode()
670 u16 reg, bits; in mv88e6341_port_set_cmode_writable() local
673 return -EOPNOTSUPP; in mv88e6341_port_set_cmode_writable()
675 addr = chip->info->port_base_addr + port; in mv88e6341_port_set_cmode_writable()
677 err = mv88e6xxx_port_hidden_read(chip, 0x7, addr, 0, ®); in mv88e6341_port_set_cmode_writable()
684 if ((reg & bits) == bits) in mv88e6341_port_set_cmode_writable()
687 reg |= bits; in mv88e6341_port_set_cmode_writable()
688 return mv88e6xxx_port_hidden_write(chip, 0x7, addr, 0, reg); in mv88e6341_port_set_cmode_writable()
692 phy_interface_t mode) in mv88e6341_port_set_cmode() argument
697 return -EOPNOTSUPP; in mv88e6341_port_set_cmode()
699 switch (mode) { in mv88e6341_port_set_cmode()
705 return -EINVAL; in mv88e6341_port_set_cmode()
714 return mv88e6xxx_port_set_cmode(chip, port, mode, true); in mv88e6341_port_set_cmode()
720 u16 reg; in mv88e6185_port_get_cmode() local
722 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®); in mv88e6185_port_get_cmode()
726 *cmode = reg & MV88E6185_PORT_STS_CMODE_MASK; in mv88e6185_port_get_cmode()
734 u16 reg; in mv88e6352_port_get_cmode() local
736 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®); in mv88e6352_port_get_cmode()
740 *cmode = reg & MV88E6XXX_PORT_STS_CMODE_MASK; in mv88e6352_port_get_cmode()
785 u16 reg; in mv88e6xxx_port_set_state() local
788 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®); in mv88e6xxx_port_set_state()
792 reg &= ~MV88E6XXX_PORT_CTL0_STATE_MASK; in mv88e6xxx_port_set_state()
809 return -EINVAL; in mv88e6xxx_port_set_state()
812 reg |= state; in mv88e6xxx_port_set_state()
814 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); in mv88e6xxx_port_set_state()
818 dev_dbg(chip->dev, "p%d: PortState set to %s\n", port, in mv88e6xxx_port_set_state()
825 enum mv88e6xxx_egress_mode mode) in mv88e6xxx_port_set_egress_mode() argument
828 u16 reg; in mv88e6xxx_port_set_egress_mode() local
830 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®); in mv88e6xxx_port_set_egress_mode()
834 reg &= ~MV88E6XXX_PORT_CTL0_EGRESS_MODE_MASK; in mv88e6xxx_port_set_egress_mode()
836 switch (mode) { in mv88e6xxx_port_set_egress_mode()
838 reg |= MV88E6XXX_PORT_CTL0_EGRESS_MODE_UNMODIFIED; in mv88e6xxx_port_set_egress_mode()
841 reg |= MV88E6XXX_PORT_CTL0_EGRESS_MODE_UNTAGGED; in mv88e6xxx_port_set_egress_mode()
844 reg |= MV88E6XXX_PORT_CTL0_EGRESS_MODE_TAGGED; in mv88e6xxx_port_set_egress_mode()
847 reg |= MV88E6XXX_PORT_CTL0_EGRESS_MODE_ETHER_TYPE_DSA; in mv88e6xxx_port_set_egress_mode()
850 return -EINVAL; in mv88e6xxx_port_set_egress_mode()
853 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); in mv88e6xxx_port_set_egress_mode()
857 enum mv88e6xxx_frame_mode mode) in mv88e6085_port_set_frame_mode() argument
860 u16 reg; in mv88e6085_port_set_frame_mode() local
862 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®); in mv88e6085_port_set_frame_mode()
866 reg &= ~MV88E6XXX_PORT_CTL0_FRAME_MODE_MASK; in mv88e6085_port_set_frame_mode()
868 switch (mode) { in mv88e6085_port_set_frame_mode()
870 reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_NORMAL; in mv88e6085_port_set_frame_mode()
873 reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_DSA; in mv88e6085_port_set_frame_mode()
876 return -EINVAL; in mv88e6085_port_set_frame_mode()
879 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); in mv88e6085_port_set_frame_mode()
883 enum mv88e6xxx_frame_mode mode) in mv88e6351_port_set_frame_mode() argument
886 u16 reg; in mv88e6351_port_set_frame_mode() local
888 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®); in mv88e6351_port_set_frame_mode()
892 reg &= ~MV88E6XXX_PORT_CTL0_FRAME_MODE_MASK; in mv88e6351_port_set_frame_mode()
894 switch (mode) { in mv88e6351_port_set_frame_mode()
896 reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_NORMAL; in mv88e6351_port_set_frame_mode()
899 reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_DSA; in mv88e6351_port_set_frame_mode()
902 reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_PROVIDER; in mv88e6351_port_set_frame_mode()
905 reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_ETHER_TYPE_DSA; in mv88e6351_port_set_frame_mode()
908 return -EINVAL; in mv88e6351_port_set_frame_mode()
911 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); in mv88e6351_port_set_frame_mode()
918 u16 reg; in mv88e6185_port_set_forward_unknown() local
920 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®); in mv88e6185_port_set_forward_unknown()
925 reg |= MV88E6185_PORT_CTL0_FORWARD_UNKNOWN; in mv88e6185_port_set_forward_unknown()
927 reg &= ~MV88E6185_PORT_CTL0_FORWARD_UNKNOWN; in mv88e6185_port_set_forward_unknown()
929 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); in mv88e6185_port_set_forward_unknown()
936 u16 reg; in mv88e6352_port_set_ucast_flood() local
938 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®); in mv88e6352_port_set_ucast_flood()
943 reg |= MV88E6352_PORT_CTL0_EGRESS_FLOODS_UC; in mv88e6352_port_set_ucast_flood()
945 reg &= ~MV88E6352_PORT_CTL0_EGRESS_FLOODS_UC; in mv88e6352_port_set_ucast_flood()
947 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); in mv88e6352_port_set_ucast_flood()
954 u16 reg; in mv88e6352_port_set_mcast_flood() local
956 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®); in mv88e6352_port_set_mcast_flood()
961 reg |= MV88E6352_PORT_CTL0_EGRESS_FLOODS_MC; in mv88e6352_port_set_mcast_flood()
963 reg &= ~MV88E6352_PORT_CTL0_EGRESS_FLOODS_MC; in mv88e6352_port_set_mcast_flood()
965 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); in mv88e6352_port_set_mcast_flood()
1014 u16 reg; in mv88e6xxx_port_set_vlan_map() local
1017 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_BASE_VLAN, ®); in mv88e6xxx_port_set_vlan_map()
1021 reg &= ~mask; in mv88e6xxx_port_set_vlan_map()
1022 reg |= map & mask; in mv88e6xxx_port_set_vlan_map()
1024 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_BASE_VLAN, reg); in mv88e6xxx_port_set_vlan_map()
1028 dev_dbg(chip->dev, "p%d: VLANTable set to %.3x\n", port, map); in mv88e6xxx_port_set_vlan_map()
1035 const u16 upper_mask = (mv88e6xxx_num_databases(chip) - 1) >> 4; in mv88e6xxx_port_get_fid()
1036 u16 reg; in mv88e6xxx_port_get_fid() local
1039 /* Port's default FID lower 4 bits are located in reg 0x06, offset 12 */ in mv88e6xxx_port_get_fid()
1040 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_BASE_VLAN, ®); in mv88e6xxx_port_get_fid()
1044 *fid = (reg & 0xf000) >> 12; in mv88e6xxx_port_get_fid()
1046 /* Port's default FID upper bits are located in reg 0x05, offset 0 */ in mv88e6xxx_port_get_fid()
1049 ®); in mv88e6xxx_port_get_fid()
1053 *fid |= (reg & upper_mask) << 4; in mv88e6xxx_port_get_fid()
1061 const u16 upper_mask = (mv88e6xxx_num_databases(chip) - 1) >> 4; in mv88e6xxx_port_set_fid()
1062 u16 reg; in mv88e6xxx_port_set_fid() local
1066 return -EINVAL; in mv88e6xxx_port_set_fid()
1068 /* Port's default FID lower 4 bits are located in reg 0x06, offset 12 */ in mv88e6xxx_port_set_fid()
1069 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_BASE_VLAN, ®); in mv88e6xxx_port_set_fid()
1073 reg &= 0x0fff; in mv88e6xxx_port_set_fid()
1074 reg |= (fid & 0x000f) << 12; in mv88e6xxx_port_set_fid()
1076 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_BASE_VLAN, reg); in mv88e6xxx_port_set_fid()
1080 /* Port's default FID upper bits are located in reg 0x05, offset 0 */ in mv88e6xxx_port_set_fid()
1083 ®); in mv88e6xxx_port_set_fid()
1087 reg &= ~upper_mask; in mv88e6xxx_port_set_fid()
1088 reg |= (fid >> 4) & upper_mask; in mv88e6xxx_port_set_fid()
1091 reg); in mv88e6xxx_port_set_fid()
1096 dev_dbg(chip->dev, "p%d: FID set to %u\n", port, fid); in mv88e6xxx_port_set_fid()
1105 u16 reg; in mv88e6xxx_port_get_pvid() local
1109 ®); in mv88e6xxx_port_get_pvid()
1113 *pvid = reg & MV88E6XXX_PORT_DEFAULT_VLAN_MASK; in mv88e6xxx_port_get_pvid()
1120 u16 reg; in mv88e6xxx_port_set_pvid() local
1124 ®); in mv88e6xxx_port_set_pvid()
1128 reg &= ~MV88E6XXX_PORT_DEFAULT_VLAN_MASK; in mv88e6xxx_port_set_pvid()
1129 reg |= pvid & MV88E6XXX_PORT_DEFAULT_VLAN_MASK; in mv88e6xxx_port_set_pvid()
1132 reg); in mv88e6xxx_port_set_pvid()
1136 dev_dbg(chip->dev, "p%d: DefaultVID set to %u\n", port, pvid); in mv88e6xxx_port_set_pvid()
1154 u16 reg; in mv88e6185_port_set_default_forward() local
1156 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®); in mv88e6185_port_set_default_forward()
1161 reg |= MV88E6XXX_PORT_CTL2_DEFAULT_FORWARD; in mv88e6185_port_set_default_forward()
1163 reg &= ~MV88E6XXX_PORT_CTL2_DEFAULT_FORWARD; in mv88e6185_port_set_default_forward()
1165 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg); in mv88e6185_port_set_default_forward()
1172 u16 reg; in mv88e6095_port_set_upstream_port() local
1174 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®); in mv88e6095_port_set_upstream_port()
1178 reg &= ~MV88E6095_PORT_CTL2_CPU_PORT_MASK; in mv88e6095_port_set_upstream_port()
1179 reg |= upstream_port; in mv88e6095_port_set_upstream_port()
1181 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg); in mv88e6095_port_set_upstream_port()
1189 u16 reg; in mv88e6xxx_port_set_mirror() local
1193 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®); in mv88e6xxx_port_set_mirror()
1200 mirror_port = &chip->ports[port].mirror_ingress; in mv88e6xxx_port_set_mirror()
1204 mirror_port = &chip->ports[port].mirror_egress; in mv88e6xxx_port_set_mirror()
1207 return -EINVAL; in mv88e6xxx_port_set_mirror()
1210 reg &= ~bit; in mv88e6xxx_port_set_mirror()
1212 reg |= bit; in mv88e6xxx_port_set_mirror()
1214 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg); in mv88e6xxx_port_set_mirror()
1224 u16 reg; in mv88e6xxx_port_set_lock() local
1227 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®); in mv88e6xxx_port_set_lock()
1231 reg &= ~MV88E6XXX_PORT_CTL0_SA_FILT_MASK; in mv88e6xxx_port_set_lock()
1233 reg |= MV88E6XXX_PORT_CTL0_SA_FILT_DROP_ON_LOCK; in mv88e6xxx_port_set_lock()
1235 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); in mv88e6xxx_port_set_lock()
1239 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR, ®); in mv88e6xxx_port_set_lock()
1243 reg &= ~MV88E6XXX_PORT_ASSOC_VECTOR_LOCKED_PORT; in mv88e6xxx_port_set_lock()
1245 reg |= MV88E6XXX_PORT_ASSOC_VECTOR_LOCKED_PORT; in mv88e6xxx_port_set_lock()
1247 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR, reg); in mv88e6xxx_port_set_lock()
1251 u16 mode) in mv88e6xxx_port_set_8021q_mode() argument
1253 u16 reg; in mv88e6xxx_port_set_8021q_mode() local
1256 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®); in mv88e6xxx_port_set_8021q_mode()
1260 reg &= ~MV88E6XXX_PORT_CTL2_8021Q_MODE_MASK; in mv88e6xxx_port_set_8021q_mode()
1261 reg |= mode & MV88E6XXX_PORT_CTL2_8021Q_MODE_MASK; in mv88e6xxx_port_set_8021q_mode()
1263 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg); in mv88e6xxx_port_set_8021q_mode()
1267 dev_dbg(chip->dev, "p%d: 802.1QMode set to %s\n", port, in mv88e6xxx_port_set_8021q_mode()
1268 mv88e6xxx_port_8021q_mode_names[mode]); in mv88e6xxx_port_set_8021q_mode()
1296 u16 reg; in mv88e6xxx_port_set_map_da() local
1299 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®); in mv88e6xxx_port_set_map_da()
1304 reg |= MV88E6XXX_PORT_CTL2_MAP_DA; in mv88e6xxx_port_set_map_da()
1306 reg &= ~MV88E6XXX_PORT_CTL2_MAP_DA; in mv88e6xxx_port_set_map_da()
1308 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg); in mv88e6xxx_port_set_map_da()
1314 u16 reg; in mv88e6165_port_set_jumbo_size() local
1319 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®); in mv88e6165_port_set_jumbo_size()
1323 reg &= ~MV88E6XXX_PORT_CTL2_JUMBO_MODE_MASK; in mv88e6165_port_set_jumbo_size()
1326 reg |= MV88E6XXX_PORT_CTL2_JUMBO_MODE_1522; in mv88e6165_port_set_jumbo_size()
1328 reg |= MV88E6XXX_PORT_CTL2_JUMBO_MODE_2048; in mv88e6165_port_set_jumbo_size()
1330 reg |= MV88E6XXX_PORT_CTL2_JUMBO_MODE_10240; in mv88e6165_port_set_jumbo_size()
1332 return -ERANGE; in mv88e6165_port_set_jumbo_size()
1334 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg); in mv88e6165_port_set_jumbo_size()
1356 u16 reg, mask; in mv88e6xxx_port_set_assoc_vector() local
1360 ®); in mv88e6xxx_port_set_assoc_vector()
1365 reg &= ~mask; in mv88e6xxx_port_set_assoc_vector()
1366 reg |= pav & mask; in mv88e6xxx_port_set_assoc_vector()
1369 reg); in mv88e6xxx_port_set_assoc_vector()
1391 u16 reg; in mv88e6393x_port_policy_read() local
1400 ®); in mv88e6393x_port_policy_read()
1404 *data = reg; in mv88e6393x_port_policy_read()
1412 u16 reg; in mv88e6393x_port_policy_write() local
1414 reg = MV88E6393X_PORT_POLICY_MGMT_CTL_UPDATE | pointer | data; in mv88e6393x_port_policy_write()
1417 reg); in mv88e6393x_port_policy_write()
1426 if (dsa_is_unused_port(chip->ds, port)) in mv88e6393x_port_policy_write_all()
1544 /* Offset 0x18: Port IEEE Priority Remapping Registers [0-3]
1545 * Offset 0x19: Port IEEE Priority Remapping Registers [4-7]
1567 u16 reg; in mv88e6xxx_port_ieeepmt_write() local
1569 reg = MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_UPDATE | table | in mv88e6xxx_port_ieeepmt_write()
1574 MV88E6390_PORT_IEEE_PRIO_MAP_TABLE, reg); in mv88e6xxx_port_ieeepmt_write()
1649 return -EOPNOTSUPP; in mv88e6xxx_port_policy_mapping_get_pos()
1666 return -EOPNOTSUPP; in mv88e6xxx_port_policy_mapping_get_pos()
1676 u16 reg, mask, val; in mv88e6352_port_set_policy() local
1685 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_POLICY_CTL, ®); in mv88e6352_port_set_policy()
1689 reg &= ~mask; in mv88e6352_port_set_policy()
1690 reg |= (val << shift) & mask; in mv88e6352_port_set_policy()
1692 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_POLICY_CTL, reg); in mv88e6352_port_set_policy()
1703 u8 reg; in mv88e6393x_port_set_policy() local
1710 /* The 16-bit Port Policy CTL register from older chips is on 6393x in mv88e6393x_port_set_policy()
1712 * indirectly. The original 16-bit value is divided into two 8-bit in mv88e6393x_port_set_policy()
1720 err = mv88e6393x_port_policy_read(chip, port, ptr, ®); in mv88e6393x_port_set_policy()
1724 reg &= ~mask; in mv88e6393x_port_set_policy()
1725 reg |= (val << shift) & mask; in mv88e6393x_port_set_policy()
1727 return mv88e6393x_port_policy_write(chip, port, ptr, reg); in mv88e6393x_port_set_policy()