Lines Matching +full:0 +full:x3210
47 /* Offset 0x00: MAC (or PCS or Physical) Status Register
70 /* Offset 0x01: MAC (or PCS or Physical) Control Register
74 * For port's MAC speed, ForceSpd (or SpdValue) bits 1:0 program the value.
106 return 0; in mv88e6xxx_port_set_rgmii_delay()
117 return 0; in mv88e6xxx_port_set_rgmii_delay()
132 if (port != 0) in mv88e6390_port_set_rgmii_delay()
182 return 0; in mv88e6xxx_port_set_link()
188 int err = 0; in mv88e6xxx_port_sync_link()
205 int err = 0; in mv88e6185_port_sync_link()
305 return 0; in mv88e6xxx_port_set_speed_duplex()
337 if (speed == 200 && port != 0) in mv88e6341_port_set_speed_duplex()
377 if (speed == 200 && port != 0) in mv88e6390_port_set_speed_duplex()
400 if (speed == 200 && port != 0) in mv88e6390x_port_set_speed_duplex()
433 if (speed == 200 && port != 0) in mv88e6393x_port_set_speed_duplex()
436 if (speed >= 2500 && port > 0 && port < 9) in mv88e6393x_port_set_speed_duplex()
509 return 0; in mv88e6393x_port_set_speed_duplex()
516 if (port != 0 && port != 9 && port != 10) in mv88e6393x_port_max_speed_mode()
574 cmode = 0; in mv88e6xxx_port_set_cmode()
579 return 0; in mv88e6xxx_port_set_cmode()
581 chip->ports[port].cmode = 0; in mv88e6xxx_port_set_cmode()
598 return 0; in mv88e6xxx_port_set_cmode()
618 return 0; in mv88e6390_port_set_cmode()
636 if (port != 0 && port != 9 && port != 10) in mv88e6393x_port_set_cmode()
677 err = mv88e6xxx_port_hidden_read(chip, 0x7, addr, 0, ®); in mv88e6341_port_set_cmode_writable()
685 return 0; in mv88e6341_port_set_cmode_writable()
688 return mv88e6xxx_port_hidden_write(chip, 0x7, addr, 0, reg); in mv88e6341_port_set_cmode_writable()
701 return 0; in mv88e6341_port_set_cmode()
728 return 0; in mv88e6185_port_get_cmode()
742 return 0; in mv88e6352_port_get_cmode()
745 /* Offset 0x02: Jamming Control
774 /* Offset 0x04: Port Control Register */
821 return 0; in mv88e6xxx_port_set_state()
968 /* Offset 0x05: Port Control 1 */
1009 /* Offset 0x06: Port Based VLAN Map */
1030 return 0; in mv88e6xxx_port_set_vlan_map()
1039 /* Port's default FID lower 4 bits are located in reg 0x06, offset 12 */ in mv88e6xxx_port_get_fid()
1044 *fid = (reg & 0xf000) >> 12; in mv88e6xxx_port_get_fid()
1046 /* Port's default FID upper bits are located in reg 0x05, offset 0 */ in mv88e6xxx_port_get_fid()
1056 return 0; in mv88e6xxx_port_get_fid()
1068 /* Port's default FID lower 4 bits are located in reg 0x06, offset 12 */ in mv88e6xxx_port_set_fid()
1073 reg &= 0x0fff; in mv88e6xxx_port_set_fid()
1074 reg |= (fid & 0x000f) << 12; in mv88e6xxx_port_set_fid()
1080 /* Port's default FID upper bits are located in reg 0x05, offset 0 */ in mv88e6xxx_port_set_fid()
1098 return 0; in mv88e6xxx_port_set_fid()
1101 /* Offset 0x07: Default Port VLAN ID & Priority */
1115 return 0; in mv88e6xxx_port_get_pvid()
1138 return 0; in mv88e6xxx_port_set_pvid()
1141 /* Offset 0x08: Port Control 2 Register */
1270 return 0; in mv88e6xxx_port_set_8021q_mode()
1289 return 0; in mv88e6xxx_port_drop_untagged()
1337 /* Offset 0x09: Port Rate Control */
1342 0x0000); in mv88e6095_port_egress_rate_limiting()
1348 0x0001); in mv88e6097_port_egress_rate_limiting()
1351 /* Offset 0x0B: Port Association Vector */
1372 /* Offset 0x0C: Port ATU Control */
1376 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ATU_CTL, 0); in mv88e6xxx_port_disable_learn_limit()
1379 /* Offset 0x0D: (Priority) Override Register */
1383 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_PRI_OVERRIDE, 0); in mv88e6xxx_port_disable_pri_override()
1386 /* Offset 0x0E: Policy & MGMT Control Register for FAMILY 6191X 6193X 6393X */
1406 return 0; in mv88e6393x_port_policy_read()
1425 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { in mv88e6393x_port_policy_write_all()
1434 return 0; in mv88e6393x_port_policy_write_all()
1459 return 0; in mv88e6393x_set_egress_port()
1482 err = mv88e6393x_port_policy_write_all(chip, ptr, 0xff); in mv88e6393x_port_mgmt_rsvd2cpu()
1487 err = mv88e6393x_port_policy_write_all(chip, ptr, 0xff); in mv88e6393x_port_mgmt_rsvd2cpu()
1492 err = mv88e6393x_port_policy_write_all(chip, ptr, 0xff); in mv88e6393x_port_mgmt_rsvd2cpu()
1497 err = mv88e6393x_port_policy_write_all(chip, ptr, 0xff); in mv88e6393x_port_mgmt_rsvd2cpu()
1501 return 0; in mv88e6393x_port_mgmt_rsvd2cpu()
1504 /* Offset 0x10 & 0x11: EPC */
1510 return mv88e6xxx_port_wait_bit(chip, port, MV88E6393X_PORT_EPC_CMD, bit, 0); in mv88e6393x_port_epc_wait_ready()
1536 /* Offset 0x0f: Port Ether type */
1544 /* Offset 0x18: Port IEEE Priority Remapping Registers [0-3]
1545 * Offset 0x19: Port IEEE Priority Remapping Registers [4-7]
1555 0x3210); in mv88e6095_port_tag_remap()
1561 0x7654); in mv88e6095_port_tag_remap()
1582 for (i = 0; i <= 7; i++) { in mv88e6390_port_tag_remap()
1605 return 0; in mv88e6390_port_tag_remap()
1608 /* Offset 0x0E: Policy Control Register */
1669 return 0; in mv88e6xxx_port_policy_mapping_get_pos()