1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3  * Marvell 88E6xxx Ethernet switch single-chip definition
30 /* PVT limits for 4-bit port and 5-bit switch */
112  * enum mv88e6xxx_edsa_support - Ethertype DSA tag support level
117  *                               empirical data shows that this mode
152 	 * ports 2-4 are not routet to pins.
155 	/* Multi-chip Addressing Mode.
157 	 * when it is non-zero, and use indirect access to internal registers.
160 	/* Dual-chip Addressing Mode
178 	 * port 0, 1 means internal PHYs range starts at port 1, etc
228 	/* Port index */
266 	enum mv88e6xxx_policy_mapping mapping;  member
270 	int port;  member
281 	int port;  member
364 	/* Handles automatic disabling and re-enabling of the PHY
435 	/* Per-port timestamping resources. */
438 	/* Array of port structures. */
474 	int (*irl_init_all)(struct mv88e6xxx_chip *chip, int port);
516 	int (*port_set_rgmii_delay)(struct mv88e6xxx_chip *chip, int port,
517 				    phy_interface_t mode);
521 #define LINK_UNFORCED		-2
523 	/* Port's MAC link state
527 	int (*port_set_link)(struct mv88e6xxx_chip *chip, int port, int link);
529 	/* Synchronise the port link state with that of the SERDES
531 	int (*port_sync_link)(struct mv88e6xxx_chip *chip, int port, unsigned int mode, bool isup);
537 	int (*port_set_pause)(struct mv88e6xxx_chip *chip, int port,
540 #define SPEED_UNFORCED		-2
541 #define DUPLEX_UNFORCED		-2
543 	/* Port's MAC speed (in Mbps) and MAC duplex mode
551 	int (*port_set_speed_duplex)(struct mv88e6xxx_chip *chip, int port,
554 	/* What interface mode should be used for maximum speed? */
556 					       int port);
558 	int (*port_tag_remap)(struct mv88e6xxx_chip *chip, int port);
560 	int (*port_set_policy)(struct mv88e6xxx_chip *chip, int port,
561 			       enum mv88e6xxx_policy_mapping mapping,
564 	int (*port_set_frame_mode)(struct mv88e6xxx_chip *chip, int port,
565 				   enum mv88e6xxx_frame_mode mode);
566 	int (*port_set_ucast_flood)(struct mv88e6xxx_chip *chip, int port,
568 	int (*port_set_mcast_flood)(struct mv88e6xxx_chip *chip, int port,
570 	int (*port_set_ether_type)(struct mv88e6xxx_chip *chip, int port,
572 	int (*port_set_jumbo_size)(struct mv88e6xxx_chip *chip, int port,
575 	int (*port_egress_rate_limiting)(struct mv88e6xxx_chip *chip, int port);
576 	int (*port_pause_limit)(struct mv88e6xxx_chip *chip, int port, u8 in,
578 	int (*port_disable_learn_limit)(struct mv88e6xxx_chip *chip, int port);
579 	int (*port_disable_pri_override)(struct mv88e6xxx_chip *chip, int port);
580 	int (*port_setup_message_port)(struct mv88e6xxx_chip *chip, int port);
582 	/* CMODE control what PHY mode the MAC will use, eg. SGMII, RGMII, etc.
585 	int (*port_set_cmode)(struct mv88e6xxx_chip *chip, int port,
586 			      phy_interface_t mode);
587 	int (*port_get_cmode)(struct mv88e6xxx_chip *chip, int port, u8 *cmode);
590 	int (*port_setup_leds)(struct mv88e6xxx_chip *chip, int port);
592 	/* Some devices have a per port register indicating what is
593 	 * the upstream port this port should forward to.
595 	int (*port_set_upstream_port)(struct mv88e6xxx_chip *chip, int port,
598 	/* Snapshot the statistics for a port. The statistics can then
601 	int (*stats_snapshot)(struct mv88e6xxx_chip *chip, int port);
603 	/* Set the histogram mode for statistics, when the control registers
611 	size_t (*stats_get_stat)(struct mv88e6xxx_chip *chip, int port,
614 	int (*set_cpu_port)(struct mv88e6xxx_chip *chip, int port);
617 			       int port);
622 	int (*set_cascade_port)(struct mv88e6xxx_chip *chip, int port);
628 	/* SERDES lane mapping */
629 	int (*serdes_get_lane)(struct mv88e6xxx_chip *chip, int port);
633 					   int port);
636 	int (*serdes_get_sset_count)(struct mv88e6xxx_chip *chip, int port);
637 	int (*serdes_get_strings)(struct mv88e6xxx_chip *chip, int port,
639 	size_t (*serdes_get_stats)(struct mv88e6xxx_chip *chip, int port,
643 	int (*serdes_get_regs_len)(struct mv88e6xxx_chip *chip,  int port);
644 	void (*serdes_get_regs)(struct mv88e6xxx_chip *chip, int port,
648 	int (*serdes_set_tx_amplitude)(struct mv88e6xxx_chip *chip, int port,
680 	void (*phylink_get_caps)(struct mv88e6xxx_chip *chip, int port,
717 	/* Access port-scoped Precision Time Protocol registers */
718 	int (*port_ptp_read)(struct mv88e6xxx_chip *chip, int port, int addr,
720 	int (*port_ptp_write)(struct mv88e6xxx_chip *chip, int port, int addr,
741 	int (*port_enable)(struct mv88e6xxx_chip *chip, int port);
742 	int (*port_disable)(struct mv88e6xxx_chip *chip, int port);
745 	int (*set_ptp_cpu_port)(struct mv88e6xxx_chip *chip, int port);
754 	int (*pcs_init)(struct mv88e6xxx_chip *chip, int port);
755 	void (*pcs_teardown)(struct mv88e6xxx_chip *chip, int port);
756 	struct phylink_pcs *(*pcs_select)(struct mv88e6xxx_chip *chip, int port,
757 					  phy_interface_t mode);
763 	return chip->info->max_sid > 0 &&  in mv88e6xxx_has_stu()
764 		chip->info->ops->stu_loadpurge &&  in mv88e6xxx_has_stu()
765 		chip->info->ops->stu_getnext;  in mv88e6xxx_has_stu()
770 	return chip->info->pvt;  in mv88e6xxx_has_pvt()
775 	return !!chip->info->global2_addr;  in mv88e6xxx_has_lag()
780 	return chip->info->num_databases;  in mv88e6xxx_num_databases()
785 	return chip->info->num_macs;  in mv88e6xxx_num_macs()
790 	return chip->info->num_ports;  in mv88e6xxx_num_ports()
795 	return chip->info->max_vid;  in mv88e6xxx_max_vid()
800 	return chip->info->max_sid;  in mv88e6xxx_max_sid()
805 	return GENMASK((s32)mv88e6xxx_num_ports(chip) - 1, 0);  in mv88e6xxx_port_mask()
810 	return chip->info->num_gpio;  in mv88e6xxx_num_gpio()
813 static inline bool mv88e6xxx_is_invalid_port(struct mv88e6xxx_chip *chip, int port)  in mv88e6xxx_is_invalid_port()  argument
815 	return (chip->info->invalid_port_mask & BIT(port)) != 0;  in mv88e6xxx_is_invalid_port()
819 					  int port, bool mab)  in mv88e6xxx_port_set_mab()  argument
821 	chip->ports[port].mab = mab;  in mv88e6xxx_port_set_mab()
834 	mutex_lock(&chip->reg_lock);  in mv88e6xxx_reg_lock()
839 	mutex_unlock(&chip->reg_lock);  in mv88e6xxx_reg_unlock()