Lines Matching +full:half +full:- +full:precision

1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3  * Marvell 88E6xxx Ethernet switch single-chip definition
30 /* PVT limits for 4-bit port and 5-bit switch */
112  * enum mv88e6xxx_edsa_support - Ethertype DSA tag support level
152 	 * ports 2-4 are not routet to pins.
155 	/* Multi-chip Addressing Mode.
157 	 * when it is non-zero, and use indirect access to internal registers.
160 	/* Dual-chip Addressing Mode
161 	 * Some chips respond to only half of the 32 SMI addresses,
364 	/* Handles automatic disabling and re-enabling of the PHY
435 	/* Per-port timestamping resources. */
521 #define LINK_UNFORCED		-2
540 #define SPEED_UNFORCED		-2
541 #define DUPLEX_UNFORCED		-2
548 	 * Use DUPLEX_HALF or DUPLEX_FULL to force half or full duplex,
676 	/* Precision Time Protocol operations */
717 	/* Access port-scoped Precision Time Protocol registers */
723 	/* Access global Precision Time Protocol registers */
763 	return chip->info->max_sid > 0 &&  in mv88e6xxx_has_stu()
764 		chip->info->ops->stu_loadpurge &&  in mv88e6xxx_has_stu()
765 		chip->info->ops->stu_getnext;  in mv88e6xxx_has_stu()
770 	return chip->info->pvt;  in mv88e6xxx_has_pvt()
775 	return !!chip->info->global2_addr;  in mv88e6xxx_has_lag()
780 	return chip->info->num_databases;  in mv88e6xxx_num_databases()
785 	return chip->info->num_macs;  in mv88e6xxx_num_macs()
790 	return chip->info->num_ports;  in mv88e6xxx_num_ports()
795 	return chip->info->max_vid;  in mv88e6xxx_max_vid()
800 	return chip->info->max_sid;  in mv88e6xxx_max_sid()
805 	return GENMASK((s32)mv88e6xxx_num_ports(chip) - 1, 0);  in mv88e6xxx_port_mask()
810 	return chip->info->num_gpio;  in mv88e6xxx_num_gpio()
815 	return (chip->info->invalid_port_mask & BIT(port)) != 0;  in mv88e6xxx_is_invalid_port()
821 	chip->ports[port].mab = mab;  in mv88e6xxx_port_set_mab()
834 	mutex_lock(&chip->reg_lock);  in mv88e6xxx_reg_lock()
839 	mutex_unlock(&chip->reg_lock);  in mv88e6xxx_reg_unlock()