Lines Matching +full:switch +full:- +full:x +full:- +full:sgmii
1 /* SPDX-License-Identifier: GPL-2.0-only */
15 #define MT7530_MAX_MTU (15 * 1024 - ETH_HLEN - ETH_FCS_LEN - MTK_HDR_LEN)
27 #define TRGMII_BASE(x) (0x10000 + (x)) argument
43 #define BC_FFP(x) FIELD_PREP(BC_FFP_MASK, x) argument
45 #define UNM_FFP(x) FIELD_PREP(UNM_FFP_MASK, x) argument
47 #define UNU_FFP(x) FIELD_PREP(UNU_FFP_MASK, x) argument
50 #define MT7530_CPU_PORT(x) FIELD_PREP(MT7530_CPU_PORT_MASK, x) argument
53 #define MT7530_MIRROR_PORT_GET(x) FIELD_GET(MT7530_MIRROR_PORT_MASK, x) argument
54 #define MT7530_MIRROR_PORT_SET(x) FIELD_PREP(MT7530_MIRROR_PORT_MASK, x) argument
56 #define MT7531_QRY_FFP(x) FIELD_PREP(MT7531_QRY_FFP_MASK, x) argument
62 #define MT7531_MIRROR_PORT_GET(x) FIELD_GET(MT7531_MIRROR_PORT_MASK, x) argument
63 #define MT7531_MIRROR_PORT_SET(x) FIELD_PREP(MT7531_MIRROR_PORT_MASK, x) argument
65 #define MT7531_CPU_PMAP(x) FIELD_PREP(MT7531_CPU_PMAP_MASK, x) argument
99 #define PAE_EG_TAG(x) FIELD_PREP(PAE_EG_TAG_MASK, x) argument
101 #define PAE_PORT_FW(x) FIELD_PREP(PAE_PORT_FW_MASK, x) argument
103 #define BPDU_EG_TAG(x) FIELD_PREP(BPDU_EG_TAG_MASK, x) argument
106 /* Register for 01-80-C2-00-00-[01,02] MAC DA frame control */
110 #define R02_EG_TAG(x) FIELD_PREP(R02_EG_TAG_MASK, x) argument
112 #define R02_PORT_FW(x) FIELD_PREP(R02_PORT_FW_MASK, x) argument
115 #define R01_EG_TAG(x) FIELD_PREP(R01_EG_TAG_MASK, x) argument
118 /* Register for 01-80-C2-00-00-[03,0E] MAC DA frame control */
122 #define R0E_EG_TAG(x) FIELD_PREP(R0E_EG_TAG_MASK, x) argument
124 #define R0E_PORT_FW(x) FIELD_PREP(R0E_PORT_FW_MASK, x) argument
127 #define R03_EG_TAG(x) FIELD_PREP(R03_EG_TAG_MASK, x) argument
144 #define ATA2_FID(x) (((x) & 0x7) << 12) argument
151 #define ATC_HASH (((x) & 0xfff) << 16)
156 #define ATC_MAT(x) (((x) & 0xf) << 8) argument
193 #define VTCR_FUNC(x) (((x) & 0xf) << 12) argument
194 #define VTCR_VID ((x) & 0xfff)
214 #define PORT_MEM(x) (((x) & 0xff) << 16) argument
216 #define FID(x) (((x) & 0x7) << 1) argument
229 #define ETAG_CTRL_P(p, x) (((x) & 0x3) << ((p) << 1)) argument
245 #define AGE_CNT(x) (AGE_CNT_MASK & ((x) << 12)) argument
249 #define AGE_UNIT(x) (AGE_UNIT_MASK & (x)) argument
251 #define MT753X_ERLCR_P(x) (0x1040 + ((x) * 0x100)) argument
264 #define MT7530_SSP_P(x) (0x2000 + ((x) * 0x100)) argument
277 #define MT7530_PCR_P(x) (0x2004 + ((x) * 0x100)) argument
280 #define PORT_VLAN(x) ((x) & 0x3) argument
298 #define PCR_MATRIX(x) (((x) & 0xff) << 16) argument
299 #define PORT_PRI(x) (((x) & 0x7) << 24) argument
300 #define EG_TAG(x) (((x) & 0x3) << 28) argument
306 #define MT7530_PSC_P(x) (0x200c + ((x) * 0x100)) argument
310 #define MT7530_PVC_P(x) (0x2010 + ((x) * 0x100)) argument
312 #define PVC_EG_TAG(x) (((x) & 0x7) << 8) argument
314 #define VLAN_ATTR(x) (((x) & 0x3) << 6) argument
335 #define STAG_VPID (((x) & 0xffff) << 16)
337 /* Register for port port-and-protocol based vlan 1 control */
338 #define MT7530_PPBV1_P(x) (0x2014 + ((x) * 0x100)) argument
339 #define G0_PORT_VID(x) (((x) & 0xfff) << 0) argument
344 #define MT753X_PMCR_P(x) (0x3000 + ((x) * 0x100)) argument
346 #define PMCR_IFG_XMIT(x) FIELD_PREP(PMCR_IFG_XMIT_MASK, x) argument
389 #define MT753X_PMEEECR_P(x) (0x3004 + (x) * 0x100) argument
391 #define WAKEUP_TIME_1000(x) FIELD_PREP(WAKEUP_TIME_1000_MASK, x) argument
393 #define WAKEUP_TIME_100(x) FIELD_PREP(WAKEUP_TIME_100_MASK, x) argument
395 #define LPI_THRESH_GET(x) FIELD_GET(LPI_THRESH_MASK, x) argument
396 #define LPI_THRESH_SET(x) FIELD_PREP(LPI_THRESH_MASK, x) argument
399 #define MT7530_PMSR_P(x) (0x3008 + (x) * 0x100) argument
412 #define MT7531_DBG_CNT(x) (0x3018 + (x) * 0x100) argument
416 #define MAX_RX_JUMBO(x) ((x) << 2) argument
425 #define MT7530_PORT_MIB_COUNTER(x) (0x4000 + (x) * 0x100) argument
442 /* MT7531 SGMII register group */
443 #define MT7531_SGMII_REG_BASE(p) (0x5000 + ((p) - 5) * 0x1000)
466 #define MT7531_MDIO_REG_ADDR(x) (((x) & 0x1f) << 25) argument
467 #define MT7531_MDIO_DEV_ADDR(x) (((x) & 0x1f) << 25) argument
468 #define MT7531_MDIO_PHY_ADDR(x) (((x) & 0x1f) << 20) argument
469 #define MT7531_MDIO_CMD(x) (((x) & 0x3) << 18) argument
470 #define MT7531_MDIO_ST(x) (((x) & 0x3) << 16) argument
498 #define CLK_SKEW_OUT(x) (((x) & 0x3) << 8) argument
500 #define CLK_SKEW_IN(x) (((x) & 0x3) << 6) argument
504 #define GP_MODE(x) (((x) & 0x3) << 1) argument
555 #define P5_IO_CLK_DRV(x) ((x) & 0x3) argument
556 #define P5_IO_DATA_DRV(x) (((x) & 0x3) << 4) argument
567 #define P6_INTF_MODE(x) ((x) & 0x3) argument
577 /* Registers for RGMII and SGMII PLL clock */
587 #define DQSI1_TAP(x) (((x) & 0x7f) << 8) argument
588 #define DQSI0_TAP(x) ((x) & 0x7f) argument
594 #define MT7530_TRGMII_RD(x) (0x7a10 + (x) * 8) argument
598 #define RD_TAP(x) ((x) & 0x7f) argument
606 #define TD_DM_DRVP(x) ((x) & 0xf) argument
607 #define TD_DM_DRVN(x) (((x) & 0xf) << 4) argument
610 #define TCK_TAP(x) (((x) & 0xf) << 8) argument
614 #define CSR_RGMII_RXC_0DEG_CFG(x) ((x) & 0xf) argument
617 #define CSR_RGMII_TXC_CFG(x) ((x) & 0x1f) argument
663 #define RG_SYSPLL_RST_DLY(x) (((x) & 0x3) << 12) argument
665 #define RG_SYSPLL_PREDIV(x) (((x) & 0x3) << 8) argument
666 #define RG_SYSPLL_POSDIV(x) (((x) & 0x3) << 5) argument
681 #define RG_LCDDS_PCW_NCPO1(x) ((x) & 0xffff) argument
684 #define RG_LCDDS_PCW_NCPO0(x) ((x) & 0xffff) argument
689 #define RG_LCCDS_C(x) (((x) & 0x7) << 4) argument
693 #define RG_LCDDS_SSC_DELTA(x) ((x) & 0xfff) argument
696 #define RG_LCDDS_SSC_DELTA1(x) ((x) & 0xfff) argument
699 #define RG_GSWPLL_PREDIV(x) (((x) & 0x3) << 14) argument
700 #define RG_GSWPLL_POSDIV_200M(x) (((x) & 0x3) << 12) argument
705 #define RG_GSWPLL_FBKDIV_200M(x) ((x) & 0xff) argument
708 #define RG_GSWPLL_POSDIV_500M(x) (((x) & 0x3) << 8) argument
709 #define RG_GSWPLL_FBKDIV_500M(x) ((x) & 0xff) argument
736 /* struct mt7530_port - This is the main data structure for holding the state
752 /* Port 5 mode definitions of the MT7530 switch */
767 /* struct mt753x_info - This is the main data structure for holding the specific
769 * @id: Holding the identifier to a switch model
800 /* struct mt7530_priv - This is the main data structure for holding the state
804 * @bus: The bus used for the device and built-in PHY
805 * @regmap: The regmap instance representing all switch registers
815 * @p5_mode: Holding the current mode of port 5 of the MT7530 switch
816 * @p5_sgmii: Flag for distinguishing if port 5 of the MT7531 switch
817 * has got SGMII
818 * @irq: IRQ number of the switch
819 * @irq_domain: IRQ domain of the switch irq_chip
821 * @create_sgmii: Pointer to function creating SGMII PCS instance(s)
862 e->port = port; in mt7530_hw_vlan_entry_init()
863 e->untagged = untagged; in mt7530_hw_vlan_entry_init()
883 p->priv = priv; in INIT_MT7530_DUMMY_POLL()
884 p->reg = reg; in INIT_MT7530_DUMMY_POLL()