Lines Matching +full:0 +full:x001b
10 /* 0 - Operation */
11 #define REG_GLOBAL_CTRL_0 0x0007
17 #define REG_SW_INT_STATUS__4 0x0010
18 #define REG_SW_INT_MASK__4 0x0014
32 #define REG_SW_PORT_INT_STATUS__4 0x0018
33 #define REG_SW_PORT_INT_MASK__4 0x001C
36 #define REG_SW_GLOBAL_OUTPUT_CTRL__1 0x0103
38 #define SW_CLK25_ENB BIT(0)
40 #define REG_SW_CFG_STRAP_VAL 0x0200
42 #define SW_VPHY_ADD_CFG BIT(0)
45 #define REG_SW_CFG_STRAP_OVR 0x0214
49 #define REG_SW_OPERATION 0x0300
55 #define REG_SW_LUE_CTRL_0 0x0310
62 #define REG_SW_LUE_CTRL_1 0x0311
70 #define SW_LINK_AUTO_AGING BIT(0)
72 #define REG_SW_LUE_CTRL_2 0x0312
76 #define REG_SW_AGE_PERIOD__1 0x0313
77 #define SW_AGE_PERIOD_7_0_M GENMASK(7, 0)
79 #define REG_SW_AGE_PERIOD__2 0x0320
82 #define REG_SW_MAC_CTRL_0 0x0330
85 #define SW_AGGR_BACKOFF BIT(0)
87 #define REG_SW_MAC_CTRL_1 0x0331
94 #define SW_PASS_SHORT_FRAME BIT(0)
96 #define REG_SW_MAC_CTRL_6 0x0336
101 #define REG_SW_ALU_STAT_CTRL__4 0x041C
103 #define REG_SW_ALU_VAL_B 0x0424
106 #define ALU_V_PORT_MAP 0xFF
109 #define REG_VPHY_IND_ADDR__2 0x075C
110 #define REG_VPHY_IND_DATA__2 0x0760
112 #define REG_VPHY_IND_CTRL__2 0x0768
115 #define VPHY_IND_BUSY BIT(0)
117 #define REG_VPHY_SPECIAL_CTRL__2 0x077C
122 #define VPHY_PORT_MODE_M 0x3
124 #define VPHY_MODE_RGMII 0
129 #define VPHY_SPEED_DUPLEX_STAT_M 0x7
137 /* 0 - Operation */
138 #define REG_PORT_INT_STATUS 0x001B
139 #define REG_PORT_INT_MASK 0x001F
146 #define PORT_ACL_INT BIT(0)
150 #define REG_PORT_CTRL_0 0x0020
157 #define PORT_QUEUE_SPLIT_ENABLE 0x3
160 #define REG_PORT_T1_PHY_CTRL_BASE 0x0100
161 #define REG_PORT_TX_PHY_CTRL_BASE 0x0280
165 #define PORT_GRXC_ENABLE BIT(0)
169 #define REG_PORT_XMII_CTRL_4 0x0304
170 #define REG_PORT_XMII_CTRL_5 0x0306
176 #define REG_PORT_MAC_CTRL_0 0x0400
179 #define PORT_JUMBO_PACKET BIT(0)
181 #define REG_PORT_MAC_CTRL_1 0x0401
183 #define PORT_PASS_ALL BIT(0)
185 #define PORT_MAX_FR_SIZE 0x404
189 #define REG_PORT_MRI_PRIO_CTRL 0x0801
196 #define PORT_ACL_PRIO_ENABLE BIT(0)
201 #define REG_PORT_MTI_CREDIT_INCREMENT 0x091C
211 #define RGMII_2_TX_DELAY_2NS 0
212 #define RGMII_1_RX_DELAY_2NS 0x1B
213 #define RGMII_2_RX_DELAY_2NS 0x14