Lines Matching +full:2 +full:rgmii
29 * Port 5 is connected to an RGMII interface without a PHY. The values
33 [0] = 2, /* Port 1, T1 AFE0 */
34 [1] = 3, /* Port 2, T1 AFE1 */
35 [2] = 5, /* Port 3, T1 AFE3 */
37 [4] = LAN937X_NO_PHY, /* Port 5, RGMII 2 */
46 [0] = 2, /* Port 1, T1 AFE0 */
47 [1] = 3, /* Port 2, T1 AFE1 */
48 [2] = 5, /* Port 3, T1 AFE3 */
50 [4] = LAN937X_NO_PHY, /* Port 5, RGMII 2 */
51 [5] = LAN937X_NO_PHY, /* Port 6, RGMII 1 */
60 [0] = 2, /* Port 1, T1 AFE0 */
61 [1] = 3, /* Port 2, T1 AFE1 */
62 [2] = 5, /* Port 3, T1 AFE3 */
64 [4] = LAN937X_NO_PHY, /* Port 5, RGMII 2 */
65 [5] = LAN937X_NO_PHY, /* Port 6, RGMII 1 */
76 [0] = 2, /* Port 1, T1 AFE0 */
77 [1] = 3, /* Port 2, T1 AFE1 */
78 [2] = 5, /* Port 3, T1 AFE3 */
80 [4] = LAN937X_NO_PHY, /* Port 5, RGMII 2 */
81 [5] = LAN937X_NO_PHY, /* Port 6, RGMII 1 */
92 [0] = 2, /* Port 1, T1 AFE0 */
93 [1] = 3, /* Port 2, T1 AFE1 */
94 [2] = 5, /* Port 3, T1 AFE3 */
96 [4] = LAN937X_NO_PHY, /* Port 5, RGMII 2 */
97 [5] = LAN937X_NO_PHY, /* Port 6, RGMII 1 */
123 * 2. **MDIO Access**: The PHY address mapping varies based on chip variant
219 * 2. **MDIO Access**: Grants access to internal PHYs over the side MDIO bus,
263 temp = PORT_CTRL_ADDR(addr, (addr_base + (reg << 2))); in lan937x_vphy_ind_addr_wr()
580 /* MII/RMII/RGMII ports */ in lan937x_phylink_get_caps()
595 dev_info(dev->dev, "Applied rgmii tx delay for the port %d\n", in lan937x_setup_rgmii_delay()
601 dev_info(dev->dev, "Applied rgmii rx delay for the port %d\n", in lan937x_setup_rgmii_delay()