60 	case MCP251XFD_REG_FLTCON(0):  in mcp251xfd_update_bits_read_reg()
76 		WARN(1, "Status of reg 0x%04x unknown.\n", reg);  in mcp251xfd_update_bits_read_reg()
90 	__le32 orig_le32 = 0, mask_le32, val_le32, tmp_le32;  in mcp251xfd_regmap_nocrc_update_bits()
98 	    mask == 0)  in mcp251xfd_regmap_nocrc_update_bits()
110 		spi_message_add_tail(&xfer[0], &msg);  in mcp251xfd_regmap_nocrc_update_bits()
113 			xfer[0].tx_buf = buf_tx;  in mcp251xfd_regmap_nocrc_update_bits()
114 			xfer[0].len = sizeof(buf_tx->cmd);  in mcp251xfd_regmap_nocrc_update_bits()
120 			xfer[0].tx_buf = buf_tx;  in mcp251xfd_regmap_nocrc_update_bits()
121 			xfer[0].rx_buf = buf_rx;  in mcp251xfd_regmap_nocrc_update_bits()
122 			xfer[0].len = sizeof(buf_tx->cmd) + len;  in mcp251xfd_regmap_nocrc_update_bits()
125 				memset(buf_tx->data, 0x0, len);  in mcp251xfd_regmap_nocrc_update_bits()
169 	spi_message_add_tail(&xfer[0], &msg);  in mcp251xfd_regmap_nocrc_read()
172 		xfer[0].tx_buf = reg;  in mcp251xfd_regmap_nocrc_read()
173 		xfer[0].len = sizeof(buf_tx->cmd);  in mcp251xfd_regmap_nocrc_read()
179 		xfer[0].tx_buf = buf_tx;  in mcp251xfd_regmap_nocrc_read()
180 		xfer[0].rx_buf = buf_rx;  in mcp251xfd_regmap_nocrc_read()
181 		xfer[0].len = sizeof(buf_tx->cmd) + val_len;  in mcp251xfd_regmap_nocrc_read()
185 			memset(buf_tx->data, 0x0, val_len);  in mcp251xfd_regmap_nocrc_read()
195 	return 0;  in mcp251xfd_regmap_nocrc_read()
260 	return 0;  in mcp251xfd_regmap_crc_read_check_crc()
304 	spi_message_add_tail(&xfer[0], &msg);  in mcp251xfd_regmap_crc_read()
307 		xfer[0].tx_buf = buf_tx;  in mcp251xfd_regmap_crc_read()
308 		xfer[0].len = sizeof(buf_tx->cmd);  in mcp251xfd_regmap_crc_read()
314 		xfer[0].tx_buf = buf_tx;  in mcp251xfd_regmap_crc_read()
315 		xfer[0].rx_buf = buf_rx;  in mcp251xfd_regmap_crc_read()
316 		xfer[0].len = sizeof(buf_tx->cmd) + val_len +  in mcp251xfd_regmap_crc_read()
320 			memset(buf_tx->data, 0x0, val_len +  in mcp251xfd_regmap_crc_read()
326 	for (i = 0; i < MCP251XFD_READ_CRC_RETRIES_MAX; i++) {  in mcp251xfd_regmap_crc_read()
339 		 * bus) of that register is 0x00 or 0x80 the  in mcp251xfd_regmap_crc_read()
342 		 * to the first byte being 0x00 or 0x80.  in mcp251xfd_regmap_crc_read()
350 		    ((buf_rx->data[0] & 0xf8) == 0x0 ||  in mcp251xfd_regmap_crc_read()
351 		     (buf_rx->data[0] & 0xf8) == 0x80)) {  in mcp251xfd_regmap_crc_read()
353 			buf_rx->data[0] ^= 0x80;  in mcp251xfd_regmap_crc_read()
382 			err = 0;  in mcp251xfd_regmap_crc_read()
387 			    "CRC read error at address 0x%04x (length=%zd, data=%*ph, CRC=0x%04x) retrying.\n",  in mcp251xfd_regmap_crc_read()
394 			   "CRC read error at address 0x%04x (length=%zd, data=%*ph, CRC=0x%04x).\n",  in mcp251xfd_regmap_crc_read()
403 	return 0;  in mcp251xfd_regmap_crc_read()
407 	regmap_reg_range(0x000, 0x2ec),	/* CAN FD Controller Module SFR */
408 	regmap_reg_range(0x400, 0xbfc),	/* RAM */
409 	regmap_reg_range(0xe00, 0xe14),	/* MCP2517/18FD SFR */
421 	.pad_bits = 0,
423 	.max_register = 0xffc,
450 	.max_register = 0xffc,
518 	return 0;  in mcp251xfd_regmap_init_nocrc()
571 	return 0;  in mcp251xfd_regmap_init_crc()
608 	return 0;  in mcp251xfd_regmap_init()