Lines Matching +full:use +full:- +full:minimum +full:- +full:ecc
1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /* Copyright (C) 2015 - 2016 Thomas Körper, esd electronic system design gmbh
3 * Copyright (C) 2017 - 2023 Stefan Mätje, esd electronics gmbh
34 * extraction into an extra variable => (xx - 16).
36 #define ACC_OV_REG_FEAT_MASK_CANFD BIT(27 - 16)
37 #define ACC_OV_REG_FEAT_MASK_NEW_PSC BIT(28 - 16)
38 #define ACC_OV_REG_FEAT_MASK_DAR BIT(30 - 16)
87 /* BRP and BTR register layout for CAN-Classic version */
93 /* BRP and BTR register layout for CAN-FD version */
118 * ACC_CORE_DMAMSG_SIZE and a minimum alignment of ACC_CORE_DMAMSG_SIZE in
172 u8 ecc; member
235 * are valid. Use READ_ONCE() to access this memory location.
270 return ioread32be(core->addr + offs); in acc_read32()
276 iowrite32be(v, core->addr + offs); in acc_write32()
282 iowrite32(v, core->addr + offs); in acc_write32_noswap()
312 return ioread32be(ov->addr + offs); in acc_ov_read32()
318 iowrite32be(v, ov->addr + offs); in acc_ov_write32()
343 /* (Re-)start and wait for completion of addon detection on the I^2C bus */ in acc_reset_fpga()