1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /* Copyright (C) 2015 - 2016 Thomas Körper, esd electronic system design gmbh
3  * Copyright (C) 2017 - 2023 Stefan Mätje, esd electronics gmbh
32 /* Feature flags are contained in the upper 16 bit of the version
34  * extraction into an extra variable => (xx - 16).
36 #define ACC_OV_REG_FEAT_MASK_CANFD BIT(27 - 16)
37 #define ACC_OV_REG_FEAT_MASK_NEW_PSC BIT(28 - 16)
38 #define ACC_OV_REG_FEAT_MASK_DAR BIT(30 - 16)
40 #define ACC_OV_REG_MODE_MASK_ENDIAN_LITTLE BIT(0)
41 #define ACC_OV_REG_MODE_MASK_BM_ENABLE BIT(1)
42 #define ACC_OV_REG_MODE_MASK_MODE_LED BIT(2)
43 #define ACC_OV_REG_MODE_MASK_TIMER_ENABLE BIT(4)
44 #define ACC_OV_REG_MODE_MASK_TIMER_ONE_SHOT BIT(5)
45 #define ACC_OV_REG_MODE_MASK_TIMER_ABSOLUTE BIT(6)
48 #define ACC_OV_REG_MODE_MASK_I2C_ENABLE BIT(11)
49 #define ACC_OV_REG_MODE_MASK_MSI_ENABLE BIT(14)
50 #define ACC_OV_REG_MODE_MASK_NEW_PSC_ENABLE BIT(15)
51 #define ACC_OV_REG_MODE_MASK_FPGA_RESET BIT(31)
71 #define ACC_REG_CTRL_MASK_RESETMODE BIT(0)
72 #define ACC_REG_CTRL_MASK_LOM BIT(1)
73 #define ACC_REG_CTRL_MASK_STM BIT(2)
74 #define ACC_REG_CTRL_MASK_TRANSEN BIT(5)
75 #define ACC_REG_CTRL_MASK_TS BIT(6)
76 #define ACC_REG_CTRL_MASK_SCHEDULE BIT(7)
78 #define ACC_REG_CTRL_MASK_IE_RXTX BIT(8)
79 #define ACC_REG_CTRL_MASK_IE_TXERROR BIT(9)
80 #define ACC_REG_CTRL_MASK_IE_ERRWARN BIT(10)
81 #define ACC_REG_CTRL_MASK_IE_OVERRUN BIT(11)
82 #define ACC_REG_CTRL_MASK_IE_TSI BIT(12)
83 #define ACC_REG_CTRL_MASK_IE_ERRPASS BIT(13)
84 #define ACC_REG_CTRL_MASK_IE_ALI BIT(14)
85 #define ACC_REG_CTRL_MASK_IE_BUSERR BIT(15)
87 /* BRP and BTR register layout for CAN-Classic version */
93 /* BRP and BTR register layout for CAN-FD version */
270 	return ioread32be(core->addr + offs);  in acc_read32()
274 			       unsigned short offs, u32 v)  in acc_write32()  argument
276 	iowrite32be(v, core->addr + offs);  in acc_write32()
280 				      unsigned short offs, u32 v)  in acc_write32_noswap()  argument
282 	iowrite32(v, core->addr + offs);  in acc_write32_noswap()
288 	u32 v = acc_read32(core, offs);  in acc_set_bits()  local
290 	v |= mask;  in acc_set_bits()
291 	acc_write32(core, offs, v);  in acc_set_bits()
297 	u32 v = acc_read32(core, offs);  in acc_clear_bits()  local
299 	v &= ~mask;  in acc_clear_bits()
300 	acc_write32(core, offs, v);  in acc_clear_bits()
312 	return ioread32be(ov->addr + offs);  in acc_ov_read32()
316 				  unsigned short offs, u32 v)  in acc_ov_write32()  argument
318 	iowrite32be(v, ov->addr + offs);  in acc_ov_write32()
324 	u32 v = acc_ov_read32(ov, offs);  in acc_ov_set_bits()  local
326 	v |= b;  in acc_ov_set_bits()
327 	acc_ov_write32(ov, offs, v);  in acc_ov_set_bits()
333 	u32 v = acc_ov_read32(ov, offs);  in acc_ov_clear_bits()  local
335 	v &= ~b;  in acc_ov_clear_bits()
336 	acc_ov_write32(ov, offs, v);  in acc_ov_clear_bits()
343 	/* (Re-)start and wait for completion of addon detection on the I^2C bus */  in acc_reset_fpga()