Lines Matching +full:11 +full:- +full:bit

1 /* SPDX-License-Identifier: GPL-2.0-or-later */
6  * Copyright (C) 2015-2018 Ondrej Ille <[email protected]> FEE CTU
7  * Copyright (C) 2018-2022 Ondrej Ille <[email protected]> self-funded
8  * Copyright (C) 2018-2019 Martin Jerabek <[email protected]> FEE CTU
9  * Copyright (C) 2018-2022 Pavel Pisa <[email protected]> FEE CTU/self-funded
103 #define REG_MODE_RST BIT(0)
104 #define REG_MODE_BMM BIT(1)
105 #define REG_MODE_STM BIT(2)
106 #define REG_MODE_AFM BIT(3)
107 #define REG_MODE_FDE BIT(4)
108 #define REG_MODE_TTTM BIT(5)
109 #define REG_MODE_ROM BIT(6)
110 #define REG_MODE_ACF BIT(7)
111 #define REG_MODE_TSTM BIT(8)
112 #define REG_MODE_RXBAM BIT(9)
113 #define REG_MODE_SAM BIT(11)
114 #define REG_MODE_RTRLE BIT(16)
116 #define REG_MODE_ILBP BIT(21)
117 #define REG_MODE_ENA BIT(22)
118 #define REG_MODE_NISOFD BIT(23)
119 #define REG_MODE_PEX BIT(24)
120 #define REG_MODE_TBFBO BIT(25)
121 #define REG_MODE_FDRF BIT(26)
124 #define REG_STATUS_RXNE BIT(0)
125 #define REG_STATUS_DOR BIT(1)
126 #define REG_STATUS_TXNF BIT(2)
127 #define REG_STATUS_EFT BIT(3)
128 #define REG_STATUS_RXS BIT(4)
129 #define REG_STATUS_TXS BIT(5)
130 #define REG_STATUS_EWL BIT(6)
131 #define REG_STATUS_IDLE BIT(7)
132 #define REG_STATUS_PEXS BIT(8)
133 #define REG_STATUS_STCNT BIT(16)
136 #define REG_COMMAND_RXRPMV BIT(1)
137 #define REG_COMMAND_RRB BIT(2)
138 #define REG_COMMAND_CDO BIT(3)
139 #define REG_COMMAND_ERCRST BIT(4)
140 #define REG_COMMAND_RXFCRST BIT(5)
141 #define REG_COMMAND_TXFCRST BIT(6)
142 #define REG_COMMAND_CPEXS BIT(7)
145 #define REG_INT_STAT_RXI BIT(0)
146 #define REG_INT_STAT_TXI BIT(1)
147 #define REG_INT_STAT_EWLI BIT(2)
148 #define REG_INT_STAT_DOI BIT(3)
149 #define REG_INT_STAT_FCSI BIT(4)
150 #define REG_INT_STAT_ALI BIT(5)
151 #define REG_INT_STAT_BEI BIT(6)
152 #define REG_INT_STAT_OFI BIT(7)
153 #define REG_INT_STAT_RXFI BIT(8)
154 #define REG_INT_STAT_BSI BIT(9)
155 #define REG_INT_STAT_RBNEI BIT(10)
156 #define REG_INT_STAT_TXBHCI BIT(11)
159 #define REG_INT_ENA_SET_INT_ENA_SET GENMASK(11, 0)
162 #define REG_INT_ENA_CLR_INT_ENA_CLR GENMASK(11, 0)
165 #define REG_INT_MASK_SET_INT_MASK_SET GENMASK(11, 0)
168 #define REG_INT_MASK_CLR_INT_MASK_CLR GENMASK(11, 0)
179 #define REG_BTR_FD_PH1_FD GENMASK(11, 7)
187 #define REG_EWL_ERA BIT(16)
188 #define REG_EWL_ERP BIT(17)
189 #define REG_EWL_BOF BIT(18)
201 #define REG_CTR_PRES_PTX BIT(9)
202 #define REG_CTR_PRES_PRX BIT(10)
203 #define REG_CTR_PRES_ENORM BIT(11)
204 #define REG_CTR_PRES_EFD BIT(12)
231 #define REG_FILTER_CONTROL_FANB BIT(0)
232 #define REG_FILTER_CONTROL_FANE BIT(1)
233 #define REG_FILTER_CONTROL_FAFB BIT(2)
234 #define REG_FILTER_CONTROL_FAFE BIT(3)
235 #define REG_FILTER_CONTROL_FBNB BIT(4)
236 #define REG_FILTER_CONTROL_FBNE BIT(5)
237 #define REG_FILTER_CONTROL_FBFB BIT(6)
238 #define REG_FILTER_CONTROL_FBFE BIT(7)
239 #define REG_FILTER_CONTROL_FCNB BIT(8)
240 #define REG_FILTER_CONTROL_FCNE BIT(9)
241 #define REG_FILTER_CONTROL_FCFB BIT(10)
242 #define REG_FILTER_CONTROL_FCFE BIT(11)
243 #define REG_FILTER_CONTROL_FRNB BIT(12)
244 #define REG_FILTER_CONTROL_FRNE BIT(13)
245 #define REG_FILTER_CONTROL_FRFB BIT(14)
246 #define REG_FILTER_CONTROL_FRFE BIT(15)
247 #define REG_FILTER_CONTROL_SFA BIT(16)
248 #define REG_FILTER_CONTROL_SFB BIT(17)
249 #define REG_FILTER_CONTROL_SFC BIT(18)
250 #define REG_FILTER_CONTROL_SFR BIT(19)
257 #define REG_RX_POINTERS_RX_WPP GENMASK(11, 0)
261 #define REG_RX_STATUS_RXE BIT(0)
262 #define REG_RX_STATUS_RXF BIT(1)
263 #define REG_RX_STATUS_RXMOF BIT(2)
265 #define REG_RX_STATUS_RTSOP BIT(16)
273 #define REG_TX_STATUS_TX3S GENMASK(11, 8)
281 #define REG_TX_COMMAND_TXCE BIT(0)
282 #define REG_TX_COMMAND_TXCR BIT(1)
283 #define REG_TX_COMMAND_TXCA BIT(2)
284 #define REG_TX_COMMAND_TXB1 BIT(8)
285 #define REG_TX_COMMAND_TXB2 BIT(9)
286 #define REG_TX_COMMAND_TXB3 BIT(10)
287 #define REG_TX_COMMAND_TXB4 BIT(11)
288 #define REG_TX_COMMAND_TXB5 BIT(12)
289 #define REG_TX_COMMAND_TXB6 BIT(13)
290 #define REG_TX_COMMAND_TXB7 BIT(14)
291 #define REG_TX_COMMAND_TXB8 BIT(15)
307 #define REG_ERR_CAPT_RETR_CTR_VAL GENMASK(11, 8)
326 #define REG_DEBUG_REGISTER_PC_ARB BIT(6)
327 #define REG_DEBUG_REGISTER_PC_CON BIT(7)
328 #define REG_DEBUG_REGISTER_PC_DAT BIT(8)
329 #define REG_DEBUG_REGISTER_PC_STC BIT(9)
330 #define REG_DEBUG_REGISTER_PC_CRC BIT(10)
331 #define REG_DEBUG_REGISTER_PC_CRCD BIT(11)
332 #define REG_DEBUG_REGISTER_PC_ACK BIT(12)
333 #define REG_DEBUG_REGISTER_PC_ACKD BIT(13)
334 #define REG_DEBUG_REGISTER_PC_EOF BIT(14)
335 #define REG_DEBUG_REGISTER_PC_INT BIT(15)
336 #define REG_DEBUG_REGISTER_PC_SUSP BIT(16)
337 #define REG_DEBUG_REGISTER_PC_OVR BIT(17)
338 #define REG_DEBUG_REGISTER_PC_SOF BIT(18)