1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/mtd/spi-nor.h>
14 #define SPINOR_OP_MT_DIE_ERASE	0xc4	/* Chip (die) erase opcode */
28 #define FSR_E_ERR		BIT(5)	/* Erase operation status */
54 	u8 *buf = nor->bouncebuf;  in micron_st_nor_octal_dtr_en()
56 	u8 addr_mode_nbytes = nor->params->addr_mode_nbytes;  in micron_st_nor_octal_dtr_en()
63 	ret = spi_nor_write_any_volatile_reg(nor, &op, nor->reg_proto);  in micron_st_nor_octal_dtr_en()
71 	ret = spi_nor_write_any_volatile_reg(nor, &op, nor->reg_proto);  in micron_st_nor_octal_dtr_en()
78 		dev_dbg(nor->dev, "error %d reading JEDEC ID after enabling 8D-8D-8D mode\n", ret);  in micron_st_nor_octal_dtr_en()
82 	if (memcmp(buf, nor->info->id->bytes, nor->info->id->len))  in micron_st_nor_octal_dtr_en()
83 		return -EINVAL;  in micron_st_nor_octal_dtr_en()
91 	u8 *buf = nor->bouncebuf;  in micron_st_nor_octal_dtr_dis()
95 	 * The register is 1-byte wide, but 1-byte transactions are not allowed  in micron_st_nor_octal_dtr_dis()
96 	 * in 8D-8D-8D mode. The next register is the dummy cycle configuration  in micron_st_nor_octal_dtr_dis()
99 	 * because the value was changed when enabling 8D-8D-8D mode, it should  in micron_st_nor_octal_dtr_dis()
105 		MICRON_ST_NOR_WR_ANY_REG_OP(nor->addr_nbytes,  in micron_st_nor_octal_dtr_dis()
114 		dev_dbg(nor->dev, "error %d reading JEDEC ID after disabling 8D-8D-8D mode\n", ret);  in micron_st_nor_octal_dtr_dis()
118 	if (memcmp(buf, nor->info->id->bytes, nor->info->id->len))  in micron_st_nor_octal_dtr_dis()
119 		return -EINVAL;  in micron_st_nor_octal_dtr_dis()
132 	nor->params->set_octal_dtr = micron_st_nor_set_octal_dtr;  in mt35xu512aba_default_init()
138 	nor->params->hwcaps.mask |= SNOR_HWCAPS_READ_8_8_8_DTR;  in mt35xu512aba_post_sfdp_fixup()
139 	spi_nor_set_read_settings(&nor->params->reads[SNOR_CMD_READ_8_8_8_DTR],  in mt35xu512aba_post_sfdp_fixup()
143 	nor->cmd_ext_type = SPI_NOR_EXT_REPEAT;  in mt35xu512aba_post_sfdp_fixup()
144 	nor->params->rdsr_dummy = 8;  in mt35xu512aba_post_sfdp_fixup()
145 	nor->params->rdsr_addr_nbytes = 0;  in mt35xu512aba_post_sfdp_fixup()
152 	nor->params->quad_enable = NULL;  in mt35xu512aba_post_sfdp_fixup()
167 		.size = SZ_64M,
177 		.size = SZ_256M,
188 	nor->flags &= ~SNOR_F_HAS_16BIT_SR;  in mt25qu512a_post_bfpt_fixup()
198 	struct spi_nor_flash_parameter *params = nor->params;  in st_nor_four_die_late_init()
200 	params->die_erase_opcode = SPINOR_OP_MT_DIE_ERASE;  in st_nor_four_die_late_init()
201 	params->n_dice = 4;  in st_nor_four_die_late_init()
204 	 * Unfortunately the die erase opcode does not have a 4-byte opcode  in st_nor_four_die_late_init()
206 	 * consider the die erase too. We're forced to enter in the 4 byte  in st_nor_four_die_late_init()
207 	 * address mode in order to benefit of the die erase.  in st_nor_four_die_late_init()
214 	struct spi_nor_flash_parameter *params = nor->params;  in st_nor_two_die_late_init()
216 	params->die_erase_opcode = SPINOR_OP_MT_DIE_ERASE;  in st_nor_two_die_late_init()
217 	params->n_dice = 2;  in st_nor_two_die_late_init()
220 	 * Unfortunately the die erase opcode does not have a 4-byte opcode  in st_nor_two_die_late_init()
222 	 * consider the die erase too. We're forced to enter in the 4 byte  in st_nor_two_die_late_init()
223 	 * address mode in order to benefit of the die erase.  in st_nor_two_die_late_init()
242 		.name = "m25p05-nonjedec",
244 		.size = SZ_64K,
246 		.name = "m25p10-nonjedec",
248 		.size = SZ_128K,
250 		.name = "m25p20-nonjedec",
251 		.size = SZ_256K,
253 		.name = "m25p40-nonjedec",
254 		.size = SZ_512K,
256 		.name = "m25p80-nonjedec",
257 		.size = SZ_1M,
259 		.name = "m25p16-nonjedec",
260 		.size = SZ_2M,
262 		.name = "m25p32-nonjedec",
263 		.size = SZ_4M,
265 		.name = "m25p64-nonjedec",
266 		.size = SZ_8M,
268 		.name = "m25p128-nonjedec",
270 		.size = SZ_16M,
275 		.size = SZ_64K,
280 		.size = SZ_128K,
284 		.size = SZ_256K,
288 		.size = SZ_512K,
292 		.size = SZ_1M,
296 		.size = SZ_2M,
300 		.size = SZ_4M,
304 		.size = SZ_8M,
309 		.size = SZ_16M,
313 		.size = SZ_128K,
317 		.size = SZ_1M,
321 		.size = SZ_2M,
324 		.name = "m25px32-s1",
325 		.size = SZ_4M,
330 		.size = SZ_1M,
334 		.size = SZ_2M,
339 		.size = SZ_4M,
344 		.size = SZ_8M,
347 		.name = "m25px32-s0",
348 		.size = SZ_4M,
353 		.size = SZ_256K,
357 		.size = SZ_1M,
361 		.size = SZ_2M,
366 		.size = SZ_4M,
371 		.size = SZ_8M,
376 		.size = SZ_16M,
384 		.size = SZ_32M,
391 		.size = SZ_32M,
397 		.size = SZ_64M,
404 		.size = SZ_64M,
412 		.size = SZ_128M,
421 		.size = SZ_256M,
428 		.size = SZ_2M,
433 		.size = SZ_4M,
438 		.size = SZ_8M,
445 		.size = SZ_16M,
453 		.size = SZ_32M,
462 		.size = SZ_32M,
475 		.size = SZ_64M,
488 		.size = SZ_128M,
495 		.size = SZ_256M,
503  * micron_st_nor_read_fsr() - Read the Flag Status Register.
505  * @fsr:	pointer to a DMA-able buffer where the value of the
509  * Return: 0 on success, -errno otherwise.
515 	if (nor->spimem) {  in micron_st_nor_read_fsr()
518 		if (nor->reg_proto == SNOR_PROTO_8_8_8_DTR) {  in micron_st_nor_read_fsr()
519 			op.addr.nbytes = nor->params->rdsr_addr_nbytes;  in micron_st_nor_read_fsr()
520 			op.dummy.nbytes = nor->params->rdsr_dummy;  in micron_st_nor_read_fsr()
528 		spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);  in micron_st_nor_read_fsr()
530 		ret = spi_mem_exec_op(nor->spimem, &op);  in micron_st_nor_read_fsr()
537 		dev_dbg(nor->dev, "error %d reading FSR\n", ret);  in micron_st_nor_read_fsr()
543  * micron_st_nor_clear_fsr() - Clear the Flag Status Register.
550 	if (nor->spimem) {  in micron_st_nor_clear_fsr()
553 		spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);  in micron_st_nor_clear_fsr()
555 		ret = spi_mem_exec_op(nor->spimem, &op);  in micron_st_nor_clear_fsr()
562 		dev_dbg(nor->dev, "error %d clearing FSR\n", ret);  in micron_st_nor_clear_fsr()
566  * micron_st_nor_ready() - Query the Status Register as well as the Flag Status
571  * Return: 1 if ready, 0 if not ready, -errno on errors.
581 	ret = micron_st_nor_read_fsr(nor, nor->bouncebuf);  in micron_st_nor_ready()
590 		return ret == -EOPNOTSUPP ? sr_ready : ret;  in micron_st_nor_ready()
593 	if (nor->bouncebuf[0] & (FSR_E_ERR | FSR_P_ERR)) {  in micron_st_nor_ready()
594 		if (nor->bouncebuf[0] & FSR_E_ERR)  in micron_st_nor_ready()
595 			dev_err(nor->dev, "Erase operation failed.\n");  in micron_st_nor_ready()
597 			dev_err(nor->dev, "Program operation failed.\n");  in micron_st_nor_ready()
599 		if (nor->bouncebuf[0] & FSR_PT_ERR)  in micron_st_nor_ready()
600 			dev_err(nor->dev,  in micron_st_nor_ready()
606 		 * WEL bit remains set to one when an erase or page program  in micron_st_nor_ready()
615 		return -EIO;  in micron_st_nor_ready()
618 	return sr_ready && !!(nor->bouncebuf[0] & FSR_READY);  in micron_st_nor_ready()
623 	nor->flags |= SNOR_F_HAS_LOCK;  in micron_st_nor_default_init()
624 	nor->flags &= ~SNOR_F_HAS_16BIT_SR;  in micron_st_nor_default_init()
625 	nor->params->quad_enable = NULL;  in micron_st_nor_default_init()
630 	struct spi_nor_flash_parameter *params = nor->params;  in micron_st_nor_late_init()
632 	if (nor->info->mfr_flags & USE_FSR)  in micron_st_nor_late_init()
633 		params->ready = micron_st_nor_ready;  in micron_st_nor_late_init()
635 	if (!params->set_4byte_addr_mode)  in micron_st_nor_late_init()
636 		params->set_4byte_addr_mode = spi_nor_set_4byte_addr_mode_wren_en4b_ex4b;  in micron_st_nor_late_init()