Lines Matching +full:ecc +full:- +full:size
1 // SPDX-License-Identifier: GPL-2.0
6 #include <linux/dma-mapping.h>
73 /* Define for the BCH hardware ECC engine */
119 return -ERANGE; in ma35_ooblayout_ecc()
121 oob_region->length = chip->ecc.total; in ma35_ooblayout_ecc()
122 oob_region->offset = mtd->oobsize - oob_region->length; in ma35_ooblayout_ecc()
133 return -ERANGE; in ma35_ooblayout_free()
135 oob_region->length = mtd->oobsize - chip->ecc.total - 2; in ma35_ooblayout_free()
136 oob_region->offset = 2; in ma35_ooblayout_free()
143 .ecc = ma35_ooblayout_ecc,
146 static inline void ma35_clear_spare(struct nand_chip *chip, int size) in ma35_clear_spare() argument
151 for (i = 0; i < size / 4; i++) in ma35_clear_spare()
152 writel(0xff, nand->regs + MA35_NFI_REG_NANDRA0); in ma35_clear_spare()
156 u32 offset, int size, int swap) in read_remaining_bytes() argument
158 u32 value = readl(nand->regs + MA35_NFI_REG_NANDRA0 + offset); in read_remaining_bytes()
162 for (i = 0; i < size; i++) { in read_remaining_bytes()
163 shift = (swap ? 3 - i : i) * 8; in read_remaining_bytes()
168 static inline void ma35_read_spare(struct nand_chip *chip, int size, u32 *buf, u32 offset) in ma35_read_spare() argument
176 read_remaining_bytes(nand, buf, off, 4 - len, 1); in ma35_read_spare()
178 size -= (4 - len); in ma35_read_spare()
181 for (i = 0; i < size / 4; i++) in ma35_read_spare()
182 *buf++ = readl(nand->regs + MA35_NFI_REG_NANDRA0 + off + (i * 4)); in ma35_read_spare()
184 read_remaining_bytes(nand, buf, off + (size & ~3), size % 4, 0); in ma35_read_spare()
187 static inline void ma35_write_spare(struct nand_chip *chip, int size, u32 *buf) in ma35_write_spare() argument
194 for (i = 0, j = 0; i < size / 4; i++, j += 4) in ma35_write_spare()
195 writel(*buf++, nand->regs + MA35_NFI_REG_NANDRA0 + j); in ma35_write_spare()
198 switch (size % 4) { in ma35_write_spare()
200 writel(*ptr, nand->regs + MA35_NFI_REG_NANDRA0 + j); in ma35_write_spare()
204 writel(value, nand->regs + MA35_NFI_REG_NANDRA0 + j); in ma35_write_spare()
208 writel(value, nand->regs + MA35_NFI_REG_NANDRA0 + j); in ma35_write_spare()
222 reg = readl(nand->regs + MA35_NFI_REG_NANDCTL); in ma35_nand_target_enable()
223 writel(reg & ~DISABLE_CS0, nand->regs + MA35_NFI_REG_NANDCTL); in ma35_nand_target_enable()
225 reg = readl(nand->regs + MA35_NFI_REG_NANDINTSTS); in ma35_nand_target_enable()
227 writel(reg, nand->regs + MA35_NFI_REG_NANDINTSTS); in ma35_nand_target_enable()
238 struct device *dev = mtd->dev.parent; in ma35_nand_hwecc_init()
241 nand->buffer = devm_kzalloc(dev, mtd->writesize, GFP_KERNEL); in ma35_nand_hwecc_init()
242 if (!nand->buffer) in ma35_nand_hwecc_init()
243 return -ENOMEM; in ma35_nand_hwecc_init()
245 /* Redundant area size */ in ma35_nand_hwecc_init()
246 writel(mtd->oobsize, nand->regs + MA35_NFI_REG_NANDRACTL); in ma35_nand_hwecc_init()
248 /* Protect redundant 3 bytes and disable ECC engine */ in ma35_nand_hwecc_init()
249 reg = readl(nand->regs + MA35_NFI_REG_NANDCTL); in ma35_nand_hwecc_init()
253 if (chip->ecc.strength != 0) { in ma35_nand_hwecc_init()
254 chip->ecc.steps = mtd->writesize / chip->ecc.size; in ma35_nand_hwecc_init()
255 nvtnand->eccstatus = (chip->ecc.steps < 4) ? 1 : chip->ecc.steps / 4; in ma35_nand_hwecc_init()
258 switch (chip->ecc.strength) { in ma35_nand_hwecc_init()
260 chip->ecc.total = chip->ecc.steps * MA35_PARITY_BCH8; in ma35_nand_hwecc_init()
264 chip->ecc.total = chip->ecc.steps * MA35_PARITY_BCH12; in ma35_nand_hwecc_init()
268 chip->ecc.total = chip->ecc.steps * MA35_PARITY_BCH24; in ma35_nand_hwecc_init()
272 dev_err(nand->dev, "ECC strength unsupported\n"); in ma35_nand_hwecc_init()
273 return -EINVAL; in ma35_nand_hwecc_init()
276 chip->ecc.bytes = chip->ecc.total / chip->ecc.steps; in ma35_nand_hwecc_init()
278 writel(reg, nand->regs + MA35_NFI_REG_NANDCTL); in ma35_nand_hwecc_init()
294 if (chip->ecc.strength <= 8) { in ma35_nfi_correct()
297 } else if (chip->ecc.strength <= 12) { in ma35_nfi_correct()
300 } else if (chip->ecc.strength <= 24) { in ma35_nfi_correct()
304 dev_err(nand->dev, "Invalid BCH_TSEL = 0x%lx\n", in ma35_nfi_correct()
305 readl(nand->regs + MA35_NFI_REG_NANDCTL) & BCH_MASK); in ma35_nfi_correct()
317 err_data[i] = readl(nand->regs + MA35_NFI_REG_NANDECCED0 + i * 4); in ma35_nfi_correct()
334 temp_addr[i * 2 + 0] = readl(nand->regs + MA35_NFI_REG_NANDECCEA0 + i * 4) in ma35_nfi_correct()
336 temp_addr[i * 2 + 1] = (readl(nand->regs + MA35_NFI_REG_NANDECCEA0 + i * 4) in ma35_nfi_correct()
341 addr += index * chip->ecc.size; in ma35_nfi_correct()
347 if (corrected_index < chip->ecc.size) { in ma35_nfi_correct()
350 } else if (corrected_index < (chip->ecc.size + 3)) { in ma35_nfi_correct()
351 /* for wrong first-3-bytes in redundancy area */ in ma35_nfi_correct()
352 corrected_index -= chip->ecc.size; in ma35_nfi_correct()
355 value = readl(nand->regs + MA35_NFI_REG_NANDRA0); in ma35_nfi_correct()
357 writel(value, nand->regs + MA35_NFI_REG_NANDRA0); in ma35_nfi_correct()
362 * |<-- padding bytes -->| in ma35_nfi_correct()
363 * The ERR_ADDRx for last parity code always = field size + padding size. in ma35_nfi_correct()
364 * The first parity code = field size + padding size - parity code length. in ma35_nfi_correct()
365 * For example, for BCH T12, the first parity code = 512 + 32 - 23 = 521. in ma35_nfi_correct()
368 corrected_index -= (chip->ecc.size + padding_len - parity_len); in ma35_nfi_correct()
375 offset = (readl(nand->regs + MA35_NFI_REG_NANDRACTL) & 0x1ff) - in ma35_nfi_correct()
376 (parity_len * chip->ecc.steps) + in ma35_nfi_correct()
380 value = readl(nand->regs + MA35_NFI_REG_NANDRA0 + offset - remain); in ma35_nfi_correct()
382 writel(value, nand->regs + MA35_NFI_REG_NANDRA0 + offset - remain); in ma35_nfi_correct()
397 for (j = 0; j < nvtnand->eccstatus; j++) { in ma35_nfi_ecc_check()
398 status = readl(nand->regs + MA35_NFI_REG_NANDECCES0 + j * 4); in ma35_nfi_ecc_check()
408 mtd->ecc_stats.corrected += cnt; in ma35_nfi_ecc_check()
411 mtd->ecc_stats.failed++; in ma35_nfi_ecc_check()
412 dev_err(nand->dev, "uncorrectable error! 0x%4x\n", status); in ma35_nfi_ecc_check()
413 return -EBADMSG; in ma35_nfi_ecc_check()
424 writel(DMA_RST | DMA_EN, nand->regs + MA35_NFI_REG_DMACTL); in ma35_nand_dmac_init()
425 writel(DMA_EN, nand->regs + MA35_NFI_REG_DMACTL); in ma35_nand_dmac_init()
428 writel(INT_DMA | INT_ECC, nand->regs + MA35_NFI_REG_NANDINTSTS); in ma35_nand_dmac_init()
429 writel(INT_DMA, nand->regs + MA35_NFI_REG_NANDINTEN); in ma35_nand_dmac_init()
440 if (len != mtd->writesize) { in ma35_nand_do_write()
442 writel(addr[i], nand->regs + MA35_NFI_REG_NANDDATA); in ma35_nand_do_write()
449 reg = readl(nand->regs + MA35_NFI_REG_NANDRA0); in ma35_nand_do_write()
451 writel(reg & 0xffff, nand->regs + MA35_NFI_REG_NANDRA0); in ma35_nand_do_write()
453 dma_addr = dma_map_single(nand->dev, (void *)addr, len, DMA_TO_DEVICE); in ma35_nand_do_write()
454 ret = dma_mapping_error(nand->dev, dma_addr); in ma35_nand_do_write()
456 dev_err(nand->dev, "dma mapping error\n"); in ma35_nand_do_write()
457 return -EINVAL; in ma35_nand_do_write()
459 dma_sync_single_for_device(nand->dev, dma_addr, len, DMA_TO_DEVICE); in ma35_nand_do_write()
461 reinit_completion(&nand->complete); in ma35_nand_do_write()
462 writel(dma_addr, nand->regs + MA35_NFI_REG_DMASA); in ma35_nand_do_write()
463 writel(readl(nand->regs + MA35_NFI_REG_NANDCTL) | DMA_W_EN, in ma35_nand_do_write()
464 nand->regs + MA35_NFI_REG_NANDCTL); in ma35_nand_do_write()
465 ret = wait_for_completion_timeout(&nand->complete, msecs_to_jiffies(1000)); in ma35_nand_do_write()
467 dev_err(nand->dev, "write timeout\n"); in ma35_nand_do_write()
468 ret = -ETIMEDOUT; in ma35_nand_do_write()
471 dma_unmap_single(nand->dev, dma_addr, len, DMA_TO_DEVICE); in ma35_nand_do_write()
484 if (len != mtd->writesize) { in ma35_nand_do_read()
486 addr[i] = readb(nand->regs + MA35_NFI_REG_NANDDATA); in ma35_nand_do_read()
493 dma_addr = dma_map_single(nand->dev, (void *)addr, len, DMA_FROM_DEVICE); in ma35_nand_do_read()
494 ret = dma_mapping_error(nand->dev, dma_addr); in ma35_nand_do_read()
496 dev_err(nand->dev, "dma mapping error\n"); in ma35_nand_do_read()
497 return -EINVAL; in ma35_nand_do_read()
500 reinit_completion(&nand->complete); in ma35_nand_do_read()
501 writel(dma_addr, nand->regs + MA35_NFI_REG_DMASA); in ma35_nand_do_read()
502 writel(readl(nand->regs + MA35_NFI_REG_NANDCTL) | DMA_R_EN, in ma35_nand_do_read()
503 nand->regs + MA35_NFI_REG_NANDCTL); in ma35_nand_do_read()
504 ret = wait_for_completion_timeout(&nand->complete, msecs_to_jiffies(1000)); in ma35_nand_do_read()
506 dev_err(nand->dev, "read timeout\n"); in ma35_nand_do_read()
507 ret = -ETIMEDOUT; in ma35_nand_do_read()
510 dma_unmap_single(nand->dev, dma_addr, len, DMA_FROM_DEVICE); in ma35_nand_do_read()
512 reg = readl(nand->regs + MA35_NFI_REG_NANDINTSTS); in ma35_nand_do_read()
516 writel(DMA_RST | DMA_EN, nand->regs + MA35_NFI_REG_DMACTL); in ma35_nand_do_read()
517 writel(readl(nand->regs + MA35_NFI_REG_NANDCTL) | SWRST, in ma35_nand_do_read()
518 nand->regs + MA35_NFI_REG_NANDCTL); in ma35_nand_do_read()
520 writel(INT_ECC, nand->regs + MA35_NFI_REG_NANDINTSTS); in ma35_nand_do_read()
532 u32 page_off = round_down(offset, chip->ecc.size); in ma35_nand_format_subpage()
533 u32 end = DIV_ROUND_UP(page_off + len, chip->ecc.size); in ma35_nand_format_subpage()
534 u32 start = page_off / chip->ecc.size; in ma35_nand_format_subpage()
538 reg = readl(nand->regs + MA35_NFI_REG_NANDRACTL) | 0xffff0000; in ma35_nand_format_subpage()
539 memset(nand->buffer, 0xff, mtd->writesize); in ma35_nand_format_subpage()
541 memcpy(nand->buffer + i * chip->ecc.size, in ma35_nand_format_subpage()
542 buf + i * chip->ecc.size, chip->ecc.size); in ma35_nand_format_subpage()
545 writel(reg, nand->regs + MA35_NFI_REG_NANDRACTL); in ma35_nand_format_subpage()
559 /* Enable HW ECC engine */ in ma35_nand_write_subpage_hwecc()
560 reg = readl(nand->regs + MA35_NFI_REG_NANDCTL); in ma35_nand_write_subpage_hwecc()
561 writel(reg | ECC_EN, nand->regs + MA35_NFI_REG_NANDCTL); in ma35_nand_write_subpage_hwecc()
563 ma35_nand_target_enable(chip, chip->cur_cs); in ma35_nand_write_subpage_hwecc()
565 ma35_clear_spare(chip, mtd->oobsize); in ma35_nand_write_subpage_hwecc()
566 ma35_write_spare(chip, mtd->oobsize - chip->ecc.total, in ma35_nand_write_subpage_hwecc()
567 (u32 *)chip->oob_poi); in ma35_nand_write_subpage_hwecc()
571 ma35_nand_do_write(chip, nand->buffer, mtd->writesize); in ma35_nand_write_subpage_hwecc()
574 oobpoi = mtd->oobsize - chip->ecc.total; in ma35_nand_write_subpage_hwecc()
575 reg = readl(nand->regs + MA35_NFI_REG_NANDRACTL); in ma35_nand_write_subpage_hwecc()
576 for (i = 0; i < chip->ecc.steps; i++) { in ma35_nand_write_subpage_hwecc()
577 index = i * chip->ecc.bytes; in ma35_nand_write_subpage_hwecc()
579 ma35_read_spare(chip, chip->ecc.bytes, in ma35_nand_write_subpage_hwecc()
580 (u32 *)(chip->oob_poi + oobpoi + index), in ma35_nand_write_subpage_hwecc()
585 writel(mtd->oobsize, nand->regs + MA35_NFI_REG_NANDRACTL); in ma35_nand_write_subpage_hwecc()
586 /* Disable HW ECC engine */ in ma35_nand_write_subpage_hwecc()
587 reg = readl(nand->regs + MA35_NFI_REG_NANDCTL); in ma35_nand_write_subpage_hwecc()
588 writel(reg & ~ECC_EN, nand->regs + MA35_NFI_REG_NANDCTL); in ma35_nand_write_subpage_hwecc()
600 /* Enable HW ECC engine */ in ma35_nand_write_page_hwecc()
601 reg = readl(nand->regs + MA35_NFI_REG_NANDCTL); in ma35_nand_write_page_hwecc()
602 writel(reg | ECC_EN, nand->regs + MA35_NFI_REG_NANDCTL); in ma35_nand_write_page_hwecc()
604 ma35_nand_target_enable(chip, chip->cur_cs); in ma35_nand_write_page_hwecc()
606 ma35_clear_spare(chip, mtd->oobsize); in ma35_nand_write_page_hwecc()
607 ma35_write_spare(chip, mtd->oobsize - chip->ecc.total, in ma35_nand_write_page_hwecc()
608 (u32 *)chip->oob_poi); in ma35_nand_write_page_hwecc()
611 ma35_nand_do_write(chip, buf, mtd->writesize); in ma35_nand_write_page_hwecc()
614 ma35_read_spare(chip, chip->ecc.total, in ma35_nand_write_page_hwecc()
615 (u32 *)(chip->oob_poi + (mtd->oobsize - chip->ecc.total)), in ma35_nand_write_page_hwecc()
616 mtd->oobsize - chip->ecc.total); in ma35_nand_write_page_hwecc()
618 /* Disable HW ECC engine */ in ma35_nand_write_page_hwecc()
619 writel(reg & ~ECC_EN, nand->regs + MA35_NFI_REG_NANDCTL); in ma35_nand_write_page_hwecc()
632 /* Enable HW ECC engine */ in ma35_nand_read_subpage_hwecc()
633 reg = readl(nand->regs + MA35_NFI_REG_NANDCTL); in ma35_nand_read_subpage_hwecc()
634 writel(reg | ECC_EN, nand->regs + MA35_NFI_REG_NANDCTL); in ma35_nand_read_subpage_hwecc()
636 ma35_nand_target_enable(chip, chip->cur_cs); in ma35_nand_read_subpage_hwecc()
637 nand_read_oob_op(chip, page, 0, chip->oob_poi, mtd->oobsize); in ma35_nand_read_subpage_hwecc()
638 ma35_write_spare(chip, mtd->oobsize, (u32 *)chip->oob_poi); in ma35_nand_read_subpage_hwecc()
640 reg = readl(nand->regs + MA35_NFI_REG_NANDRA0); in ma35_nand_read_subpage_hwecc()
642 memset((void *)buf, 0xff, mtd->writesize); in ma35_nand_read_subpage_hwecc()
646 ma35_read_spare(chip, mtd->oobsize, (u32 *)chip->oob_poi, 0); in ma35_nand_read_subpage_hwecc()
649 /* Disable HW ECC engine */ in ma35_nand_read_subpage_hwecc()
650 reg = readl(nand->regs + MA35_NFI_REG_NANDCTL); in ma35_nand_read_subpage_hwecc()
651 writel(reg & ~ECC_EN, nand->regs + MA35_NFI_REG_NANDCTL); in ma35_nand_read_subpage_hwecc()
664 /* Enable HW ECC engine */ in ma35_nand_read_page_hwecc()
665 reg = readl(nand->regs + MA35_NFI_REG_NANDCTL); in ma35_nand_read_page_hwecc()
666 writel(reg | ECC_EN, nand->regs + MA35_NFI_REG_NANDCTL); in ma35_nand_read_page_hwecc()
668 ma35_nand_target_enable(chip, chip->cur_cs); in ma35_nand_read_page_hwecc()
669 nand_read_oob_op(chip, page, 0, chip->oob_poi, mtd->oobsize); in ma35_nand_read_page_hwecc()
670 ma35_write_spare(chip, mtd->oobsize, (u32 *)chip->oob_poi); in ma35_nand_read_page_hwecc()
672 reg = readl(nand->regs + MA35_NFI_REG_NANDRA0); in ma35_nand_read_page_hwecc()
674 memset((void *)buf, 0xff, mtd->writesize); in ma35_nand_read_page_hwecc()
677 bitflips = ma35_nand_do_read(chip, buf, mtd->writesize); in ma35_nand_read_page_hwecc()
678 ma35_read_spare(chip, mtd->oobsize, (u32 *)chip->oob_poi, 0); in ma35_nand_read_page_hwecc()
681 /* Disable HW ECC engine */ in ma35_nand_read_page_hwecc()
682 reg = readl(nand->regs + MA35_NFI_REG_NANDCTL); in ma35_nand_read_page_hwecc()
683 writel(reg & ~ECC_EN, nand->regs + MA35_NFI_REG_NANDCTL); in ma35_nand_read_page_hwecc()
694 ma35_nand_target_enable(chip, chip->cur_cs); in ma35_nand_read_oob_hwecc()
695 nand_read_oob_op(chip, page, 0, chip->oob_poi, mtd->oobsize); in ma35_nand_read_oob_hwecc()
698 ma35_write_spare(chip, mtd->oobsize, (u32 *)chip->oob_poi); in ma35_nand_read_oob_hwecc()
700 reg = readl(nand->regs + MA35_NFI_REG_NANDRA0); in ma35_nand_read_oob_hwecc()
702 memset((void *)chip->oob_poi, 0xff, mtd->oobsize); in ma35_nand_read_oob_hwecc()
712 writel(DISABLE_WP, nand->regs + MA35_NFI_REG_NANDECTL); in ma35_hw_init()
715 reg = readl(nand->regs + MA35_NFI_REG_NANDCTL); in ma35_hw_init()
717 writel(reg, nand->regs + MA35_NFI_REG_NANDCTL); in ma35_hw_init()
725 isr = readl(nand->regs + MA35_NFI_REG_NANDINTSTS); in ma35_nand_irq()
727 writel(INT_DMA, nand->regs + MA35_NFI_REG_NANDINTSTS); in ma35_nand_irq()
728 complete(&nand->complete); in ma35_nand_irq()
739 struct device *dev = mtd->dev.parent; in ma35_nand_attach_chip()
742 if (chip->options & NAND_BUSWIDTH_16) { in ma35_nand_attach_chip()
744 return -EINVAL; in ma35_nand_attach_chip()
747 reg = readl(nand->regs + MA35_NFI_REG_NANDCTL) & (~PSIZE_MASK); in ma35_nand_attach_chip()
748 switch (mtd->writesize) { in ma35_nand_attach_chip()
750 writel(reg | PSIZE_2K, nand->regs + MA35_NFI_REG_NANDCTL); in ma35_nand_attach_chip()
753 writel(reg | PSIZE_4K, nand->regs + MA35_NFI_REG_NANDCTL); in ma35_nand_attach_chip()
756 writel(reg | PSIZE_8K, nand->regs + MA35_NFI_REG_NANDCTL); in ma35_nand_attach_chip()
759 dev_err(dev, "Unsupported page size"); in ma35_nand_attach_chip()
760 return -EINVAL; in ma35_nand_attach_chip()
763 switch (chip->ecc.engine_type) { in ma35_nand_attach_chip()
766 if (chip->bbt_options & NAND_BBT_USE_FLASH) in ma35_nand_attach_chip()
767 chip->bbt_options |= NAND_BBT_NO_OOB; in ma35_nand_attach_chip()
768 chip->options |= NAND_USES_DMA | NAND_SUBPAGE_READ; in ma35_nand_attach_chip()
769 chip->ecc.write_subpage = ma35_nand_write_subpage_hwecc; in ma35_nand_attach_chip()
770 chip->ecc.write_page = ma35_nand_write_page_hwecc; in ma35_nand_attach_chip()
771 chip->ecc.read_subpage = ma35_nand_read_subpage_hwecc; in ma35_nand_attach_chip()
772 chip->ecc.read_page = ma35_nand_read_page_hwecc; in ma35_nand_attach_chip()
773 chip->ecc.read_oob = ma35_nand_read_oob_hwecc; in ma35_nand_attach_chip()
780 return -EINVAL; in ma35_nand_attach_chip()
794 switch (instr->type) { in ma35_nfc_exec_instr()
796 writel(instr->ctx.cmd.opcode, nand->regs + MA35_NFI_REG_NANDCMD); in ma35_nfc_exec_instr()
799 for (i = 0; i < instr->ctx.addr.naddrs; i++) { in ma35_nfc_exec_instr()
800 if (i == (instr->ctx.addr.naddrs - 1)) in ma35_nfc_exec_instr()
801 writel(instr->ctx.addr.addrs[i] | ENDADDR, in ma35_nfc_exec_instr()
802 nand->regs + MA35_NFI_REG_NANDADDR); in ma35_nfc_exec_instr()
804 writel(instr->ctx.addr.addrs[i], in ma35_nfc_exec_instr()
805 nand->regs + MA35_NFI_REG_NANDADDR); in ma35_nfc_exec_instr()
809 ret = ma35_nand_do_read(chip, instr->ctx.data.buf.in, instr->ctx.data.len); in ma35_nfc_exec_instr()
812 ret = ma35_nand_do_write(chip, instr->ctx.data.buf.out, instr->ctx.data.len); in ma35_nfc_exec_instr()
815 return readl_poll_timeout(nand->regs + MA35_NFI_REG_NANDINTSTS, status, in ma35_nfc_exec_instr()
817 instr->ctx.waitrdy.timeout_ms * MSEC_PER_SEC); in ma35_nfc_exec_instr()
819 ret = -EINVAL; in ma35_nfc_exec_instr()
836 ma35_nand_target_enable(chip, op->cs); in ma35_nfc_exec_op()
838 for (i = 0; i < op->ninstrs; i++) { in ma35_nfc_exec_op()
839 ret = ma35_nfc_exec_instr(chip, &op->instrs[i]); in ma35_nfc_exec_op()
865 dev_err(dev, "invalid reg property size %d\n", nsels); in ma35_nand_chip_init()
866 return -EINVAL; in ma35_nand_chip_init()
872 return -ENOMEM; in ma35_nand_chip_init()
874 nvtnand->nsels = nsels; in ma35_nand_chip_init()
884 return -EINVAL; in ma35_nand_chip_init()
887 if (test_and_set_bit(cs, &nand->assigned_cs)) { in ma35_nand_chip_init()
889 return -EINVAL; in ma35_nand_chip_init()
892 nvtnand->sels[i] = cs; in ma35_nand_chip_init()
895 chip = &nvtnand->chip; in ma35_nand_chip_init()
896 chip->controller = &nand->controller; in ma35_nand_chip_init()
902 mtd->owner = THIS_MODULE; in ma35_nand_chip_init()
903 mtd->dev.parent = dev; in ma35_nand_chip_init()
916 list_add_tail(&nvtnand->node, &nand->chips); in ma35_nand_chip_init()
927 list_for_each_entry_safe(nvtnand, tmp, &nand->chips, node) { in ma35_chips_cleanup()
928 chip = &nvtnand->chip; in ma35_chips_cleanup()
932 list_del(&nvtnand->node); in ma35_chips_cleanup()
938 struct device_node *np = dev->of_node, *nand_np; in ma35_nand_chips_init()
956 nand = devm_kzalloc(&pdev->dev, sizeof(*nand), GFP_KERNEL); in ma35_nand_probe()
958 return -ENOMEM; in ma35_nand_probe()
960 nand_controller_init(&nand->controller); in ma35_nand_probe()
961 INIT_LIST_HEAD(&nand->chips); in ma35_nand_probe()
962 nand->controller.ops = &ma35_nfc_ops; in ma35_nand_probe()
964 init_completion(&nand->complete); in ma35_nand_probe()
966 nand->regs = devm_platform_ioremap_resource(pdev, 0); in ma35_nand_probe()
967 if (IS_ERR(nand->regs)) in ma35_nand_probe()
968 return PTR_ERR(nand->regs); in ma35_nand_probe()
970 nand->dev = &pdev->dev; in ma35_nand_probe()
972 nand->clk = devm_clk_get_enabled(&pdev->dev, "nand_gate"); in ma35_nand_probe()
973 if (IS_ERR(nand->clk)) in ma35_nand_probe()
974 return dev_err_probe(&pdev->dev, PTR_ERR(nand->clk), in ma35_nand_probe()
977 nand->irq = platform_get_irq(pdev, 0); in ma35_nand_probe()
978 if (nand->irq < 0) in ma35_nand_probe()
979 return dev_err_probe(&pdev->dev, nand->irq, in ma35_nand_probe()
982 ret = devm_request_irq(&pdev->dev, nand->irq, ma35_nand_irq, in ma35_nand_probe()
983 IRQF_TRIGGER_HIGH, "ma35d1-nand-controller", nand); in ma35_nand_probe()
985 dev_err(&pdev->dev, "failed to request NAND irq\n"); in ma35_nand_probe()
986 return -ENXIO; in ma35_nand_probe()
991 writel(GRST | NAND_EN, nand->regs + MA35_NFI_REG_GCTL); in ma35_nand_probe()
993 ret = ma35_nand_chips_init(&pdev->dev, nand); in ma35_nand_probe()
995 dev_err(&pdev->dev, "failed to init NAND chips\n"); in ma35_nand_probe()
996 clk_disable(nand->clk); in ma35_nand_probe()
1011 { .compatible = "nuvoton,ma35d1-nand-controller" },
1018 .name = "ma35d1-nand-controller",
1028 MODULE_AUTHOR("Hui-Ping Chen <[email protected]>");