Lines Matching +full:chip +full:- +full:id
1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
20 * struct hynix_read_retry - read-retry data
21 * @nregs: number of register to set when applying a new read-retry mode
22 * @regs: register offsets (NAND chip dependent)
33 * struct hynix_nand - private Hynix NAND struct
34 * @read_retry: read-retry information
41 * struct hynix_read_retry_otp - structure describing how the read-retry OTP
48 * chip
49 * @size: size of the read-retry OTP section
59 static bool hynix_nand_has_valid_jedecid(struct nand_chip *chip) in hynix_nand_has_valid_jedecid() argument
64 ret = nand_readid_op(chip, 0x40, jedecid, sizeof(jedecid)); in hynix_nand_has_valid_jedecid()
71 static int hynix_nand_cmd_op(struct nand_chip *chip, u8 cmd) in hynix_nand_cmd_op() argument
73 if (nand_has_exec_op(chip)) { in hynix_nand_cmd_op()
77 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs); in hynix_nand_cmd_op()
79 return nand_exec_op(chip, &op); in hynix_nand_cmd_op()
82 chip->legacy.cmdfunc(chip, cmd, -1, -1); in hynix_nand_cmd_op()
87 static int hynix_nand_reg_write_op(struct nand_chip *chip, u8 addr, u8 val) in hynix_nand_reg_write_op() argument
91 if (nand_has_exec_op(chip)) { in hynix_nand_reg_write_op()
96 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs); in hynix_nand_reg_write_op()
98 return nand_exec_op(chip, &op); in hynix_nand_reg_write_op()
101 chip->legacy.cmdfunc(chip, NAND_CMD_NONE, column, -1); in hynix_nand_reg_write_op()
102 chip->legacy.write_byte(chip, val); in hynix_nand_reg_write_op()
107 static int hynix_nand_setup_read_retry(struct nand_chip *chip, int retry_mode) in hynix_nand_setup_read_retry() argument
109 struct hynix_nand *hynix = nand_get_manufacturer_data(chip); in hynix_nand_setup_read_retry()
113 values = hynix->read_retry->values + in hynix_nand_setup_read_retry()
114 (retry_mode * hynix->read_retry->nregs); in hynix_nand_setup_read_retry()
117 ret = hynix_nand_cmd_op(chip, NAND_HYNIX_CMD_SET_PARAMS); in hynix_nand_setup_read_retry()
122 * Configure the NAND in the requested read-retry mode. in hynix_nand_setup_read_retry()
123 * This is done by setting pre-defined values in internal NAND in hynix_nand_setup_read_retry()
130 for (i = 0; i < hynix->read_retry->nregs; i++) { in hynix_nand_setup_read_retry()
131 ret = hynix_nand_reg_write_op(chip, hynix->read_retry->regs[i], in hynix_nand_setup_read_retry()
138 return hynix_nand_cmd_op(chip, NAND_HYNIX_CMD_APPLY_PARAMS); in hynix_nand_setup_read_retry()
142 * hynix_get_majority - get the value that is occurring the most in a given
150 * the read-retry parameters.
155 * Let's hope this dummy algorithm prevents us from losing the read-retry
187 return -EIO; in hynix_get_majority()
190 static int hynix_read_rr_otp(struct nand_chip *chip, in hynix_read_rr_otp() argument
196 ret = nand_reset_op(chip); in hynix_read_rr_otp()
200 ret = hynix_nand_cmd_op(chip, NAND_HYNIX_CMD_SET_PARAMS); in hynix_read_rr_otp()
204 for (i = 0; i < info->nregs; i++) { in hynix_read_rr_otp()
205 ret = hynix_nand_reg_write_op(chip, info->regs[i], in hynix_read_rr_otp()
206 info->values[i]); in hynix_read_rr_otp()
211 ret = hynix_nand_cmd_op(chip, NAND_HYNIX_CMD_APPLY_PARAMS); in hynix_read_rr_otp()
216 ret = hynix_nand_cmd_op(chip, 0x17); in hynix_read_rr_otp()
220 ret = hynix_nand_cmd_op(chip, 0x4); in hynix_read_rr_otp()
224 ret = hynix_nand_cmd_op(chip, 0x19); in hynix_read_rr_otp()
229 ret = nand_read_page_op(chip, info->page, 0, buf, info->size); in hynix_read_rr_otp()
234 ret = nand_reset_op(chip); in hynix_read_rr_otp()
238 ret = hynix_nand_cmd_op(chip, NAND_HYNIX_CMD_SET_PARAMS); in hynix_read_rr_otp()
242 ret = hynix_nand_reg_write_op(chip, 0x38, 0); in hynix_read_rr_otp()
246 ret = hynix_nand_cmd_op(chip, NAND_HYNIX_CMD_APPLY_PARAMS); in hynix_read_rr_otp()
250 return nand_read_page_op(chip, 0, 0, NULL, 0); in hynix_read_rr_otp()
286 static int hynix_mlc_1xnm_rr_init(struct nand_chip *chip, in hynix_mlc_1xnm_rr_init() argument
289 struct hynix_nand *hynix = nand_get_manufacturer_data(chip); in hynix_mlc_1xnm_rr_init()
295 buf = kmalloc(info->size, GFP_KERNEL); in hynix_mlc_1xnm_rr_init()
297 return -ENOMEM; in hynix_mlc_1xnm_rr_init()
299 ret = hynix_read_rr_otp(chip, info, buf); in hynix_mlc_1xnm_rr_init()
316 ret = -ENOMEM; in hynix_mlc_1xnm_rr_init()
322 u8 *val = rr->values + (i * nregs); in hynix_mlc_1xnm_rr_init()
336 rr->nregs = nregs; in hynix_mlc_1xnm_rr_init()
337 rr->regs = hynix_1xnm_mlc_read_retry_regs; in hynix_mlc_1xnm_rr_init()
338 hynix->read_retry = rr; in hynix_mlc_1xnm_rr_init()
339 chip->ops.setup_read_retry = hynix_nand_setup_read_retry; in hynix_mlc_1xnm_rr_init()
340 chip->read_retries = nmodes; in hynix_mlc_1xnm_rr_init()
371 static int hynix_nand_rr_init(struct nand_chip *chip) in hynix_nand_rr_init() argument
376 valid_jedecid = hynix_nand_has_valid_jedecid(chip); in hynix_nand_rr_init()
379 * We only support read-retry for 1xnm NANDs, and those NANDs all in hynix_nand_rr_init()
380 * expose a valid JEDEC ID. in hynix_nand_rr_init()
383 u8 nand_tech = chip->id.data[5] >> 4; in hynix_nand_rr_init()
391 * read-retry OTP area into a normal page. in hynix_nand_rr_init()
393 ret = hynix_mlc_1xnm_rr_init(chip, in hynix_nand_rr_init()
402 pr_warn("failed to initialize read-retry infrastructure"); in hynix_nand_rr_init()
407 static void hynix_nand_extract_oobsize(struct nand_chip *chip, in hynix_nand_extract_oobsize() argument
410 struct mtd_info *mtd = nand_to_mtd(chip); in hynix_nand_extract_oobsize()
414 memorg = nanddev_get_memorg(&chip->base); in hynix_nand_extract_oobsize()
416 oobsize = ((chip->id.data[3] >> 2) & 0x3) | in hynix_nand_extract_oobsize()
417 ((chip->id.data[3] >> 4) & 0x4); in hynix_nand_extract_oobsize()
422 memorg->oobsize = 2048; in hynix_nand_extract_oobsize()
425 memorg->oobsize = 1664; in hynix_nand_extract_oobsize()
428 memorg->oobsize = 1024; in hynix_nand_extract_oobsize()
431 memorg->oobsize = 640; in hynix_nand_extract_oobsize()
437 * a different extended ID format, and we should find in hynix_nand_extract_oobsize()
446 memorg->oobsize = 128; in hynix_nand_extract_oobsize()
449 memorg->oobsize = 224; in hynix_nand_extract_oobsize()
452 memorg->oobsize = 448; in hynix_nand_extract_oobsize()
455 memorg->oobsize = 64; in hynix_nand_extract_oobsize()
458 memorg->oobsize = 32; in hynix_nand_extract_oobsize()
461 memorg->oobsize = 16; in hynix_nand_extract_oobsize()
464 memorg->oobsize = 640; in hynix_nand_extract_oobsize()
470 * a different extended ID format, and we should find in hynix_nand_extract_oobsize()
479 * Area Size" is encoded "per 8KB" (page size). This chip uses in hynix_nand_extract_oobsize()
481 * 1.280 bytes, but the OOB size encoded in the ID bytes (using in hynix_nand_extract_oobsize()
483 * Update the OOB size for this chip by taking the value in hynix_nand_extract_oobsize()
485 * the actual OOB size for this chip is: 640 * 16k / 8k). in hynix_nand_extract_oobsize()
487 if (chip->id.data[1] == 0xde) in hynix_nand_extract_oobsize()
488 memorg->oobsize *= memorg->pagesize / SZ_8K; in hynix_nand_extract_oobsize()
491 mtd->oobsize = memorg->oobsize; in hynix_nand_extract_oobsize()
494 static void hynix_nand_extract_ecc_requirements(struct nand_chip *chip, in hynix_nand_extract_ecc_requirements() argument
497 struct nand_device *base = &chip->base; in hynix_nand_extract_ecc_requirements()
499 u8 ecc_level = (chip->id.data[4] >> 4) & 0x7; in hynix_nand_extract_ecc_requirements()
532 * a different extended ID format, and we should find in hynix_nand_extract_ecc_requirements()
542 u8 nand_tech = chip->id.data[5] & 0x7; in hynix_nand_extract_ecc_requirements()
559 * to use a different extended ID format, and in hynix_nand_extract_ecc_requirements()
571 requirements.strength = 1 << (ecc_level - 1); in hynix_nand_extract_ecc_requirements()
575 (8 * (ecc_level - 5)); in hynix_nand_extract_ecc_requirements()
583 static void hynix_nand_extract_scrambling_requirements(struct nand_chip *chip, in hynix_nand_extract_scrambling_requirements() argument
589 if (nanddev_bits_per_cell(&chip->base) > 2) in hynix_nand_extract_scrambling_requirements()
590 chip->options |= NAND_NEED_SCRAMBLING; in hynix_nand_extract_scrambling_requirements()
592 /* And on MLC NANDs with sub-3xnm process */ in hynix_nand_extract_scrambling_requirements()
594 nand_tech = chip->id.data[5] >> 4; in hynix_nand_extract_scrambling_requirements()
598 chip->options |= NAND_NEED_SCRAMBLING; in hynix_nand_extract_scrambling_requirements()
600 nand_tech = chip->id.data[5] & 0x7; in hynix_nand_extract_scrambling_requirements()
604 chip->options |= NAND_NEED_SCRAMBLING; in hynix_nand_extract_scrambling_requirements()
608 static void hynix_nand_decode_id(struct nand_chip *chip) in hynix_nand_decode_id() argument
610 struct mtd_info *mtd = nand_to_mtd(chip); in hynix_nand_decode_id()
615 memorg = nanddev_get_memorg(&chip->base); in hynix_nand_decode_id()
620 * appear that even SLC NANDs could fall in this extended ID scheme. in hynix_nand_decode_id()
624 if (chip->id.len < 6 || nand_is_slc(chip)) { in hynix_nand_decode_id()
625 nand_decode_ext_id(chip); in hynix_nand_decode_id()
630 memorg->pagesize = 2048 << (chip->id.data[3] & 0x03); in hynix_nand_decode_id()
631 mtd->writesize = memorg->pagesize; in hynix_nand_decode_id()
633 tmp = (chip->id.data[3] >> 4) & 0x3; in hynix_nand_decode_id()
637 * ID[3][4:5]. in hynix_nand_decode_id()
638 * The only exception is when ID[3][4:5] == 3 and ID[3][7] == 0, in in hynix_nand_decode_id()
641 if (chip->id.data[3] & 0x80) { in hynix_nand_decode_id()
642 memorg->pages_per_eraseblock = (SZ_1M << tmp) / in hynix_nand_decode_id()
643 memorg->pagesize; in hynix_nand_decode_id()
644 mtd->erasesize = SZ_1M << tmp; in hynix_nand_decode_id()
646 memorg->pages_per_eraseblock = (SZ_512K + SZ_256K) / in hynix_nand_decode_id()
647 memorg->pagesize; in hynix_nand_decode_id()
648 mtd->erasesize = SZ_512K + SZ_256K; in hynix_nand_decode_id()
650 memorg->pages_per_eraseblock = (SZ_128K << tmp) / in hynix_nand_decode_id()
651 memorg->pagesize; in hynix_nand_decode_id()
652 mtd->erasesize = SZ_128K << tmp; in hynix_nand_decode_id()
658 * These NANDs use a different NAND ID scheme. in hynix_nand_decode_id()
660 valid_jedecid = hynix_nand_has_valid_jedecid(chip); in hynix_nand_decode_id()
662 hynix_nand_extract_oobsize(chip, valid_jedecid); in hynix_nand_decode_id()
663 hynix_nand_extract_ecc_requirements(chip, valid_jedecid); in hynix_nand_decode_id()
664 hynix_nand_extract_scrambling_requirements(chip, valid_jedecid); in hynix_nand_decode_id()
667 static void hynix_nand_cleanup(struct nand_chip *chip) in hynix_nand_cleanup() argument
669 struct hynix_nand *hynix = nand_get_manufacturer_data(chip); in hynix_nand_cleanup()
674 kfree(hynix->read_retry); in hynix_nand_cleanup()
676 nand_set_manufacturer_data(chip, NULL); in hynix_nand_cleanup()
680 h27ucg8t2atrbc_choose_interface_config(struct nand_chip *chip, in h27ucg8t2atrbc_choose_interface_config() argument
683 onfi_fill_interface_config(chip, iface, NAND_SDR_IFACE, 4); in h27ucg8t2atrbc_choose_interface_config()
685 return nand_choose_best_sdr_timings(chip, iface, NULL); in h27ucg8t2atrbc_choose_interface_config()
688 static int h27ucg8t2etrbc_init(struct nand_chip *chip) in h27ucg8t2etrbc_init() argument
690 struct mtd_info *mtd = nand_to_mtd(chip); in h27ucg8t2etrbc_init()
692 chip->options |= NAND_NEED_SCRAMBLING; in h27ucg8t2etrbc_init()
698 static int hynix_nand_init(struct nand_chip *chip) in hynix_nand_init() argument
703 if (!nand_is_slc(chip)) in hynix_nand_init()
704 chip->options |= NAND_BBM_LASTPAGE; in hynix_nand_init()
706 chip->options |= NAND_BBM_FIRSTPAGE | NAND_BBM_SECONDPAGE; in hynix_nand_init()
710 return -ENOMEM; in hynix_nand_init()
712 nand_set_manufacturer_data(chip, hynix); in hynix_nand_init()
714 if (!strncmp("H27UCG8T2ATR-BC", chip->parameters.model, in hynix_nand_init()
715 sizeof("H27UCG8T2ATR-BC") - 1)) in hynix_nand_init()
716 chip->ops.choose_interface_config = in hynix_nand_init()
719 if (!strncmp("H27UCG8T2ETR-BC", chip->parameters.model, in hynix_nand_init()
720 sizeof("H27UCG8T2ETR-BC") - 1)) in hynix_nand_init()
721 h27ucg8t2etrbc_init(chip); in hynix_nand_init()
723 ret = hynix_nand_rr_init(chip); in hynix_nand_init()
725 hynix_nand_cleanup(chip); in hynix_nand_init()
730 static void hynix_fixup_onfi_param_page(struct nand_chip *chip, in hynix_fixup_onfi_param_page() argument
735 * (bytes 129-130). This has been seen on H27U4G8F2GDA-BI. in hynix_fixup_onfi_param_page()
739 p->sdr_timing_modes |= cpu_to_le16(BIT(0)); in hynix_fixup_onfi_param_page()