Lines Matching +full:bank +full:- +full:ioport
1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Copyright © 2006-2007, 2010 Freescale Semiconductor
9 * Roy Zang <tie-[email protected]>
16 #include <linux/ioport.h>
41 int bank; /* Chip select bank number */ member
74 if (section >= chip->ecc.steps) in fsl_elbc_ooblayout_ecc()
75 return -ERANGE; in fsl_elbc_ooblayout_ecc()
77 oobregion->offset = (16 * section) + 6; in fsl_elbc_ooblayout_ecc()
78 if (priv->fmr & FMR_ECCM) in fsl_elbc_ooblayout_ecc()
79 oobregion->offset += 2; in fsl_elbc_ooblayout_ecc()
81 oobregion->length = chip->ecc.bytes; in fsl_elbc_ooblayout_ecc()
92 if (section > chip->ecc.steps) in fsl_elbc_ooblayout_free()
93 return -ERANGE; in fsl_elbc_ooblayout_free()
96 oobregion->offset = 0; in fsl_elbc_ooblayout_free()
97 if (mtd->writesize > 512) in fsl_elbc_ooblayout_free()
98 oobregion->offset++; in fsl_elbc_ooblayout_free()
99 oobregion->length = (priv->fmr & FMR_ECCM) ? 7 : 5; in fsl_elbc_ooblayout_free()
101 oobregion->offset = (16 * section) - in fsl_elbc_ooblayout_free()
102 ((priv->fmr & FMR_ECCM) ? 5 : 7); in fsl_elbc_ooblayout_free()
103 if (section < chip->ecc.steps) in fsl_elbc_ooblayout_free()
104 oobregion->length = 13; in fsl_elbc_ooblayout_free()
106 oobregion->length = mtd->oobsize - oobregion->offset; in fsl_elbc_ooblayout_free()
155 struct fsl_lbc_ctrl *ctrl = priv->ctrl; in set_addr()
156 struct fsl_lbc_regs __iomem *lbc = ctrl->regs; in set_addr()
157 struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = ctrl->nand; in set_addr()
160 elbc_fcm_ctrl->page = page_addr; in set_addr()
162 if (priv->page_size) { in set_addr()
167 out_be32(&lbc->fbar, page_addr >> 6); in set_addr()
168 out_be32(&lbc->fpar, in set_addr()
177 out_be32(&lbc->fbar, page_addr >> 5); in set_addr()
178 out_be32(&lbc->fpar, in set_addr()
184 elbc_fcm_ctrl->addr = priv->vbase + buf_num * 1024; in set_addr()
185 elbc_fcm_ctrl->index = column; in set_addr()
189 elbc_fcm_ctrl->index += priv->page_size ? 2048 : 512; in set_addr()
191 dev_vdbg(priv->dev, "set_addr: bank=%d, " in set_addr()
192 "elbc_fcm_ctrl->addr=0x%p (0x%p), " in set_addr()
194 buf_num, elbc_fcm_ctrl->addr, priv->vbase, in set_addr()
195 elbc_fcm_ctrl->index, in set_addr()
196 chip->phys_erase_shift, chip->page_shift); in set_addr()
206 struct fsl_lbc_ctrl *ctrl = priv->ctrl; in fsl_elbc_run_command()
207 struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = ctrl->nand; in fsl_elbc_run_command()
208 struct fsl_lbc_regs __iomem *lbc = ctrl->regs; in fsl_elbc_run_command()
211 out_be32(&lbc->fmr, priv->fmr | 3); in fsl_elbc_run_command()
212 if (elbc_fcm_ctrl->use_mdr) in fsl_elbc_run_command()
213 out_be32(&lbc->mdr, elbc_fcm_ctrl->mdr); in fsl_elbc_run_command()
215 dev_vdbg(priv->dev, in fsl_elbc_run_command()
217 in_be32(&lbc->fmr), in_be32(&lbc->fir), in_be32(&lbc->fcr)); in fsl_elbc_run_command()
218 dev_vdbg(priv->dev, in fsl_elbc_run_command()
220 "fbcr=%08x bank=%d\n", in fsl_elbc_run_command()
221 in_be32(&lbc->fbar), in_be32(&lbc->fpar), in fsl_elbc_run_command()
222 in_be32(&lbc->fbcr), priv->bank); in fsl_elbc_run_command()
224 ctrl->irq_status = 0; in fsl_elbc_run_command()
226 out_be32(&lbc->lsor, priv->bank); in fsl_elbc_run_command()
229 wait_event_timeout(ctrl->irq_wait, ctrl->irq_status, in fsl_elbc_run_command()
231 elbc_fcm_ctrl->status = ctrl->irq_status; in fsl_elbc_run_command()
233 if (elbc_fcm_ctrl->use_mdr) in fsl_elbc_run_command()
234 elbc_fcm_ctrl->mdr = in_be32(&lbc->mdr); in fsl_elbc_run_command()
236 elbc_fcm_ctrl->use_mdr = 0; in fsl_elbc_run_command()
238 if (elbc_fcm_ctrl->status != LTESR_CC) { in fsl_elbc_run_command()
239 dev_info(priv->dev, in fsl_elbc_run_command()
241 in_be32(&lbc->fir), in_be32(&lbc->fcr), in fsl_elbc_run_command()
242 elbc_fcm_ctrl->status, elbc_fcm_ctrl->mdr); in fsl_elbc_run_command()
243 return -EIO; in fsl_elbc_run_command()
246 if (chip->ecc.engine_type != NAND_ECC_ENGINE_TYPE_ON_HOST) in fsl_elbc_run_command()
249 elbc_fcm_ctrl->max_bitflips = 0; in fsl_elbc_run_command()
251 if (elbc_fcm_ctrl->read_bytes == mtd->writesize + mtd->oobsize) { in fsl_elbc_run_command()
252 uint32_t lteccr = in_be32(&lbc->lteccr); in fsl_elbc_run_command()
255 * has the LTECCR register, then bits 12-15 (ppc order) of in fsl_elbc_run_command()
256 * LTECCR indicates which 512 byte sub-pages had fixed errors. in fsl_elbc_run_command()
257 * bits 28-31 are uncorrectable errors, marked elsewhere. in fsl_elbc_run_command()
261 * count the number of sub-pages with bitflips and update in fsl_elbc_run_command()
265 out_be32(&lbc->lteccr, 0x000F000F); /* clear lteccr */ in fsl_elbc_run_command()
267 mtd->ecc_stats.corrected++; in fsl_elbc_run_command()
268 elbc_fcm_ctrl->max_bitflips = 1; in fsl_elbc_run_command()
278 struct fsl_lbc_ctrl *ctrl = priv->ctrl; in fsl_elbc_do_read()
279 struct fsl_lbc_regs __iomem *lbc = ctrl->regs; in fsl_elbc_do_read()
281 if (priv->page_size) { in fsl_elbc_do_read()
282 out_be32(&lbc->fir, in fsl_elbc_do_read()
289 out_be32(&lbc->fcr, (NAND_CMD_READ0 << FCR_CMD0_SHIFT) | in fsl_elbc_do_read()
292 out_be32(&lbc->fir, in fsl_elbc_do_read()
299 out_be32(&lbc->fcr, NAND_CMD_READOOB << FCR_CMD0_SHIFT); in fsl_elbc_do_read()
301 out_be32(&lbc->fcr, NAND_CMD_READ0 << FCR_CMD0_SHIFT); in fsl_elbc_do_read()
311 struct fsl_lbc_ctrl *ctrl = priv->ctrl; in fsl_elbc_cmdfunc()
312 struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = ctrl->nand; in fsl_elbc_cmdfunc()
313 struct fsl_lbc_regs __iomem *lbc = ctrl->regs; in fsl_elbc_cmdfunc()
315 elbc_fcm_ctrl->use_mdr = 0; in fsl_elbc_cmdfunc()
318 elbc_fcm_ctrl->read_bytes = 0; in fsl_elbc_cmdfunc()
320 elbc_fcm_ctrl->index = 0; in fsl_elbc_cmdfunc()
328 dev_dbg(priv->dev, in fsl_elbc_cmdfunc()
333 out_be32(&lbc->fbcr, 0); /* read entire page to enable ECC */ in fsl_elbc_cmdfunc()
336 elbc_fcm_ctrl->read_bytes = mtd->writesize + mtd->oobsize; in fsl_elbc_cmdfunc()
337 elbc_fcm_ctrl->index += column; in fsl_elbc_cmdfunc()
345 dev_dbg(priv->dev, in fsl_elbc_cmdfunc()
349 elbc_fcm_ctrl->index = column; in fsl_elbc_cmdfunc()
354 dev_vdbg(priv->dev, in fsl_elbc_cmdfunc()
358 out_be32(&lbc->fbcr, mtd->oobsize - column); in fsl_elbc_cmdfunc()
361 elbc_fcm_ctrl->read_bytes = mtd->writesize + mtd->oobsize; in fsl_elbc_cmdfunc()
369 dev_vdbg(priv->dev, "fsl_elbc_cmdfunc: NAND_CMD %x\n", command); in fsl_elbc_cmdfunc()
371 out_be32(&lbc->fir, (FIR_OP_CM0 << FIR_OP0_SHIFT) | in fsl_elbc_cmdfunc()
374 out_be32(&lbc->fcr, command << FCR_CMD0_SHIFT); in fsl_elbc_cmdfunc()
379 out_be32(&lbc->fbcr, 256); in fsl_elbc_cmdfunc()
380 elbc_fcm_ctrl->read_bytes = 256; in fsl_elbc_cmdfunc()
381 elbc_fcm_ctrl->use_mdr = 1; in fsl_elbc_cmdfunc()
382 elbc_fcm_ctrl->mdr = column; in fsl_elbc_cmdfunc()
389 dev_vdbg(priv->dev, in fsl_elbc_cmdfunc()
397 dev_vdbg(priv->dev, "fsl_elbc_cmdfunc: NAND_CMD_ERASE2.\n"); in fsl_elbc_cmdfunc()
399 out_be32(&lbc->fir, in fsl_elbc_cmdfunc()
406 out_be32(&lbc->fcr, in fsl_elbc_cmdfunc()
411 out_be32(&lbc->fbcr, 0); in fsl_elbc_cmdfunc()
412 elbc_fcm_ctrl->read_bytes = 0; in fsl_elbc_cmdfunc()
413 elbc_fcm_ctrl->use_mdr = 1; in fsl_elbc_cmdfunc()
421 dev_vdbg(priv->dev, in fsl_elbc_cmdfunc()
426 elbc_fcm_ctrl->column = column; in fsl_elbc_cmdfunc()
427 elbc_fcm_ctrl->use_mdr = 1; in fsl_elbc_cmdfunc()
429 if (column >= mtd->writesize) { in fsl_elbc_cmdfunc()
431 column -= mtd->writesize; in fsl_elbc_cmdfunc()
432 elbc_fcm_ctrl->oob = 1; in fsl_elbc_cmdfunc()
435 elbc_fcm_ctrl->oob = 0; in fsl_elbc_cmdfunc()
442 if (priv->page_size) { in fsl_elbc_cmdfunc()
443 out_be32(&lbc->fir, in fsl_elbc_cmdfunc()
452 out_be32(&lbc->fir, in fsl_elbc_cmdfunc()
462 if (elbc_fcm_ctrl->oob) in fsl_elbc_cmdfunc()
463 /* OOB area --> READOOB */ in fsl_elbc_cmdfunc()
466 /* First 256 bytes --> READ0 */ in fsl_elbc_cmdfunc()
470 out_be32(&lbc->fcr, fcr); in fsl_elbc_cmdfunc()
471 set_addr(mtd, column, page_addr, elbc_fcm_ctrl->oob); in fsl_elbc_cmdfunc()
477 dev_vdbg(priv->dev, in fsl_elbc_cmdfunc()
479 "writing %d bytes.\n", elbc_fcm_ctrl->index); in fsl_elbc_cmdfunc()
485 if (elbc_fcm_ctrl->oob || elbc_fcm_ctrl->column != 0 || in fsl_elbc_cmdfunc()
486 elbc_fcm_ctrl->index != mtd->writesize + mtd->oobsize) in fsl_elbc_cmdfunc()
487 out_be32(&lbc->fbcr, in fsl_elbc_cmdfunc()
488 elbc_fcm_ctrl->index - elbc_fcm_ctrl->column); in fsl_elbc_cmdfunc()
490 out_be32(&lbc->fbcr, 0); in fsl_elbc_cmdfunc()
497 /* Note - it does not wait for the ready line */ in fsl_elbc_cmdfunc()
499 out_be32(&lbc->fir, in fsl_elbc_cmdfunc()
502 out_be32(&lbc->fcr, NAND_CMD_STATUS << FCR_CMD0_SHIFT); in fsl_elbc_cmdfunc()
503 out_be32(&lbc->fbcr, 1); in fsl_elbc_cmdfunc()
505 elbc_fcm_ctrl->read_bytes = 1; in fsl_elbc_cmdfunc()
510 * write-protected, even when it is not. in fsl_elbc_cmdfunc()
512 setbits8(elbc_fcm_ctrl->addr, NAND_STATUS_WP); in fsl_elbc_cmdfunc()
517 dev_dbg(priv->dev, "fsl_elbc_cmdfunc: NAND_CMD_RESET.\n"); in fsl_elbc_cmdfunc()
518 out_be32(&lbc->fir, FIR_OP_CM0 << FIR_OP0_SHIFT); in fsl_elbc_cmdfunc()
519 out_be32(&lbc->fcr, NAND_CMD_RESET << FCR_CMD0_SHIFT); in fsl_elbc_cmdfunc()
524 dev_err(priv->dev, in fsl_elbc_cmdfunc()
533 * chips per bank. in fsl_elbc_select_chip()
544 struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = priv->ctrl->nand; in fsl_elbc_write_buf()
545 unsigned int bufsize = mtd->writesize + mtd->oobsize; in fsl_elbc_write_buf()
548 dev_err(priv->dev, "write_buf of %d bytes", len); in fsl_elbc_write_buf()
549 elbc_fcm_ctrl->status = 0; in fsl_elbc_write_buf()
553 if ((unsigned int)len > bufsize - elbc_fcm_ctrl->index) { in fsl_elbc_write_buf()
554 dev_err(priv->dev, in fsl_elbc_write_buf()
557 len, bufsize - elbc_fcm_ctrl->index); in fsl_elbc_write_buf()
558 len = bufsize - elbc_fcm_ctrl->index; in fsl_elbc_write_buf()
561 memcpy_toio(&elbc_fcm_ctrl->addr[elbc_fcm_ctrl->index], buf, len); in fsl_elbc_write_buf()
569 in_8(&elbc_fcm_ctrl->addr[elbc_fcm_ctrl->index] + len - 1); in fsl_elbc_write_buf()
571 elbc_fcm_ctrl->index += len; in fsl_elbc_write_buf()
581 struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = priv->ctrl->nand; in fsl_elbc_read_byte()
584 if (elbc_fcm_ctrl->index < elbc_fcm_ctrl->read_bytes) in fsl_elbc_read_byte()
585 return in_8(&elbc_fcm_ctrl->addr[elbc_fcm_ctrl->index++]); in fsl_elbc_read_byte()
587 dev_err(priv->dev, "read_byte beyond end of buffer\n"); in fsl_elbc_read_byte()
597 struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = priv->ctrl->nand; in fsl_elbc_read_buf()
604 elbc_fcm_ctrl->read_bytes - elbc_fcm_ctrl->index); in fsl_elbc_read_buf()
605 memcpy_fromio(buf, &elbc_fcm_ctrl->addr[elbc_fcm_ctrl->index], avail); in fsl_elbc_read_buf()
606 elbc_fcm_ctrl->index += avail; in fsl_elbc_read_buf()
609 dev_err(priv->dev, in fsl_elbc_read_buf()
621 struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = priv->ctrl->nand; in fsl_elbc_wait()
623 if (elbc_fcm_ctrl->status != LTESR_CC) in fsl_elbc_wait()
627 * write-protected, even when it is not. in fsl_elbc_wait()
629 return (elbc_fcm_ctrl->mdr & 0xff) | NAND_STATUS_WP; in fsl_elbc_wait()
637 struct fsl_lbc_ctrl *ctrl = priv->ctrl; in fsl_elbc_read_page()
638 struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = ctrl->nand; in fsl_elbc_read_page()
640 nand_read_page_op(chip, page, 0, buf, mtd->writesize); in fsl_elbc_read_page()
642 fsl_elbc_read_buf(chip, chip->oob_poi, mtd->oobsize); in fsl_elbc_read_page()
645 mtd->ecc_stats.failed++; in fsl_elbc_read_page()
647 return elbc_fcm_ctrl->max_bitflips; in fsl_elbc_read_page()
658 nand_prog_page_begin_op(chip, page, 0, buf, mtd->writesize); in fsl_elbc_write_page()
659 fsl_elbc_write_buf(chip, chip->oob_poi, mtd->oobsize); in fsl_elbc_write_page()
674 fsl_elbc_write_buf(chip, buf, mtd->writesize); in fsl_elbc_write_subpage()
675 fsl_elbc_write_buf(chip, chip->oob_poi, mtd->oobsize); in fsl_elbc_write_subpage()
681 struct fsl_lbc_ctrl *ctrl = priv->ctrl; in fsl_elbc_chip_init()
682 struct fsl_lbc_regs __iomem *lbc = ctrl->regs; in fsl_elbc_chip_init()
683 struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = ctrl->nand; in fsl_elbc_chip_init()
684 struct nand_chip *chip = &priv->chip; in fsl_elbc_chip_init()
687 dev_dbg(priv->dev, "eLBC Set Information for bank %d\n", priv->bank); in fsl_elbc_chip_init()
690 mtd->dev.parent = priv->dev; in fsl_elbc_chip_init()
691 nand_set_flash_node(chip, priv->dev->of_node); in fsl_elbc_chip_init()
694 priv->fmr = 15 << FMR_CWTO_SHIFT; in fsl_elbc_chip_init()
695 if (in_be32(&lbc->bank[priv->bank].or) & OR_FCM_PGS) in fsl_elbc_chip_init()
696 priv->fmr |= FMR_ECCM; in fsl_elbc_chip_init()
700 chip->legacy.read_byte = fsl_elbc_read_byte; in fsl_elbc_chip_init()
701 chip->legacy.write_buf = fsl_elbc_write_buf; in fsl_elbc_chip_init()
702 chip->legacy.read_buf = fsl_elbc_read_buf; in fsl_elbc_chip_init()
703 chip->legacy.select_chip = fsl_elbc_select_chip; in fsl_elbc_chip_init()
704 chip->legacy.cmdfunc = fsl_elbc_cmdfunc; in fsl_elbc_chip_init()
705 chip->legacy.waitfunc = fsl_elbc_wait; in fsl_elbc_chip_init()
706 chip->legacy.set_features = nand_get_set_features_notsupp; in fsl_elbc_chip_init()
707 chip->legacy.get_features = nand_get_set_features_notsupp; in fsl_elbc_chip_init()
709 chip->bbt_td = &bbt_main_descr; in fsl_elbc_chip_init()
710 chip->bbt_md = &bbt_mirror_descr; in fsl_elbc_chip_init()
713 chip->bbt_options = NAND_BBT_USE_FLASH; in fsl_elbc_chip_init()
715 chip->controller = &elbc_fcm_ctrl->controller; in fsl_elbc_chip_init()
725 struct fsl_lbc_ctrl *ctrl = priv->ctrl; in fsl_elbc_attach_chip()
726 struct fsl_lbc_regs __iomem *lbc = ctrl->regs; in fsl_elbc_attach_chip()
734 if (chip->ecc.engine_type == NAND_ECC_ENGINE_TYPE_INVALID) { in fsl_elbc_attach_chip()
736 if ((in_be32(&lbc->bank[priv->bank].br) & BR_DECC) == in fsl_elbc_attach_chip()
738 chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST; in fsl_elbc_attach_chip()
741 chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_SOFT; in fsl_elbc_attach_chip()
742 chip->ecc.algo = NAND_ECC_ALGO_HAMMING; in fsl_elbc_attach_chip()
746 switch (chip->ecc.engine_type) { in fsl_elbc_attach_chip()
749 chip->ecc.read_page = fsl_elbc_read_page; in fsl_elbc_attach_chip()
750 chip->ecc.write_page = fsl_elbc_write_page; in fsl_elbc_attach_chip()
751 chip->ecc.write_subpage = fsl_elbc_write_subpage; in fsl_elbc_attach_chip()
753 chip->ecc.size = 512; in fsl_elbc_attach_chip()
754 chip->ecc.bytes = 3; in fsl_elbc_attach_chip()
755 chip->ecc.strength = 1; in fsl_elbc_attach_chip()
765 return -EINVAL; in fsl_elbc_attach_chip()
769 br = in_be32(&lbc->bank[priv->bank].br) & ~BR_DECC; in fsl_elbc_attach_chip()
770 if (chip->ecc.engine_type == NAND_ECC_ENGINE_TYPE_ON_HOST) in fsl_elbc_attach_chip()
771 out_be32(&lbc->bank[priv->bank].br, br | BR_DECC_CHK_GEN); in fsl_elbc_attach_chip()
773 out_be32(&lbc->bank[priv->bank].br, br | BR_DECC_OFF); in fsl_elbc_attach_chip()
777 if (chip->pagemask & 0xffff0000) in fsl_elbc_attach_chip()
779 if (chip->pagemask & 0xff000000) in fsl_elbc_attach_chip()
782 priv->fmr |= al << FMR_AL_SHIFT; in fsl_elbc_attach_chip()
784 dev_dbg(priv->dev, "fsl_elbc_init: nand->numchips = %d\n", in fsl_elbc_attach_chip()
785 nanddev_ntargets(&chip->base)); in fsl_elbc_attach_chip()
786 dev_dbg(priv->dev, "fsl_elbc_init: nand->chipsize = %lld\n", in fsl_elbc_attach_chip()
787 nanddev_target_size(&chip->base)); in fsl_elbc_attach_chip()
788 dev_dbg(priv->dev, "fsl_elbc_init: nand->pagemask = %8x\n", in fsl_elbc_attach_chip()
789 chip->pagemask); in fsl_elbc_attach_chip()
790 dev_dbg(priv->dev, "fsl_elbc_init: nand->legacy.chip_delay = %d\n", in fsl_elbc_attach_chip()
791 chip->legacy.chip_delay); in fsl_elbc_attach_chip()
792 dev_dbg(priv->dev, "fsl_elbc_init: nand->badblockpos = %d\n", in fsl_elbc_attach_chip()
793 chip->badblockpos); in fsl_elbc_attach_chip()
794 dev_dbg(priv->dev, "fsl_elbc_init: nand->chip_shift = %d\n", in fsl_elbc_attach_chip()
795 chip->chip_shift); in fsl_elbc_attach_chip()
796 dev_dbg(priv->dev, "fsl_elbc_init: nand->page_shift = %d\n", in fsl_elbc_attach_chip()
797 chip->page_shift); in fsl_elbc_attach_chip()
798 dev_dbg(priv->dev, "fsl_elbc_init: nand->phys_erase_shift = %d\n", in fsl_elbc_attach_chip()
799 chip->phys_erase_shift); in fsl_elbc_attach_chip()
800 dev_dbg(priv->dev, "fsl_elbc_init: nand->ecc.engine_type = %d\n", in fsl_elbc_attach_chip()
801 chip->ecc.engine_type); in fsl_elbc_attach_chip()
802 dev_dbg(priv->dev, "fsl_elbc_init: nand->ecc.steps = %d\n", in fsl_elbc_attach_chip()
803 chip->ecc.steps); in fsl_elbc_attach_chip()
804 dev_dbg(priv->dev, "fsl_elbc_init: nand->ecc.bytes = %d\n", in fsl_elbc_attach_chip()
805 chip->ecc.bytes); in fsl_elbc_attach_chip()
806 dev_dbg(priv->dev, "fsl_elbc_init: nand->ecc.total = %d\n", in fsl_elbc_attach_chip()
807 chip->ecc.total); in fsl_elbc_attach_chip()
808 dev_dbg(priv->dev, "fsl_elbc_init: mtd->ooblayout = %p\n", in fsl_elbc_attach_chip()
809 mtd->ooblayout); in fsl_elbc_attach_chip()
810 dev_dbg(priv->dev, "fsl_elbc_init: mtd->flags = %08x\n", mtd->flags); in fsl_elbc_attach_chip()
811 dev_dbg(priv->dev, "fsl_elbc_init: mtd->size = %lld\n", mtd->size); in fsl_elbc_attach_chip()
812 dev_dbg(priv->dev, "fsl_elbc_init: mtd->erasesize = %d\n", in fsl_elbc_attach_chip()
813 mtd->erasesize); in fsl_elbc_attach_chip()
814 dev_dbg(priv->dev, "fsl_elbc_init: mtd->writesize = %d\n", in fsl_elbc_attach_chip()
815 mtd->writesize); in fsl_elbc_attach_chip()
816 dev_dbg(priv->dev, "fsl_elbc_init: mtd->oobsize = %d\n", in fsl_elbc_attach_chip()
817 mtd->oobsize); in fsl_elbc_attach_chip()
820 if (mtd->writesize == 512) { in fsl_elbc_attach_chip()
821 priv->page_size = 0; in fsl_elbc_attach_chip()
822 clrbits32(&lbc->bank[priv->bank].or, OR_FCM_PGS); in fsl_elbc_attach_chip()
823 } else if (mtd->writesize == 2048) { in fsl_elbc_attach_chip()
824 priv->page_size = 1; in fsl_elbc_attach_chip()
825 setbits32(&lbc->bank[priv->bank].or, OR_FCM_PGS); in fsl_elbc_attach_chip()
827 dev_err(priv->dev, in fsl_elbc_attach_chip()
829 mtd->writesize); in fsl_elbc_attach_chip()
830 return -ENOTSUPP; in fsl_elbc_attach_chip()
842 struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = priv->ctrl->nand; in fsl_elbc_chip_remove()
843 struct mtd_info *mtd = nand_to_mtd(&priv->chip); in fsl_elbc_chip_remove()
845 kfree(mtd->name); in fsl_elbc_chip_remove()
847 if (priv->vbase) in fsl_elbc_chip_remove()
848 iounmap(priv->vbase); in fsl_elbc_chip_remove()
850 elbc_fcm_ctrl->chips[priv->bank] = NULL; in fsl_elbc_chip_remove()
866 int bank; in fsl_elbc_nand_probe() local
868 struct device_node *node = pdev->dev.of_node; in fsl_elbc_nand_probe()
871 if (!fsl_lbc_ctrl_dev || !fsl_lbc_ctrl_dev->regs) in fsl_elbc_nand_probe()
872 return dev_err_probe(&pdev->dev, -EPROBE_DEFER, "lbc_ctrl_dev missing\n"); in fsl_elbc_nand_probe()
874 lbc = fsl_lbc_ctrl_dev->regs; in fsl_elbc_nand_probe()
875 dev = fsl_lbc_ctrl_dev->dev; in fsl_elbc_nand_probe()
885 for (bank = 0; bank < MAX_BANKS; bank++) in fsl_elbc_nand_probe()
886 if ((in_be32(&lbc->bank[bank].br) & BR_V) && in fsl_elbc_nand_probe()
887 (in_be32(&lbc->bank[bank].br) & BR_MSEL) == BR_MS_FCM && in fsl_elbc_nand_probe()
888 (in_be32(&lbc->bank[bank].br) & in fsl_elbc_nand_probe()
889 in_be32(&lbc->bank[bank].or) & BR_BA) in fsl_elbc_nand_probe()
893 if (bank >= MAX_BANKS) { in fsl_elbc_nand_probe()
895 return -ENODEV; in fsl_elbc_nand_probe()
900 return -ENOMEM; in fsl_elbc_nand_probe()
903 if (!fsl_lbc_ctrl_dev->nand) { in fsl_elbc_nand_probe()
907 ret = -ENOMEM; in fsl_elbc_nand_probe()
910 elbc_fcm_ctrl->counter++; in fsl_elbc_nand_probe()
912 nand_controller_init(&elbc_fcm_ctrl->controller); in fsl_elbc_nand_probe()
913 fsl_lbc_ctrl_dev->nand = elbc_fcm_ctrl; in fsl_elbc_nand_probe()
915 elbc_fcm_ctrl = fsl_lbc_ctrl_dev->nand; in fsl_elbc_nand_probe()
919 elbc_fcm_ctrl->chips[bank] = priv; in fsl_elbc_nand_probe()
920 priv->bank = bank; in fsl_elbc_nand_probe()
921 priv->ctrl = fsl_lbc_ctrl_dev; in fsl_elbc_nand_probe()
922 priv->dev = &pdev->dev; in fsl_elbc_nand_probe()
923 dev_set_drvdata(priv->dev, priv); in fsl_elbc_nand_probe()
925 priv->vbase = ioremap(res.start, resource_size(&res)); in fsl_elbc_nand_probe()
926 if (!priv->vbase) { in fsl_elbc_nand_probe()
928 ret = -ENOMEM; in fsl_elbc_nand_probe()
932 mtd = nand_to_mtd(&priv->chip); in fsl_elbc_nand_probe()
933 mtd->name = kasprintf(GFP_KERNEL, "%llx.flash", (u64)res.start); in fsl_elbc_nand_probe()
934 if (!nand_to_mtd(&priv->chip)->name) { in fsl_elbc_nand_probe()
935 ret = -ENOMEM; in fsl_elbc_nand_probe()
943 priv->chip.controller->ops = &fsl_elbc_controller_ops; in fsl_elbc_nand_probe()
944 ret = nand_scan(&priv->chip, 1); in fsl_elbc_nand_probe()
954 pr_info("eLBC NAND device at 0x%llx, bank %d\n", in fsl_elbc_nand_probe()
955 (unsigned long long)res.start, priv->bank); in fsl_elbc_nand_probe()
960 nand_cleanup(&priv->chip); in fsl_elbc_nand_probe()
969 struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = fsl_lbc_ctrl_dev->nand; in fsl_elbc_nand_remove()
970 struct fsl_elbc_mtd *priv = dev_get_drvdata(&pdev->dev); in fsl_elbc_nand_remove()
971 struct nand_chip *chip = &priv->chip; in fsl_elbc_nand_remove()
981 elbc_fcm_ctrl->counter--; in fsl_elbc_nand_remove()
982 if (!elbc_fcm_ctrl->counter) { in fsl_elbc_nand_remove()
983 fsl_lbc_ctrl_dev->nand = NULL; in fsl_elbc_nand_remove()
991 { .compatible = "fsl,elbc-fcm-nand", },
998 .name = "fsl,elbc-fcm-nand",