Lines Matching +full:hs400 +full:- +full:cmd +full:- +full:int +full:- +full:delay
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * linux/drivers/mmc/host/sdhci.h - Secure Digital Host Controller Interface driver
7 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
130 * VDD2 - UHS2 or PCIe/NVMe
208 #define SDHCI_INT_ALL_MASK ((unsigned int)-1)
233 #define SDHCI_CTRL_HS400 0x0005 /* Non-standard */
286 #define SDHCI_CAN_VDD2_180 0x10000000 /* UHS-2 1.8V VDD2 */
287 #define SDHCI_SUPPORT_HS400 0x80000000 /* Non-standard */
298 /* 4C-4F reserved for more max current */
306 /* 55-57 reserved */
311 /* 60-FB reserved */
319 #define SDHCI_PRESET_FOR_HS400 0x74 /* Non-standard */
354 #define SDHCI_DEFAULT_BOUNDARY_ARG (ilog2(SDHCI_DEFAULT_BOUNDARY_SIZE) - 12)
356 /* ADMA2 32-bit DMA descriptor size */
359 /* ADMA2 32-bit descriptor */
361 __le16 cmd; member
368 #define SDHCI_ADMA2_MASK (SDHCI_ADMA2_ALIGN - 1)
372 * alignment for the descriptor table even in 32-bit DMA mode. Memory
378 * ADMA2 64-bit DMA descriptor size
380 * descriptors for 64-bit addressing mode: 96-bit Descriptor and 128-bit
382 * register, 128-bit Descriptor will be selected.
384 #define SDHCI_ADMA2_64_DESC_SZ(host) ((host)->v4_mode ? 16 : 12)
387 * ADMA2 64-bit descriptor. Note 12-byte descriptor can't always be 8-byte
391 __le16 cmd; member
420 mmc_debugfs_err_stats_inc((host)->mmc, MMC_ERR_##err_name)
432 unsigned int quirks; /* Deviations from spec. */
446 /* Controller can only DMA from 32-bit aligned addresses */
460 /* Controller does not provide transfer-complete interrupt when not busy */
464 /* Controller reports inverted write-protect state */
474 /* Controller cannot do multi-block transfers */
476 /* Controller can only handle 1-bit data transfers */
478 /* Controller needs 10ms delay between applying power and clock */
488 /* Controller doesn't have HISPD bit field in HI-SPEED SD card */
493 unsigned int quirks2; /* More deviations from spec. */
501 /* Controller has a non-standard host control register */
509 /* Controller does not support 64-bit DMA */
511 /* need clear transfer mode register before send cmd */
513 /* Capability register bit-63 indicates HS400 support */
531 * 32-bit block count may not support eMMC where upper bits of CMD23 are used
532 * for other purposes. Consequently we support 16-bit block count by default.
533 * Otherwise, SDHCI_QUIRK2_USE_32BIT_BLK_CNT can be selected to use 32-bit
537 /* Issue CMD and DATA reset together */
540 int irq; /* Device IRQ */
545 unsigned int bounce_buffer_size;
561 int flags; /* Host attributes */
570 #define SDHCI_USE_64_BIT_DMA (1<<12) /* Use 64-bit DMA */
571 #define SDHCI_HS400_TUNING (1<<13) /* Tuning for HS400 */
576 unsigned int version; /* SDHCI spec. version */
578 unsigned int max_clk; /* Max possible freq (MHz) */
579 unsigned int timeout_clk; /* Timeout freq (KHz) */
581 unsigned int clk_mul; /* Clock Muliplier value */
583 unsigned int clock; /* Current clock (MHz) */
585 u8 drv_type; /* Current UHS-I driver type */
586 bool reinit_uhs; /* Force UHS-related re-initialization */
591 bool pending_reset; /* Cmd/data reset is pending */
598 struct mmc_command *cmd; /* Current command */ member
602 unsigned int data_early:1; /* Data finished before cmd */
605 unsigned int blocks; /* remaining PIO blocks */
607 int sg_count; /* Mapped sg entries */
608 int max_adma; /* Max. length in ADMA descriptor */
619 unsigned int desc_sz; /* ADMA current descriptor size */
620 unsigned int alloc_desc_sz; /* ADMA descr. max size host supports */
629 irqreturn_t (*thread_irq_fn)(int irq, void *dev_id);
641 unsigned int ocr_avail_sdio; /* OCR bit masks */
642 unsigned int ocr_avail_sd;
643 unsigned int ocr_avail_mmc;
658 unsigned int tuning_done; /* Condition flag set when CMD19 succeeds */
660 unsigned int tuning_count; /* Timer count for re-tuning */
661 unsigned int tuning_mode; /* Re-tuning mode supported by host */
662 unsigned int tuning_err; /* Error code for re-tuning */
666 /* Delay (ms) between tuning commands */
667 int tuning_delay;
668 int tuning_loop_count;
683 u32 (*read_l)(struct sdhci_host *host, int reg);
684 u16 (*read_w)(struct sdhci_host *host, int reg);
685 u8 (*read_b)(struct sdhci_host *host, int reg);
686 void (*write_l)(struct sdhci_host *host, u32 val, int reg);
687 void (*write_w)(struct sdhci_host *host, u16 val, int reg);
688 void (*write_b)(struct sdhci_host *host, u8 val, int reg);
691 void (*set_clock)(struct sdhci_host *host, unsigned int clock);
697 int (*set_dma_mask)(struct sdhci_host *host);
698 int (*enable_dma)(struct sdhci_host *host);
699 unsigned int (*get_max_clock)(struct sdhci_host *host);
700 unsigned int (*get_min_clock)(struct sdhci_host *host);
702 unsigned int (*get_timeout_clock)(struct sdhci_host *host);
703 unsigned int (*get_max_timeout_count)(struct sdhci_host *host);
705 struct mmc_command *cmd);
706 void (*set_bus_width)(struct sdhci_host *host, int width);
709 unsigned int (*get_ro)(struct sdhci_host *host);
711 int (*platform_execute_tuning)(struct sdhci_host *host, u32 opcode);
712 void (*set_uhs_signaling)(struct sdhci_host *host, unsigned int uhs);
718 dma_addr_t addr, int len, unsigned int cmd);
721 unsigned int length);
731 static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg) in sdhci_writel()
733 if (unlikely(host->ops->write_l)) in sdhci_writel()
734 host->ops->write_l(host, val, reg); in sdhci_writel()
736 writel(val, host->ioaddr + reg); in sdhci_writel()
739 static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg) in sdhci_writew()
741 if (unlikely(host->ops->write_w)) in sdhci_writew()
742 host->ops->write_w(host, val, reg); in sdhci_writew()
744 writew(val, host->ioaddr + reg); in sdhci_writew()
747 static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg) in sdhci_writeb()
749 if (unlikely(host->ops->write_b)) in sdhci_writeb()
750 host->ops->write_b(host, val, reg); in sdhci_writeb()
752 writeb(val, host->ioaddr + reg); in sdhci_writeb()
755 static inline u32 sdhci_readl(struct sdhci_host *host, int reg) in sdhci_readl()
757 if (unlikely(host->ops->read_l)) in sdhci_readl()
758 return host->ops->read_l(host, reg); in sdhci_readl()
760 return readl(host->ioaddr + reg); in sdhci_readl()
763 static inline u16 sdhci_readw(struct sdhci_host *host, int reg) in sdhci_readw()
765 if (unlikely(host->ops->read_w)) in sdhci_readw()
766 return host->ops->read_w(host, reg); in sdhci_readw()
768 return readw(host->ioaddr + reg); in sdhci_readw()
771 static inline u8 sdhci_readb(struct sdhci_host *host, int reg) in sdhci_readb()
773 if (unlikely(host->ops->read_b)) in sdhci_readb()
774 return host->ops->read_b(host, reg); in sdhci_readb()
776 return readb(host->ioaddr + reg); in sdhci_readb()
781 static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg) in sdhci_writel()
783 writel(val, host->ioaddr + reg); in sdhci_writel()
786 static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg) in sdhci_writew()
788 writew(val, host->ioaddr + reg); in sdhci_writew()
791 static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg) in sdhci_writeb()
793 writeb(val, host->ioaddr + reg); in sdhci_writeb()
796 static inline u32 sdhci_readl(struct sdhci_host *host, int reg) in sdhci_readl()
798 return readl(host->ioaddr + reg); in sdhci_readl()
801 static inline u16 sdhci_readw(struct sdhci_host *host, int reg) in sdhci_readw()
803 return readw(host->ioaddr + reg); in sdhci_readw()
806 static inline u8 sdhci_readb(struct sdhci_host *host, int reg) in sdhci_readb()
808 return readb(host->ioaddr + reg); in sdhci_readb()
818 return host->private; in sdhci_priv()
823 int sdhci_setup_host(struct sdhci_host *host);
825 int __sdhci_add_host(struct sdhci_host *host);
826 int sdhci_add_host(struct sdhci_host *host);
827 void sdhci_remove_host(struct sdhci_host *host, int dead);
835 bool sdhci_data_line_cmd(struct mmc_command *cmd);
842 bool sdhci_present_error(struct sdhci_host *host, struct mmc_command *cmd, bool present);
843 u16 sdhci_calc_clk(struct sdhci_host *host, unsigned int clock,
844 unsigned int *actual_clock);
845 void sdhci_set_clock(struct sdhci_host *host, unsigned int clock);
855 int sdhci_get_cd_nogpio(struct mmc_host *mmc);
856 int sdhci_get_ro(struct mmc_host *mmc);
858 int sdhci_request_atomic(struct mmc_host *mmc, struct mmc_request *mrq);
859 void sdhci_set_bus_width(struct sdhci_host *host, int width);
863 int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode);
864 int __sdhci_execute_tuning(struct sdhci_host *host, u32 opcode);
868 int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
870 void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable);
873 irqreturn_t sdhci_thread_irq(int irq, void *dev_id);
875 dma_addr_t addr, int len, unsigned int cmd);
878 int sdhci_suspend_host(struct sdhci_host *host);
879 int sdhci_resume_host(struct sdhci_host *host);
880 int sdhci_runtime_suspend_host(struct sdhci_host *host);
881 int sdhci_runtime_resume_host(struct sdhci_host *host, int soft_reset);
886 bool sdhci_cqe_irq(struct sdhci_host *host, u32 intmask, int *cmd_error,
887 int *data_error);
899 void __sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd);