Lines Matching +full:host +full:- +full:command
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * linux/drivers/mmc/host/sdhci.h - Secure Digital Host Controller Interface driver
5 * Header file for Host Controller registers and I/O accessors.
7 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
20 #include <linux/mmc/host.h>
47 * Defined in Host Version 4.0.
57 * Host Version 4.10 adds this bit to distinguish a main command or
58 * sub command.
59 * For example with SDIO, CMD52 (sub command) issued during CMD53 (main command).
101 /* Host Version 4.10 */
130 * VDD2 - UHS2 or PCIe/NVMe
177 /* Host Version 4.10 */
194 /* Host Version 4.0 */
208 #define SDHCI_INT_ALL_MASK ((unsigned int)-1)
223 /* Host Version 4.10 */
233 #define SDHCI_CTRL_HS400 0x0005 /* Non-standard */
286 #define SDHCI_CAN_VDD2_180 0x10000000 /* UHS-2 1.8V VDD2 */
287 #define SDHCI_SUPPORT_HS400 0x80000000 /* Non-standard */
298 /* 4C-4F reserved for more max current */
301 /* Host Version 4.10 */
306 /* 55-57 reserved */
311 /* 60-FB reserved */
319 #define SDHCI_PRESET_FOR_HS400 0x74 /* Non-standard */
351 * Host SDMA buffer boundary. Valid values from 4K to 512K in powers of 2.
354 #define SDHCI_DEFAULT_BOUNDARY_ARG (ilog2(SDHCI_DEFAULT_BOUNDARY_SIZE) - 12)
356 /* ADMA2 32-bit DMA descriptor size */
359 /* ADMA2 32-bit descriptor */
368 #define SDHCI_ADMA2_MASK (SDHCI_ADMA2_ALIGN - 1)
372 * alignment for the descriptor table even in 32-bit DMA mode. Memory
378 * ADMA2 64-bit DMA descriptor size
379 * According to SD Host Controller spec v4.10, there are two kinds of
380 * descriptors for 64-bit addressing mode: 96-bit Descriptor and 128-bit
381 * Descriptor, if Host Version 4 Enable is set in the Host Control 2
382 * register, 128-bit Descriptor will be selected.
384 #define SDHCI_ADMA2_64_DESC_SZ(host) ((host)->v4_mode ? 16 : 12) argument
387 * ADMA2 64-bit descriptor. Note 12-byte descriptor can't always be 8-byte
408 /* Allow for a command request and a data request at the same time */
412 * 48bit command and 136 bit response in 100KHz clock could take upto 2.48ms.
413 * However since the start time of the command, the time between
414 * command and response, and the time between response and start of data is
415 * not known, set the command transfer time to 10ms.
419 #define sdhci_err_stats_inc(host, err_name) \ argument
420 mmc_debugfs_err_stats_inc((host)->mmc, MMC_ERR_##err_name)
446 /* Controller can only DMA from 32-bit aligned addresses */
460 /* Controller does not provide transfer-complete interrupt when not busy */
464 /* Controller reports inverted write-protect state */
466 /* Controller has unusable command queue engine */
474 /* Controller cannot do multi-block transfers */
476 /* Controller can only handle 1-bit data transfers */
486 /* Controller uses Auto CMD12 command to stop the transfer */
488 /* Controller doesn't have HISPD bit field in HI-SPEED SD card */
497 /* The system physically doesn't support 1.8v, even if the host does */
501 /* Controller has a non-standard host control register */
507 /* Stop command (CMD12) can set Transfer Complete when not using MMC_RSP_BUSY */
509 /* Controller does not support 64-bit DMA */
513 /* Capability register bit-63 indicates HS400 support */
523 /* Controller has CRC in 136 bit Command Response */
531 * 32-bit block count may not support eMMC where upper bits of CMD23 are used
532 * for other purposes. Consequently we support 16-bit block count by default.
533 * Otherwise, SDHCI_QUIRK2_USE_32BIT_BLK_CNT can be selected to use 32-bit
551 struct mmc_host_ops mmc_host_ops; /* MMC host ops */
561 int flags; /* Host attributes */
562 #define SDHCI_USE_SDMA (1<<0) /* Host is SDMA capable */
563 #define SDHCI_USE_ADMA (1<<1) /* Host is ADMA capable */
570 #define SDHCI_USE_64_BIT_DMA (1<<12) /* Use 64-bit DMA */
572 #define SDHCI_SIGNALING_330 (1<<14) /* Host is capable of 3.3V signaling */
573 #define SDHCI_SIGNALING_180 (1<<15) /* Host is capable of 1.8V signaling */
574 #define SDHCI_SIGNALING_120 (1<<16) /* Host is capable of 1.2V signaling */
585 u8 drv_type; /* Current UHS-I driver type */
586 bool reinit_uhs; /* Force UHS-related re-initialization */
588 bool runtime_suspended; /* Host is runtime suspended */
593 bool v4_mode; /* Host Version 4 Enable */
594 bool use_external_dma; /* Host selects to use external DMA */
598 struct mmc_command *cmd; /* Current command */
599 struct mmc_command *data_cmd; /* Current data command */
600 struct mmc_command *deferred_cmd; /* Deferred command */
620 unsigned int alloc_desc_sz; /* ADMA descr. max size host supports */
660 unsigned int tuning_count; /* Timer count for re-tuning */
661 unsigned int tuning_mode; /* Re-tuning mode supported by host */
662 unsigned int tuning_err; /* Error code for re-tuning */
670 /* Host SDMA buffer boundary. */
673 /* Host ADMA table count */
683 u32 (*read_l)(struct sdhci_host *host, int reg);
684 u16 (*read_w)(struct sdhci_host *host, int reg);
685 u8 (*read_b)(struct sdhci_host *host, int reg);
686 void (*write_l)(struct sdhci_host *host, u32 val, int reg);
687 void (*write_w)(struct sdhci_host *host, u16 val, int reg);
688 void (*write_b)(struct sdhci_host *host, u8 val, int reg);
691 void (*set_clock)(struct sdhci_host *host, unsigned int clock);
692 void (*set_power)(struct sdhci_host *host, unsigned char mode,
695 u32 (*irq)(struct sdhci_host *host, u32 intmask);
697 int (*set_dma_mask)(struct sdhci_host *host);
698 int (*enable_dma)(struct sdhci_host *host);
699 unsigned int (*get_max_clock)(struct sdhci_host *host);
700 unsigned int (*get_min_clock)(struct sdhci_host *host);
702 unsigned int (*get_timeout_clock)(struct sdhci_host *host);
703 unsigned int (*get_max_timeout_count)(struct sdhci_host *host);
704 void (*set_timeout)(struct sdhci_host *host,
706 void (*set_bus_width)(struct sdhci_host *host, int width);
707 void (*platform_send_init_74_clocks)(struct sdhci_host *host,
709 unsigned int (*get_ro)(struct sdhci_host *host);
710 void (*reset)(struct sdhci_host *host, u8 mask);
711 int (*platform_execute_tuning)(struct sdhci_host *host, u32 opcode);
712 void (*set_uhs_signaling)(struct sdhci_host *host, unsigned int uhs);
713 void (*hw_reset)(struct sdhci_host *host);
714 void (*adma_workaround)(struct sdhci_host *host, u32 intmask);
715 void (*card_event)(struct sdhci_host *host);
716 void (*voltage_switch)(struct sdhci_host *host);
717 void (*adma_write_desc)(struct sdhci_host *host, void **desc,
719 void (*copy_to_bounce_buffer)(struct sdhci_host *host,
722 void (*request_done)(struct sdhci_host *host,
724 void (*dump_vendor_regs)(struct sdhci_host *host);
725 void (*dump_uhs2_regs)(struct sdhci_host *host);
726 void (*uhs2_pre_detect_init)(struct sdhci_host *host);
731 static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg) in sdhci_writel() argument
733 if (unlikely(host->ops->write_l)) in sdhci_writel()
734 host->ops->write_l(host, val, reg); in sdhci_writel()
736 writel(val, host->ioaddr + reg); in sdhci_writel()
739 static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg) in sdhci_writew() argument
741 if (unlikely(host->ops->write_w)) in sdhci_writew()
742 host->ops->write_w(host, val, reg); in sdhci_writew()
744 writew(val, host->ioaddr + reg); in sdhci_writew()
747 static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg) in sdhci_writeb() argument
749 if (unlikely(host->ops->write_b)) in sdhci_writeb()
750 host->ops->write_b(host, val, reg); in sdhci_writeb()
752 writeb(val, host->ioaddr + reg); in sdhci_writeb()
755 static inline u32 sdhci_readl(struct sdhci_host *host, int reg) in sdhci_readl() argument
757 if (unlikely(host->ops->read_l)) in sdhci_readl()
758 return host->ops->read_l(host, reg); in sdhci_readl()
760 return readl(host->ioaddr + reg); in sdhci_readl()
763 static inline u16 sdhci_readw(struct sdhci_host *host, int reg) in sdhci_readw() argument
765 if (unlikely(host->ops->read_w)) in sdhci_readw()
766 return host->ops->read_w(host, reg); in sdhci_readw()
768 return readw(host->ioaddr + reg); in sdhci_readw()
771 static inline u8 sdhci_readb(struct sdhci_host *host, int reg) in sdhci_readb() argument
773 if (unlikely(host->ops->read_b)) in sdhci_readb()
774 return host->ops->read_b(host, reg); in sdhci_readb()
776 return readb(host->ioaddr + reg); in sdhci_readb()
781 static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg) in sdhci_writel() argument
783 writel(val, host->ioaddr + reg); in sdhci_writel()
786 static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg) in sdhci_writew() argument
788 writew(val, host->ioaddr + reg); in sdhci_writew()
791 static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg) in sdhci_writeb() argument
793 writeb(val, host->ioaddr + reg); in sdhci_writeb()
796 static inline u32 sdhci_readl(struct sdhci_host *host, int reg) in sdhci_readl() argument
798 return readl(host->ioaddr + reg); in sdhci_readl()
801 static inline u16 sdhci_readw(struct sdhci_host *host, int reg) in sdhci_readw() argument
803 return readw(host->ioaddr + reg); in sdhci_readw()
806 static inline u8 sdhci_readb(struct sdhci_host *host, int reg) in sdhci_readb() argument
808 return readb(host->ioaddr + reg); in sdhci_readb()
814 void sdhci_free_host(struct sdhci_host *host);
816 static inline void *sdhci_priv(struct sdhci_host *host) in sdhci_priv() argument
818 return host->private; in sdhci_priv()
821 void __sdhci_read_caps(struct sdhci_host *host, const u16 *ver,
823 int sdhci_setup_host(struct sdhci_host *host);
824 void sdhci_cleanup_host(struct sdhci_host *host);
825 int __sdhci_add_host(struct sdhci_host *host);
826 int sdhci_add_host(struct sdhci_host *host);
827 void sdhci_remove_host(struct sdhci_host *host, int dead);
829 static inline void sdhci_read_caps(struct sdhci_host *host) in sdhci_read_caps() argument
831 __sdhci_read_caps(host, NULL, NULL, NULL); in sdhci_read_caps()
834 bool sdhci_needs_reset(struct sdhci_host *host, struct mmc_request *mrq);
836 void sdhci_mod_timer(struct sdhci_host *host, struct mmc_request *mrq, unsigned long timeout);
837 void sdhci_initialize_data(struct sdhci_host *host, struct mmc_data *data);
838 void sdhci_prepare_dma(struct sdhci_host *host, struct mmc_data *data);
839 void __sdhci_finish_mrq(struct sdhci_host *host, struct mmc_request *mrq);
840 void sdhci_finish_mrq(struct sdhci_host *host, struct mmc_request *mrq);
841 void __sdhci_finish_data_common(struct sdhci_host *host, bool defer_reset);
842 bool sdhci_present_error(struct sdhci_host *host, struct mmc_command *cmd, bool present);
843 u16 sdhci_calc_clk(struct sdhci_host *host, unsigned int clock,
845 void sdhci_set_clock(struct sdhci_host *host, unsigned int clock);
846 void sdhci_enable_clk(struct sdhci_host *host, u16 clk);
847 void sdhci_set_power(struct sdhci_host *host, unsigned char mode,
849 void sdhci_set_power_and_bus_voltage(struct sdhci_host *host,
853 void sdhci_set_power_noreg(struct sdhci_host *host, unsigned char mode,
859 void sdhci_set_bus_width(struct sdhci_host *host, int width);
860 void sdhci_reset(struct sdhci_host *host, u8 mask);
861 bool sdhci_do_reset(struct sdhci_host *host, u8 mask);
862 void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing);
864 int __sdhci_execute_tuning(struct sdhci_host *host, u32 opcode);
865 void sdhci_enable_preset_value(struct sdhci_host *host, bool enable);
871 void sdhci_request_done_dma(struct sdhci_host *host, struct mmc_request *mrq);
874 void sdhci_adma_write_desc(struct sdhci_host *host, void **desc,
878 int sdhci_suspend_host(struct sdhci_host *host);
879 int sdhci_resume_host(struct sdhci_host *host);
880 int sdhci_runtime_suspend_host(struct sdhci_host *host);
881 int sdhci_runtime_resume_host(struct sdhci_host *host, int soft_reset);
886 bool sdhci_cqe_irq(struct sdhci_host *host, u32 intmask, int *cmd_error,
889 void sdhci_dumpregs(struct sdhci_host *host);
890 void sdhci_enable_v4_mode(struct sdhci_host *host);
892 void sdhci_start_tuning(struct sdhci_host *host);
893 void sdhci_end_tuning(struct sdhci_host *host);
894 void sdhci_reset_tuning(struct sdhci_host *host);
895 void sdhci_send_tuning(struct sdhci_host *host, u32 opcode);
896 void sdhci_abort_tuning(struct sdhci_host *host, u32 opcode);
897 void sdhci_switch_external_dma(struct sdhci_host *host, bool en);
898 void sdhci_set_data_timeout_irq(struct sdhci_host *host, bool enable);
899 void __sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd);