Lines Matching +full:dma +full:- +full:byte +full:- +full:en
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * linux/drivers/mmc/host/sdhci.h - Secure Digital Host Controller Interface driver
7 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
31 #define SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF)) argument
130 * VDD2 - UHS2 or PCIe/NVMe
208 #define SDHCI_INT_ALL_MASK ((unsigned int)-1)
233 #define SDHCI_CTRL_HS400 0x0005 /* Non-standard */
286 #define SDHCI_CAN_VDD2_180 0x10000000 /* UHS-2 1.8V VDD2 */
287 #define SDHCI_SUPPORT_HS400 0x80000000 /* Non-standard */
298 /* 4C-4F reserved for more max current */
306 /* 55-57 reserved */
311 /* 60-FB reserved */
319 #define SDHCI_PRESET_FOR_HS400 0x74 /* Non-standard */
354 #define SDHCI_DEFAULT_BOUNDARY_ARG (ilog2(SDHCI_DEFAULT_BOUNDARY_SIZE) - 12)
356 /* ADMA2 32-bit DMA descriptor size */
359 /* ADMA2 32-bit descriptor */
368 #define SDHCI_ADMA2_MASK (SDHCI_ADMA2_ALIGN - 1)
371 * ADMA2 descriptor alignment. Some controllers (e.g. Intel) require 8 byte
372 * alignment for the descriptor table even in 32-bit DMA mode. Memory
373 * allocation is at least 8 byte aligned anyway, so just stipulate 8 always.
378 * ADMA2 64-bit DMA descriptor size
380 * descriptors for 64-bit addressing mode: 96-bit Descriptor and 128-bit
382 * register, 128-bit Descriptor will be selected.
384 #define SDHCI_ADMA2_64_DESC_SZ(host) ((host)->v4_mode ? 16 : 12)
387 * ADMA2 64-bit descriptor. Note 12-byte descriptor can't always be 8-byte
420 mmc_debugfs_err_stats_inc((host)->mmc, MMC_ERR_##err_name)
436 /* Controller has bad caps bits, but really supports DMA */
442 /* Controller has an unusable DMA engine */
446 /* Controller can only DMA from 32-bit aligned addresses */
448 /* Controller can only DMA chunk sizes that are a multiple of 32 bits */
460 /* Controller does not provide transfer-complete interrupt when not busy */
464 /* Controller reports inverted write-protect state */
474 /* Controller cannot do multi-block transfers */
476 /* Controller can only handle 1-bit data transfers */
488 /* Controller doesn't have HISPD bit field in HI-SPEED SD card */
501 /* Controller has a non-standard host control register */
509 /* Controller does not support 64-bit DMA */
513 /* Capability register bit-63 indicates HS400 support */
531 * 32-bit block count may not support eMMC where upper bits of CMD23 are used
532 * for other purposes. Consequently we support 16-bit block count by default.
533 * Otherwise, SDHCI_QUIRK2_USE_32BIT_BLK_CNT can be selected to use 32-bit
552 u64 dma_mask; /* custom DMA mask */
564 #define SDHCI_REQ_USE_DMA (1<<2) /* Use DMA for this req. */
570 #define SDHCI_USE_64_BIT_DMA (1<<12) /* Use 64-bit DMA */
585 u8 drv_type; /* Current UHS-I driver type */
586 bool reinit_uhs; /* Force UHS-related re-initialization */
594 bool use_external_dma; /* Host selects to use external DMA */
660 unsigned int tuning_count; /* Timer count for re-tuning */
661 unsigned int tuning_mode; /* Re-tuning mode supported by host */
662 unsigned int tuning_err; /* Error code for re-tuning */
733 if (unlikely(host->ops->write_l)) in sdhci_writel()
734 host->ops->write_l(host, val, reg); in sdhci_writel()
736 writel(val, host->ioaddr + reg); in sdhci_writel()
741 if (unlikely(host->ops->write_w)) in sdhci_writew()
742 host->ops->write_w(host, val, reg); in sdhci_writew()
744 writew(val, host->ioaddr + reg); in sdhci_writew()
749 if (unlikely(host->ops->write_b)) in sdhci_writeb()
750 host->ops->write_b(host, val, reg); in sdhci_writeb()
752 writeb(val, host->ioaddr + reg); in sdhci_writeb()
757 if (unlikely(host->ops->read_l)) in sdhci_readl()
758 return host->ops->read_l(host, reg); in sdhci_readl()
760 return readl(host->ioaddr + reg); in sdhci_readl()
765 if (unlikely(host->ops->read_w)) in sdhci_readw()
766 return host->ops->read_w(host, reg); in sdhci_readw()
768 return readw(host->ioaddr + reg); in sdhci_readw()
773 if (unlikely(host->ops->read_b)) in sdhci_readb()
774 return host->ops->read_b(host, reg); in sdhci_readb()
776 return readb(host->ioaddr + reg); in sdhci_readb()
783 writel(val, host->ioaddr + reg); in sdhci_writel()
788 writew(val, host->ioaddr + reg); in sdhci_writew()
793 writeb(val, host->ioaddr + reg); in sdhci_writeb()
798 return readl(host->ioaddr + reg); in sdhci_readl()
803 return readw(host->ioaddr + reg); in sdhci_readw()
808 return readb(host->ioaddr + reg); in sdhci_readb()
818 return host->private; in sdhci_priv()
897 void sdhci_switch_external_dma(struct sdhci_host *host, bool en);