Lines Matching full:tmclk
164 struct clk *tmclk; member
1724 * timeout clock and SW can choose TMCLK or SDCLK for hardware in sdhci_tegra_probe()
1729 * 12Mhz TMCLK which is advertised in host capability register. in sdhci_tegra_probe()
1730 * With TMCLK of 12Mhz provides maximum data timeout period that can in sdhci_tegra_probe()
1733 * So, TMCLK is set to 12Mhz and kept enabled all the time on SoC's in sdhci_tegra_probe()
1734 * supporting separate TMCLK. in sdhci_tegra_probe()
1738 clk = devm_clk_get(&pdev->dev, "tmclk"); in sdhci_tegra_probe()
1744 dev_warn(&pdev->dev, "failed to get tmclk: %d\n", rc); in sdhci_tegra_probe()
1752 "failed to enable tmclk: %d\n", rc); in sdhci_tegra_probe()
1756 tegra_host->tmclk = clk; in sdhci_tegra_probe()
1812 clk_disable_unprepare(tegra_host->tmclk); in sdhci_tegra_probe()
1833 clk_disable_unprepare(tegra_host->tmclk); in sdhci_tegra_remove()