Lines Matching +full:enable +full:- +full:ssc
1 // SPDX-License-Identifier: GPL-2.0+
7 * Version: v0.9.0 (2019-08-08)
18 #include "sdhci-cqhci.h"
19 #include "sdhci-pci.h"
21 #include "sdhci-uhs2.h"
395 /* enable tuning parameters control */ in gli_set_9750()
452 if (!host->tuning_done) { in __sdhci_execute_tuning_9750()
465 if (!host->tuning_done) { in __sdhci_execute_tuning_9750()
467 mmc_hostname(host->mmc)); in __sdhci_execute_tuning_9750()
468 return -ETIMEDOUT; in __sdhci_execute_tuning_9750()
472 mmc_hostname(host->mmc)); in __sdhci_execute_tuning_9750()
475 return -EAGAIN; in __sdhci_execute_tuning_9750()
480 host->mmc->retune_period = 0; in gl9750_execute_tuning()
481 if (host->tuning_mode == SDHCI_TUNING_MODE_1) in gl9750_execute_tuning()
482 host->mmc->retune_period = host->tuning_count; in gl9750_execute_tuning()
485 host->tuning_err = __sdhci_execute_tuning_9750(host, opcode); in gl9750_execute_tuning()
534 static void gl9750_set_ssc(struct sdhci_host *host, u8 enable, u8 step, u16 ppm) in gl9750_set_ssc() argument
537 u32 ssc; in gl9750_set_ssc() local
541 ssc = sdhci_readl(host, SDHCI_GLI_9750_PLLSSC); in gl9750_set_ssc()
544 ssc &= ~SDHCI_GLI_9750_PLLSSC_PPM; in gl9750_set_ssc()
546 FIELD_PREP(SDHCI_GLI_9750_PLLSSC_EN, enable); in gl9750_set_ssc()
547 ssc |= FIELD_PREP(SDHCI_GLI_9750_PLLSSC_PPM, ppm); in gl9750_set_ssc()
548 sdhci_writel(host, ssc, SDHCI_GLI_9750_PLLSSC); in gl9750_set_ssc()
555 bool enable = gl9750_ssc_enable(host); in gl9750_set_ssc_pll_205mhz() local
557 /* set pll to 205MHz and ssc */ in gl9750_set_ssc_pll_205mhz()
558 gl9750_set_ssc(host, enable, 0xF, 0x5A1D); in gl9750_set_ssc_pll_205mhz()
564 bool enable = gl9750_ssc_enable(host); in gl9750_set_ssc_pll_100mhz() local
566 /* set pll to 100MHz and ssc */ in gl9750_set_ssc_pll_100mhz()
567 gl9750_set_ssc(host, enable, 0xE, 0x51EC); in gl9750_set_ssc_pll_100mhz()
573 bool enable = gl9750_ssc_enable(host); in gl9750_set_ssc_pll_50mhz() local
575 /* set pll to 50MHz and ssc */ in gl9750_set_ssc_pll_50mhz()
576 gl9750_set_ssc(host, enable, 0xE, 0x51EC); in gl9750_set_ssc_pll_50mhz()
582 struct mmc_ios *ios = &host->mmc->ios; in sdhci_gl9750_set_clock()
585 host->mmc->actual_clock = 0; in sdhci_gl9750_set_clock()
593 clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock); in sdhci_gl9750_set_clock()
594 if (clock == 200000000 && ios->timing == MMC_TIMING_UHS_SDR104) { in sdhci_gl9750_set_clock()
595 host->mmc->actual_clock = 205000000; in sdhci_gl9750_set_clock()
613 pdev = slot->chip->pdev; in gl9750_hw_setting()
643 ret = pci_alloc_irq_vectors(slot->chip->pdev, 1, 1, in gli_pcie_enable_msi()
646 pr_warn("%s: enable PCI MSI failed, error=%d\n", in gli_pcie_enable_msi()
647 mmc_hostname(slot->host->mmc), ret); in gli_pcie_enable_msi()
651 slot->host->irq = pci_irq_vector(slot->chip->pdev, 0); in gli_pcie_enable_msi()
731 static void gl9755_set_ssc(struct pci_dev *pdev, u8 enable, u8 step, u16 ppm) in gl9755_set_ssc() argument
734 u32 ssc; in gl9755_set_ssc() local
738 pci_read_config_dword(pdev, PCI_GLI_9755_PLLSSC, &ssc); in gl9755_set_ssc()
741 ssc &= ~PCI_GLI_9755_PLLSSC_PPM; in gl9755_set_ssc()
743 FIELD_PREP(PCI_GLI_9755_PLLSSC_EN, enable); in gl9755_set_ssc()
744 ssc |= FIELD_PREP(PCI_GLI_9755_PLLSSC_PPM, ppm); in gl9755_set_ssc()
745 pci_write_config_dword(pdev, PCI_GLI_9755_PLLSSC, ssc); in gl9755_set_ssc()
752 bool enable = gl9755_ssc_enable(pdev); in gl9755_set_ssc_pll_205mhz() local
754 /* set pll to 205MHz and ssc */ in gl9755_set_ssc_pll_205mhz()
755 gl9755_set_ssc(pdev, enable, 0xF, 0x5A1D); in gl9755_set_ssc_pll_205mhz()
761 bool enable = gl9755_ssc_enable(pdev); in gl9755_set_ssc_pll_100mhz() local
763 /* set pll to 100MHz and ssc */ in gl9755_set_ssc_pll_100mhz()
764 gl9755_set_ssc(pdev, enable, 0xE, 0x51EC); in gl9755_set_ssc_pll_100mhz()
770 bool enable = gl9755_ssc_enable(pdev); in gl9755_set_ssc_pll_50mhz() local
772 /* set pll to 50MHz and ssc */ in gl9755_set_ssc_pll_50mhz()
773 gl9755_set_ssc(pdev, enable, 0xE, 0x51EC); in gl9755_set_ssc_pll_50mhz()
780 struct mmc_ios *ios = &host->mmc->ios; in sdhci_gl9755_set_clock()
784 pdev = slot->chip->pdev; in sdhci_gl9755_set_clock()
785 host->mmc->actual_clock = 0; in sdhci_gl9755_set_clock()
793 clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock); in sdhci_gl9755_set_clock()
794 if (clock == 200000000 && ios->timing == MMC_TIMING_UHS_SDR104) { in sdhci_gl9755_set_clock()
795 host->mmc->actual_clock = 205000000; in sdhci_gl9755_set_clock()
808 struct pci_dev *pdev = slot->chip->pdev; in gl9755_hw_setting()
819 if (of_property_read_bool(pdev->dev.of_node, "cd-inverted")) in gl9755_hw_setting()
821 if (of_property_read_bool(pdev->dev.of_node, "wp-inverted")) in gl9755_hw_setting()
827 /* enable short circuit protection */ in gl9755_hw_setting()
857 struct pci_dev *pdev = slot->chip->pdev; in gl9755_vendor_init()
918 static void sdhci_gli_overcurrent_event_enable(struct sdhci_host *host, bool enable) in sdhci_gli_overcurrent_event_enable() argument
923 if (enable) in sdhci_gli_overcurrent_event_enable()
931 if (enable) in sdhci_gli_overcurrent_event_enable()
947 WARN(1, "%s: Invalid vdd %#x\n", mmc_hostname(host->mmc), vdd); in gl9755_set_power()
951 if (host->pwr == pwr) in gl9755_set_power()
954 host->pwr = pwr; in gl9755_set_power()
981 pr_err("%s: Internal clock never stabilised.\n", mmc_hostname(host->mmc)); in sdhci_wait_clock_stable()
1010 pr_err("%s: Reset 0x%x never completed.\n", mmc_hostname(host->mmc), (int)mask); in sdhci_gli_wait_software_reset_done()
1014 return -ETIMEDOUT; in sdhci_gli_wait_software_reset_done()
1023 if (host->mmc->uhs2_sd_tran) { in sdhci_gli_uhs2_reset_sd_tran()
1025 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); in sdhci_gli_uhs2_reset_sd_tran()
1026 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); in sdhci_gli_uhs2_reset_sd_tran()
1041 /* reset sd-tran on UHS2 mode if need to reset cmd/data */ in sdhci_gl9755_reset()
1046 host->clock = 0; in sdhci_gl9755_reset()
1088 u8 enable; in gl9767_ssc_enable() local
1093 enable = FIELD_GET(PCIE_GLI_9767_COM_MAILBOX_SSC_EN, value); in gl9767_ssc_enable()
1097 return enable; in gl9767_ssc_enable()
1100 static void gl9767_set_ssc(struct pci_dev *pdev, u8 enable, u8 step, u16 ppm) in gl9767_set_ssc() argument
1103 u32 ssc; in gl9767_set_ssc() local
1108 pci_read_config_dword(pdev, PCIE_GLI_9767_SD_PLL_CTL2, &ssc); in gl9767_set_ssc()
1111 ssc &= ~PCIE_GLI_9767_SD_PLL_CTL2_PLLSSC_PPM; in gl9767_set_ssc()
1113 FIELD_PREP(PCIE_GLI_9767_SD_PLL_CTL_SSC_EN, enable); in gl9767_set_ssc()
1114 ssc |= FIELD_PREP(PCIE_GLI_9767_SD_PLL_CTL2_PLLSSC_PPM, ppm); in gl9767_set_ssc()
1115 pci_write_config_dword(pdev, PCIE_GLI_9767_SD_PLL_CTL2, ssc); in gl9767_set_ssc()
1144 bool enable = gl9767_ssc_enable(pdev); in gl9767_set_ssc_pll_205mhz() local
1146 /* set pll to 205MHz and ssc */ in gl9767_set_ssc_pll_205mhz()
1147 gl9767_set_ssc(pdev, enable, 0x1F, 0xF5C3); in gl9767_set_ssc_pll_205mhz()
1164 static void gl9767_set_low_power_negotiation(struct pci_dev *pdev, bool enable) in gl9767_set_low_power_negotiation() argument
1171 if (enable) in gl9767_set_low_power_negotiation()
1183 struct mmc_ios *ios = &host->mmc->ios; in sdhci_gl9767_set_clock()
1187 pdev = slot->chip->pdev; in sdhci_gl9767_set_clock()
1188 host->mmc->actual_clock = 0; in sdhci_gl9767_set_clock()
1199 clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock); in sdhci_gl9767_set_clock()
1200 if (clock == 200000000 && ios->timing == MMC_TIMING_UHS_SDR104) { in sdhci_gl9767_set_clock()
1201 host->mmc->actual_clock = 205000000; in sdhci_gl9767_set_clock()
1251 struct pci_dev *pdev = slot->chip->pdev; in gl9767_hw_setting()
1286 struct pci_dev *pdev = slot->chip->pdev; in sdhci_gl9767_reset()
1302 pr_warn("%s: %s: Reset SDHC AHB and TL-AMBA failure.\n", in sdhci_gl9767_reset()
1303 __func__, mmc_hostname(host->mmc)); in sdhci_gl9767_reset()
1310 if (mmc_card_uhs2(host->mmc)) { in sdhci_gl9767_reset()
1333 pdev = slot->chip->pdev; in gl9767_init_sd_express()
1335 if (mmc->ops->get_ro(mmc)) { in gl9767_init_sd_express()
1336 mmc->ios.timing &= ~(MMC_TIMING_SD_EXP | MMC_TIMING_SD_EXP_1_2V); in gl9767_init_sd_express()
1396 mmc->ios.timing &= ~(MMC_TIMING_SD_EXP | MMC_TIMING_SD_EXP_1_2V); in gl9767_init_sd_express()
1418 struct pci_dev *pdev = slot->chip->pdev; in gl9767_vendor_init()
1463 struct pci_dev *pdev = slot->chip->pdev; in sdhci_gl9767_set_power()
1466 if (mmc_card_uhs2(host->mmc)) { in sdhci_gl9767_set_power()
1497 struct sdhci_host *host = slot->host; in gli_probe_slot_gl9750()
1501 slot->host->mmc->caps2 |= MMC_CAP2_NO_SDIO; in gli_probe_slot_gl9750()
1509 struct sdhci_host *host = slot->host; in gli_probe_slot_gl9755()
1513 slot->host->mmc->caps2 |= MMC_CAP2_NO_SDIO; in gli_probe_slot_gl9755()
1522 struct sdhci_host *host = slot->host; in gli_probe_slot_gl9767()
1527 slot->host->mmc->caps2 |= MMC_CAP2_NO_SDIO; in gli_probe_slot_gl9767()
1528 host->mmc->caps2 |= MMC_CAP2_SD_EXP; in gli_probe_slot_gl9767()
1529 host->mmc_host_ops.init_sd_express = gl9767_init_sd_express; in gli_probe_slot_gl9767()
1542 * (6) Set 1.8V Signal Enable in the Host Control 2 register. in sdhci_gli_voltage_switch()
1545 * (8) If 1.8V Signal Enable is cleared by Host Controller, go to in sdhci_gli_voltage_switch()
1548 * Wait 5ms after set 1.8V signal enable in Host Control 2 register in sdhci_gli_voltage_switch()
1549 * to ensure 1.8V signal enable bit is set by GL9750/GL9755. in sdhci_gli_voltage_switch()
1565 * (6) Set 1.8V Signal Enable in the Host Control 2 register. in sdhci_gl9767_voltage_switch()
1568 * (8) If 1.8V Signal Enable is cleared by Host Controller, go to in sdhci_gl9767_voltage_switch()
1571 * Wait 5ms after set 1.8V signal enable in Host Control 2 register in sdhci_gl9767_voltage_switch()
1572 * to ensure 1.8V signal enable bit is set by GL9767. in sdhci_gl9767_voltage_switch()
1588 value = readl(host->ioaddr + reg); in sdhci_gl9750_readl()
1602 if (ios->enhanced_strobe) in gl9763e_hs400_enhanced_strobe()
1611 bool enable) in gl9763e_set_low_power_negotiation() argument
1613 struct pci_dev *pdev = slot->chip->pdev; in gl9763e_set_low_power_negotiation()
1623 if (enable) in gl9763e_set_low_power_negotiation()
1662 struct cqhci_host *cq_host = mmc->cqe_private; in sdhci_gl9763e_cqe_pre_enable()
1686 cqhci_irq(host->mmc, intmask, cmd_error, data_error); in sdhci_gl9763e_cqhci_irq()
1694 struct cqhci_host *cq_host = mmc->cqe_private; in sdhci_gl9763e_cqe_post_disable()
1704 .enable = sdhci_gl9763e_cqe_enable,
1713 struct device *dev = &slot->chip->pdev->dev; in gl9763e_add_host()
1714 struct sdhci_host *host = slot->host; in gl9763e_add_host()
1725 ret = -ENOMEM; in gl9763e_add_host()
1729 cq_host->mmio = host->ioaddr + SDHCI_GLI_9763E_CQE_BASE_ADDR; in gl9763e_add_host()
1730 cq_host->ops = &sdhci_gl9763e_cqhci_ops; in gl9763e_add_host()
1732 dma64 = host->flags & SDHCI_USE_64_BIT_DMA; in gl9763e_add_host()
1734 cq_host->caps |= CQHCI_TASK_DESC_SZ_128; in gl9763e_add_host()
1736 ret = cqhci_init(cq_host, host->mmc, dma64); in gl9763e_add_host()
1756 struct pci_dev *pdev = slot->chip->pdev; in gli_set_gl9763e()
1792 struct sdhci_pci_slot *slot = chip->slots[0]; in gl9763e_runtime_suspend()
1793 struct sdhci_host *host = slot->host; in gl9763e_runtime_suspend()
1796 /* Enable LPM negotiation to allow entering L1 state */ in gl9763e_runtime_suspend()
1808 struct sdhci_pci_slot *slot = chip->slots[0]; in gl9763e_runtime_resume()
1809 struct sdhci_host *host = slot->host; in gl9763e_runtime_resume()
1812 if (host->mmc->ios.power_mode != MMC_POWER_ON) in gl9763e_runtime_resume()
1825 mmc_hostname(host->mmc)); in gl9763e_runtime_resume()
1842 struct sdhci_pci_slot *slot = chip->slots[0]; in sdhci_pci_gli_resume()
1844 pci_free_irq_vectors(slot->chip->pdev); in sdhci_pci_gli_resume()
1852 struct sdhci_pci_slot *slot = chip->slots[0]; in gl9763e_resume()
1859 ret = cqhci_resume(slot->host->mmc); in gl9763e_resume()
1874 struct sdhci_pci_slot *slot = chip->slots[0]; in gl9763e_suspend()
1878 * Certain SoCs can suspend only with the bus in low- in gl9763e_suspend()
1880 * Re-enable LPM negotiation to allow entering L1 state in gl9763e_suspend()
1885 ret = cqhci_suspend(slot->host->mmc); in gl9763e_suspend()
1889 ret = sdhci_suspend_host(slot->host); in gl9763e_suspend()
1896 cqhci_resume(slot->host->mmc); in gl9763e_suspend()
1905 struct pci_dev *pdev = slot->chip->pdev; in gli_probe_slot_gl9763e()
1906 struct sdhci_host *host = slot->host; in gli_probe_slot_gl9763e()
1909 host->mmc->caps |= MMC_CAP_8_BIT_DATA | in gli_probe_slot_gl9763e()
1912 host->mmc->caps2 |= MMC_CAP2_HS200_1_8V_SDR | in gli_probe_slot_gl9763e()
1921 host->mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD; in gli_probe_slot_gl9763e()
1924 host->mmc_host_ops.hs400_enhanced_strobe = in gli_probe_slot_gl9763e()
1936 u32 val = readl(host->ioaddr + (reg & ~3)); in sdhci_gli_readw()
1945 u32 val = readl(host->ioaddr + (reg & ~3)); in sdhci_gli_readb()