459 	 * Write the selected DLL clock output phase (0 ... 15)  in msm_config_cm_dll_phase()
483 	dev_err(mmc_dev(mmc), "%s: Failed to set DLL phase: %d\n",  in msm_config_cm_dll_phase()
492  * DLL clock output phases that can be used as sampling
496  * Select the 3/4 of the range and configure the DLL with the
497  * selected DLL clock output phase.
632 /* Initialize the DLL (Programmable Delay Line) */
650 	 * Make sure that clock is always enabled when DLL  in msm_init_cm_dll()
712 		/* wait for 5us before enabling DLL clock */  in msm_init_cm_dll()
739 	 * Configure DLL user control register to enable DLL status.  in msm_init_cm_dll()
776 			dev_err(mmc_dev(mmc), "%s: DLL failed to LOCK\n",  in msm_init_cm_dll()
894  * correct input clock for DLL depending on the mode.
1066 	 * starts coming. Controllers with 14lpp and later tech DLL cannot  in sdhci_msm_cm_dll_sdc4_calibration()
1068 	 * turned on for host controllers using this DLL.  in sdhci_msm_cm_dll_sdc4_calibration()
1079 	 * Drain writebuffer to ensure above DLL calibration  in sdhci_msm_cm_dll_sdc4_calibration()
1080 	 * and PWRSAVE DLL is enabled.  in sdhci_msm_cm_dll_sdc4_calibration()
1157 	 * SDR DLL comes into picture only for timing modes which needs  in sdhci_msm_restore_sdr_dll_config()
1302  * sdhci_msm_hs400 - Calibrate the DLL for HS400 bus speed mode operation.
1304  * DLL operation is only needed for clock > 100MHz. For clock <= 100MHz
1320 			pr_err("%s: Failed to calibrate DLL for hs400 mode (%d)\n",  in sdhci_msm_hs400()
1362 	 * provided and DLL must not be used so that tuning can be skipped. To  in sdhci_msm_set_uhs_signaling()
1372 		 * DLL is not required for clock <= 100MHz  in sdhci_msm_set_uhs_signaling()
1373 		 * Thus, make sure DLL it is disabled when not required  in sdhci_msm_set_uhs_signaling()
1388 		 * The DLL needs to be restored and CDCLP533 recalibrated  in sdhci_msm_set_uhs_signaling()
2366 			"DLL sts: 0x%08x | DLL cfg:  0x%08x | DLL cfg2: 0x%08x\n",  in sdhci_msm_dump_vendor_regs()
2371 			"DLL cfg3: 0x%08x | DLL usr ctl:  0x%08x | DDR cfg: 0x%08x\n",  in sdhci_msm_dump_vendor_regs()
2462 	of_property_read_u32(node, "qcom,dll-config", &msm_host->dll_config);  in sdhci_msm_get_of_property()
2673 	 * with HS 400 mode support will use CM DLL instead of CDC LP 533 DLL.  in sdhci_msm_probe()
2830 	 * restore the SDR DLL settings when the clock is ungated.  in sdhci_msm_runtime_resume()