Lines Matching +full:hs400 +full:- +full:cmd +full:- +full:int +full:- +full:delay
1 // SPDX-License-Identifier: GPL-2.0
5 * derived from the OF-version.
14 #include <linux/delay.h>
23 #include <linux/mmc/slot-gpio.h>
28 #include "sdhci-cqhci.h"
29 #include "sdhci-pltfm.h"
30 #include "sdhci-esdhc.h"
83 #define ESDHC_TUNE_CTRL_MAX ((1 << 7) - 1)
128 * There is an INT DMA ERR mismatch between eSDHC and STD SDHC SPEC:
130 * but bit28 is used as the INT DMA ERR in fsl eSDHC design.
131 * Define this macro DMA error INT for fsl eSDHC
139 * The CMDTYPE of the CMD register (offset 0xE) should be set to
141 * open ended multi-blk IO. Otherwise the TC INT wouldn't
171 /* The IP supports HS400 mode */
222 * struct esdhc_platform_data - platform data for esdhc on i.MX
233 int max_bus_width;
234 unsigned int delay_line;
235 unsigned int tuning_step; /* The delay cell steps in tuning procedure */
236 unsigned int tuning_start_tap; /* The start delay cell point in tuning procedure */
237 unsigned int strobe_dll_delay_target; /* The delay cell for strobe pad (read clock) */
350 unsigned int actual_clock;
355 * the card init, but at this stage, mmc_host->card is not
359 unsigned int init_card_type;
363 MULTIBLK_IN_PROCESS, /* exact multiblock cmd in process */
364 WAIT_FOR_INT, /* sent CMD12, waiting for response INT */
371 { .compatible = "fsl,imx25-esdhc", .data = &esdhc_imx25_data, },
372 { .compatible = "fsl,imx35-esdhc", .data = &esdhc_imx35_data, },
373 { .compatible = "fsl,imx51-esdhc", .data = &esdhc_imx51_data, },
374 { .compatible = "fsl,imx53-esdhc", .data = &esdhc_imx53_data, },
375 { .compatible = "fsl,imx6sx-usdhc", .data = &usdhc_imx6sx_data, },
376 { .compatible = "fsl,imx6sl-usdhc", .data = &usdhc_imx6sl_data, },
377 { .compatible = "fsl,imx6sll-usdhc", .data = &usdhc_imx6sll_data, },
378 { .compatible = "fsl,imx6q-usdhc", .data = &usdhc_imx6q_data, },
379 { .compatible = "fsl,imx6ull-usdhc", .data = &usdhc_imx6ull_data, },
380 { .compatible = "fsl,imx7d-usdhc", .data = &usdhc_imx7d_data, },
381 { .compatible = "fsl,imx7ulp-usdhc", .data = &usdhc_imx7ulp_data, },
382 { .compatible = "fsl,imx8qxp-usdhc", .data = &usdhc_imx8qxp_data, },
383 { .compatible = "fsl,imx8mm-usdhc", .data = &usdhc_imx8mm_data, },
384 { .compatible = "fsl,imxrt1050-usdhc", .data = &usdhc_imxrt1050_data, },
385 { .compatible = "nxp,s32g2-usdhc", .data = &usdhc_s32g2_data, },
390 static inline int is_imx25_esdhc(struct pltfm_imx_data *data) in is_imx25_esdhc()
392 return data->socdata == &esdhc_imx25_data; in is_imx25_esdhc()
395 static inline int is_imx53_esdhc(struct pltfm_imx_data *data) in is_imx53_esdhc()
397 return data->socdata == &esdhc_imx53_data; in is_imx53_esdhc()
400 static inline int esdhc_is_usdhc(struct pltfm_imx_data *data) in esdhc_is_usdhc()
402 return !!(data->socdata->flags & ESDHC_FLAG_USDHC); in esdhc_is_usdhc()
405 static inline void esdhc_clrset_le(struct sdhci_host *host, u32 mask, u32 val, int reg) in esdhc_clrset_le()
407 void __iomem *base = host->ioaddr + (reg & ~0x3); in esdhc_clrset_le()
413 #define DRIVER_NAME "sdhci-esdhc-imx"
415 pr_err("%s: " DRIVER_NAME ": " f, mmc_hostname(host->mmc), ## x)
418 int i; in esdhc_dump_debug_regs()
420 "cmd debug status", in esdhc_dump_debug_regs()
434 readw(host->ioaddr + ESDHC_DEBUG_SEL_AND_STATUS_REG)); in esdhc_dump_debug_regs()
444 int ret; in esdhc_wait_for_card_clock_gate_off()
446 ret = readl_poll_timeout(host->ioaddr + ESDHC_PRSSTAT, present_state, in esdhc_wait_for_card_clock_gate_off()
448 if (ret == -ETIMEDOUT) in esdhc_wait_for_card_clock_gate_off()
449 dev_warn(mmc_dev(host->mmc), "%s: card clock still not gate off in 100us!.\n", __func__); in esdhc_wait_for_card_clock_gate_off()
452 /* Enable the auto tuning circuit to check the CMD line and BUS line */
460 buswidth = USDHC_GET_BUSWIDTH(readl(host->ioaddr + SDHCI_HOST_CONTROL)); in usdhc_auto_tuning_mode_sel_and_en()
480 * DAT[1], and adjust the delay cell wrongly. in usdhc_auto_tuning_mode_sel_and_en()
482 * device, config the auto tuning circuit only check DAT[0] and CMD in usdhc_auto_tuning_mode_sel_and_en()
485 if (imx_data->init_card_type == MMC_TYPE_SDIO) in usdhc_auto_tuning_mode_sel_and_en()
492 reg = readl(host->ioaddr + ESDHC_MIX_CTRL); in usdhc_auto_tuning_mode_sel_and_en()
494 writel(reg, host->ioaddr + ESDHC_MIX_CTRL); in usdhc_auto_tuning_mode_sel_and_en()
497 static u32 esdhc_readl_le(struct sdhci_host *host, int reg) in esdhc_readl_le()
501 u32 val = readl(host->ioaddr + reg); in esdhc_readl_le()
507 /* move dat[0-3] bits */ in esdhc_readl_le()
509 /* move cmd line bit */ in esdhc_readl_le()
514 /* ignore bit[0-15] as it stores cap_1 register val for mx6sl */ in esdhc_readl_le()
515 if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1) in esdhc_readl_le()
533 if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1) in esdhc_readl_le()
534 val = readl(host->ioaddr + SDHCI_CAPABILITIES) & 0xFFFF; in esdhc_readl_le()
547 if (IS_ERR_OR_NULL(imx_data->pins_100mhz)) in esdhc_readl_le()
549 if (IS_ERR_OR_NULL(imx_data->pins_200mhz)) in esdhc_readl_le()
571 if ((imx_data->multiblock_status == WAIT_FOR_INT) && in esdhc_readl_le()
574 writel(SDHCI_INT_RESPONSE, host->ioaddr + in esdhc_readl_le()
576 imx_data->multiblock_status = NO_CMD_PENDING; in esdhc_readl_le()
583 static void esdhc_writel_le(struct sdhci_host *host, u32 val, int reg) in esdhc_writel_le()
596 * and set D3CD bit will make eSDHC re-sample the card in esdhc_writel_le()
598 * re-sample it by the following steps. in esdhc_writel_le()
600 data = readl(host->ioaddr + SDHCI_HOST_CONTROL); in esdhc_writel_le()
602 writel(data, host->ioaddr + SDHCI_HOST_CONTROL); in esdhc_writel_le()
604 writel(data, host->ioaddr + SDHCI_HOST_CONTROL); in esdhc_writel_le()
613 if (unlikely((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT) in esdhc_writel_le()
617 v = readl(host->ioaddr + ESDHC_VENDOR_SPEC); in esdhc_writel_le()
619 writel(v, host->ioaddr + ESDHC_VENDOR_SPEC); in esdhc_writel_le()
621 if (imx_data->multiblock_status == MULTIBLK_IN_PROCESS) in esdhc_writel_le()
626 writel(data, host->ioaddr + SDHCI_TRANSFER_MODE); in esdhc_writel_le()
627 imx_data->multiblock_status = WAIT_FOR_INT; in esdhc_writel_le()
631 writel(val, host->ioaddr + reg); in esdhc_writel_le()
634 static u16 esdhc_readw_le(struct sdhci_host *host, int reg) in esdhc_readw_le()
653 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); in esdhc_readw_le()
658 if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) in esdhc_readw_le()
659 val = readl(host->ioaddr + ESDHC_MIX_CTRL); in esdhc_readw_le()
660 else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) in esdhc_readw_le()
662 val = readl(host->ioaddr + SDHCI_AUTO_CMD_STATUS); in esdhc_readw_le()
677 u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL); in esdhc_readw_le()
685 ret = readw(host->ioaddr + SDHCI_TRANSFER_MODE); in esdhc_readw_le()
691 return readw(host->ioaddr + reg); in esdhc_readw_le()
694 static void esdhc_writew_le(struct sdhci_host *host, u16 val, int reg) in esdhc_writew_le()
702 new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); in esdhc_writew_le()
707 writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC); in esdhc_writew_le()
712 new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); in esdhc_writew_le()
717 writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC); in esdhc_writew_le()
718 if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) { in esdhc_writew_le()
719 u32 v = readl(host->ioaddr + SDHCI_AUTO_CMD_STATUS); in esdhc_writew_le()
720 u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL); in esdhc_writew_le()
735 writel(v, host->ioaddr + SDHCI_AUTO_CMD_STATUS); in esdhc_writew_le()
736 writel(m, host->ioaddr + ESDHC_MIX_CTRL); in esdhc_writew_le()
740 if ((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT) in esdhc_writew_le()
741 && (host->cmd->opcode == SD_IO_RW_EXTENDED) in esdhc_writew_le()
742 && (host->cmd->data->blocks > 1) in esdhc_writew_le()
743 && (host->cmd->data->flags & MMC_DATA_READ)) { in esdhc_writew_le()
745 v = readl(host->ioaddr + ESDHC_VENDOR_SPEC); in esdhc_writew_le()
747 writel(v, host->ioaddr + ESDHC_VENDOR_SPEC); in esdhc_writew_le()
752 u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL); in esdhc_writew_le()
759 writel(m, host->ioaddr + ESDHC_MIX_CTRL); in esdhc_writew_le()
765 m = readl(host->ioaddr + ESDHC_WTMK_LVL); in esdhc_writew_le()
788 writel(m, host->ioaddr + ESDHC_WTMK_LVL); in esdhc_writew_le()
794 imx_data->scratchpad = val; in esdhc_writew_le()
798 if (host->cmd->opcode == MMC_STOP_TRANSMISSION) in esdhc_writew_le()
801 if ((host->cmd->opcode == MMC_SET_BLOCK_COUNT) && in esdhc_writew_le()
802 (imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT)) in esdhc_writew_le()
803 imx_data->multiblock_status = MULTIBLK_IN_PROCESS; in esdhc_writew_le()
807 host->ioaddr + SDHCI_TRANSFER_MODE); in esdhc_writew_le()
809 writel(val << 16 | imx_data->scratchpad, in esdhc_writew_le()
810 host->ioaddr + SDHCI_TRANSFER_MODE); in esdhc_writew_le()
819 static u8 esdhc_readb_le(struct sdhci_host *host, int reg) in esdhc_readb_le()
826 val = readl(host->ioaddr + reg); in esdhc_readb_le()
835 return readb(host->ioaddr + reg); in esdhc_readb_le()
838 static void esdhc_writeb_le(struct sdhci_host *host, u8 val, int reg) in esdhc_writeb_le()
875 new_val = readl(host->ioaddr + SDHCI_HOST_CONTROL); in esdhc_writeb_le()
900 new_val = readl(host->ioaddr + ESDHC_MIX_CTRL); in esdhc_writeb_le()
902 host->ioaddr + ESDHC_MIX_CTRL); in esdhc_writeb_le()
903 imx_data->is_ddr = 0; in esdhc_writeb_le()
917 static unsigned int esdhc_pltfm_get_max_clock(struct sdhci_host *host) in esdhc_pltfm_get_max_clock()
921 return pltfm_host->clock; in esdhc_pltfm_get_max_clock()
924 static unsigned int esdhc_pltfm_get_min_clock(struct sdhci_host *host) in esdhc_pltfm_get_min_clock()
928 return pltfm_host->clock / 256 / 16; in esdhc_pltfm_get_min_clock()
932 unsigned int clock) in esdhc_pltfm_set_clock()
936 unsigned int host_clock = pltfm_host->clock; in esdhc_pltfm_set_clock()
937 int ddr_pre_div = imx_data->is_ddr ? 2 : 1; in esdhc_pltfm_set_clock()
938 int pre_div = 1; in esdhc_pltfm_set_clock()
939 int div = 1; in esdhc_pltfm_set_clock()
940 int ret; in esdhc_pltfm_set_clock()
944 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); in esdhc_pltfm_set_clock()
946 host->ioaddr + ESDHC_VENDOR_SPEC); in esdhc_pltfm_set_clock()
951 host->mmc->actual_clock = 0; in esdhc_pltfm_set_clock()
961 val = readl(host->ioaddr + ESDHC_DLL_CTRL); in esdhc_pltfm_set_clock()
962 writel(val | BIT(10), host->ioaddr + ESDHC_DLL_CTRL); in esdhc_pltfm_set_clock()
963 temp = readl(host->ioaddr + ESDHC_DLL_CTRL); in esdhc_pltfm_set_clock()
964 writel(val, host->ioaddr + ESDHC_DLL_CTRL); in esdhc_pltfm_set_clock()
974 if ((imx_data->socdata->flags & ESDHC_FLAG_ERR010450) && in esdhc_pltfm_set_clock()
975 (!(host->quirks2 & SDHCI_QUIRK2_NO_1_8_V))) { in esdhc_pltfm_set_clock()
976 unsigned int max_clock; in esdhc_pltfm_set_clock()
978 max_clock = imx_data->is_ddr ? 45000000 : 150000000; in esdhc_pltfm_set_clock()
990 host->mmc->actual_clock = host_clock / (div * pre_div * ddr_pre_div); in esdhc_pltfm_set_clock()
991 dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n", in esdhc_pltfm_set_clock()
992 clock, host->mmc->actual_clock); in esdhc_pltfm_set_clock()
995 div--; in esdhc_pltfm_set_clock()
1004 ret = readl_poll_timeout(host->ioaddr + ESDHC_PRSSTAT, temp, in esdhc_pltfm_set_clock()
1006 if (ret == -ETIMEDOUT) in esdhc_pltfm_set_clock()
1007 dev_warn(mmc_dev(host->mmc), "card clock still not stable in 100us!.\n"); in esdhc_pltfm_set_clock()
1010 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); in esdhc_pltfm_set_clock()
1012 host->ioaddr + ESDHC_VENDOR_SPEC); in esdhc_pltfm_set_clock()
1017 static unsigned int esdhc_pltfm_get_ro(struct sdhci_host *host) in esdhc_pltfm_get_ro()
1021 struct esdhc_platform_data *boarddata = &imx_data->boarddata; in esdhc_pltfm_get_ro()
1023 switch (boarddata->wp_type) { in esdhc_pltfm_get_ro()
1025 return mmc_gpio_get_ro(host->mmc); in esdhc_pltfm_get_ro()
1027 return !(readl(host->ioaddr + SDHCI_PRESENT_STATE) & in esdhc_pltfm_get_ro()
1033 return -ENOSYS; in esdhc_pltfm_get_ro()
1036 static void esdhc_pltfm_set_bus_width(struct sdhci_host *host, int width) in esdhc_pltfm_set_bus_width()
1061 int ret; in esdhc_reset_tuning()
1065 ctrl = readl(host->ioaddr + ESDHC_MIX_CTRL); in esdhc_reset_tuning()
1067 if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) { in esdhc_reset_tuning()
1070 writel(ctrl, host->ioaddr + ESDHC_MIX_CTRL); in esdhc_reset_tuning()
1071 writel(0, host->ioaddr + ESDHC_TUNE_CTRL_STATUS); in esdhc_reset_tuning()
1072 } else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) { in esdhc_reset_tuning()
1073 writel(ctrl, host->ioaddr + ESDHC_MIX_CTRL); in esdhc_reset_tuning()
1074 ctrl = readl(host->ioaddr + SDHCI_AUTO_CMD_STATUS); in esdhc_reset_tuning()
1077 writel(ctrl, host->ioaddr + SDHCI_AUTO_CMD_STATUS); in esdhc_reset_tuning()
1079 ret = readl_poll_timeout(host->ioaddr + SDHCI_AUTO_CMD_STATUS, in esdhc_reset_tuning()
1081 if (ret == -ETIMEDOUT) in esdhc_reset_tuning()
1082 dev_warn(mmc_dev(host->mmc), in esdhc_reset_tuning()
1089 ctrl = readl(host->ioaddr + SDHCI_INT_STATUS); in esdhc_reset_tuning()
1091 writel(ctrl, host->ioaddr + SDHCI_INT_STATUS); in esdhc_reset_tuning()
1102 imx_data->init_card_type = card->type; in usdhc_init_card()
1105 static int usdhc_execute_tuning(struct mmc_host *mmc, u32 opcode) in usdhc_execute_tuning()
1108 int err; in usdhc_execute_tuning()
1114 if (host->timing == MMC_TIMING_UHS_DDR50) in usdhc_execute_tuning()
1120 * correct delay cell. in usdhc_execute_tuning()
1125 if (!err && !host->tuning_err) in usdhc_execute_tuning()
1135 int ret; in esdhc_prepare_tuning()
1137 /* FIXME: delay a bit for card to be ready for next tuning due to errors */ in esdhc_prepare_tuning()
1142 ret = readb_poll_timeout(host->ioaddr + SDHCI_SOFTWARE_RESET, sw_rst, in esdhc_prepare_tuning()
1144 if (ret == -ETIMEDOUT) in esdhc_prepare_tuning()
1145 dev_warn(mmc_dev(host->mmc), in esdhc_prepare_tuning()
1148 reg = readl(host->ioaddr + ESDHC_MIX_CTRL); in esdhc_prepare_tuning()
1151 writel(reg, host->ioaddr + ESDHC_MIX_CTRL); in esdhc_prepare_tuning()
1152 writel(val << 8, host->ioaddr + ESDHC_TUNE_CTRL_STATUS); in esdhc_prepare_tuning()
1153 dev_dbg(mmc_dev(host->mmc), in esdhc_prepare_tuning()
1154 "tuning with delay 0x%x ESDHC_TUNE_CTRL_STATUS 0x%x\n", in esdhc_prepare_tuning()
1155 val, readl(host->ioaddr + ESDHC_TUNE_CTRL_STATUS)); in esdhc_prepare_tuning()
1162 reg = readl(host->ioaddr + ESDHC_MIX_CTRL); in esdhc_post_tuning()
1164 writel(reg, host->ioaddr + ESDHC_MIX_CTRL); in esdhc_post_tuning()
1168 * find the largest pass window, and use the average delay of this
1171 static int esdhc_executing_tuning(struct sdhci_host *host, u32 opcode) in esdhc_executing_tuning()
1173 int min, max, avg, ret; in esdhc_executing_tuning()
1174 int win_length, target_min, target_max, target_win_length; in esdhc_executing_tuning()
1180 /* find the mininum delay first which can pass tuning */ in esdhc_executing_tuning()
1183 if (!mmc_send_tuning(host->mmc, opcode, NULL)) in esdhc_executing_tuning()
1188 /* find the maxinum delay which can not pass tuning */ in esdhc_executing_tuning()
1192 if (mmc_send_tuning(host->mmc, opcode, NULL)) { in esdhc_executing_tuning()
1193 max -= ESDHC_TUNE_CTRL_STEP; in esdhc_executing_tuning()
1199 win_length = max - min + 1; in esdhc_executing_tuning()
1211 /* use average delay to get the best timing */ in esdhc_executing_tuning()
1214 ret = mmc_send_tuning(host->mmc, opcode, NULL); in esdhc_executing_tuning()
1217 dev_dbg(mmc_dev(host->mmc), "tuning %s at 0x%x ret %d\n", in esdhc_executing_tuning()
1228 m = readl(host->ioaddr + ESDHC_MIX_CTRL); in esdhc_hs400_enhanced_strobe()
1229 if (ios->enhanced_strobe) in esdhc_hs400_enhanced_strobe()
1233 writel(m, host->ioaddr + ESDHC_MIX_CTRL); in esdhc_hs400_enhanced_strobe()
1236 static int esdhc_change_pinstate(struct sdhci_host *host, in esdhc_change_pinstate()
1237 unsigned int uhs) in esdhc_change_pinstate()
1243 dev_dbg(mmc_dev(host->mmc), "change pinctrl state for uhs %d\n", uhs); in esdhc_change_pinstate()
1245 if (IS_ERR(imx_data->pinctrl) || in esdhc_change_pinstate()
1246 IS_ERR(imx_data->pins_100mhz) || in esdhc_change_pinstate()
1247 IS_ERR(imx_data->pins_200mhz)) in esdhc_change_pinstate()
1248 return -EINVAL; in esdhc_change_pinstate()
1253 pinctrl = imx_data->pins_100mhz; in esdhc_change_pinstate()
1258 pinctrl = imx_data->pins_200mhz; in esdhc_change_pinstate()
1262 return pinctrl_select_default_state(mmc_dev(host->mmc)); in esdhc_change_pinstate()
1265 return pinctrl_select_state(imx_data->pinctrl, pinctrl); in esdhc_change_pinstate()
1269 * For HS400 eMMC, there is a data_strobe line. This signal is generated
1271 * in HS400 mode. The frequency of this signal follows the frequency of
1273 * edge of data_strobe line. Due to the time delay between CLK line and
1274 * data_strobe line, if the delay time is larger than one clock cycle,
1283 int ret; in esdhc_set_strobe_dll()
1286 writel(readl(host->ioaddr + ESDHC_VENDOR_SPEC) & in esdhc_set_strobe_dll()
1288 host->ioaddr + ESDHC_VENDOR_SPEC); in esdhc_set_strobe_dll()
1293 host->ioaddr + ESDHC_STROBE_DLL_CTRL); in esdhc_set_strobe_dll()
1295 writel(0, host->ioaddr + ESDHC_STROBE_DLL_CTRL); in esdhc_set_strobe_dll()
1298 * enable strobe dll ctrl and adjust the delay target in esdhc_set_strobe_dll()
1301 if (imx_data->boarddata.strobe_dll_delay_target) in esdhc_set_strobe_dll()
1302 strobe_delay = imx_data->boarddata.strobe_dll_delay_target; in esdhc_set_strobe_dll()
1308 writel(v, host->ioaddr + ESDHC_STROBE_DLL_CTRL); in esdhc_set_strobe_dll()
1311 ret = readl_poll_timeout(host->ioaddr + ESDHC_STROBE_DLL_STATUS, v, in esdhc_set_strobe_dll()
1313 if (ret == -ETIMEDOUT) in esdhc_set_strobe_dll()
1314 dev_warn(mmc_dev(host->mmc), in esdhc_set_strobe_dll()
1315 "warning! HS400 strobe DLL status REF/SLV not lock in 50us, STROBE DLL status is %x!\n", v); in esdhc_set_strobe_dll()
1323 struct esdhc_platform_data *boarddata = &imx_data->boarddata; in esdhc_set_uhs_signaling()
1325 /* disable ddr mode and disable HS400 mode */ in esdhc_set_uhs_signaling()
1326 m = readl(host->ioaddr + ESDHC_MIX_CTRL); in esdhc_set_uhs_signaling()
1328 imx_data->is_ddr = 0; in esdhc_set_uhs_signaling()
1337 writel(m, host->ioaddr + ESDHC_MIX_CTRL); in esdhc_set_uhs_signaling()
1342 writel(m, host->ioaddr + ESDHC_MIX_CTRL); in esdhc_set_uhs_signaling()
1343 imx_data->is_ddr = 1; in esdhc_set_uhs_signaling()
1344 if (boarddata->delay_line) { in esdhc_set_uhs_signaling()
1346 v = boarddata->delay_line << in esdhc_set_uhs_signaling()
1351 writel(v, host->ioaddr + ESDHC_DLL_CTRL); in esdhc_set_uhs_signaling()
1356 writel(m, host->ioaddr + ESDHC_MIX_CTRL); in esdhc_set_uhs_signaling()
1357 imx_data->is_ddr = 1; in esdhc_set_uhs_signaling()
1359 host->ops->set_clock(host, host->clock); in esdhc_set_uhs_signaling()
1375 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); in esdhc_reset()
1376 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); in esdhc_reset()
1379 static unsigned int esdhc_get_max_timeout_count(struct sdhci_host *host) in esdhc_get_max_timeout_count()
1388 static void esdhc_set_timeout(struct sdhci_host *host, struct mmc_command *cmd) in esdhc_set_timeout() argument
1401 int cmd_error = 0; in esdhc_cqhci_irq()
1402 int data_error = 0; in esdhc_cqhci_irq()
1407 cqhci_irq(host->mmc, intmask, cmd_error, data_error); in esdhc_cqhci_irq()
1415 /* eMMC spec requires minimum 1us, here delay between 1-10us */ in esdhc_hw_reset()
1419 /* eMMC spec requires minimum 200us, here delay between 200-300us */ in esdhc_hw_reset()
1456 struct cqhci_host *cq_host = host->mmc->cqe_private; in sdhci_esdhc_imx_hwinit()
1464 writel(ESDHC_WTMK_DEFAULT_VAL, host->ioaddr + ESDHC_WTMK_LVL); in sdhci_esdhc_imx_hwinit()
1477 writel(readl(host->ioaddr + SDHCI_HOST_CONTROL) in sdhci_esdhc_imx_hwinit()
1479 host->ioaddr + SDHCI_HOST_CONTROL); in sdhci_esdhc_imx_hwinit()
1485 if (!(imx_data->socdata->flags & ESDHC_FLAG_SKIP_ERR004536)) { in sdhci_esdhc_imx_hwinit()
1486 writel(readl(host->ioaddr + 0x6c) & ~BIT(7), in sdhci_esdhc_imx_hwinit()
1487 host->ioaddr + 0x6c); in sdhci_esdhc_imx_hwinit()
1490 /* disable DLL_CTRL delay line settings */ in sdhci_esdhc_imx_hwinit()
1491 writel(0x0, host->ioaddr + ESDHC_DLL_CTRL); in sdhci_esdhc_imx_hwinit()
1497 * When CQHCI use DCMD to send a CMD need R1b respons, in sdhci_esdhc_imx_hwinit()
1502 if (imx_data->socdata->flags & ESDHC_FLAG_CQHCI) { in sdhci_esdhc_imx_hwinit()
1503 tmp = readl(host->ioaddr + ESDHC_VEND_SPEC2); in sdhci_esdhc_imx_hwinit()
1505 writel(tmp, host->ioaddr + ESDHC_VEND_SPEC2); in sdhci_esdhc_imx_hwinit()
1507 host->quirks &= ~SDHCI_QUIRK_NO_BUSY_IRQ; in sdhci_esdhc_imx_hwinit()
1510 if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) { in sdhci_esdhc_imx_hwinit()
1511 tmp = readl(host->ioaddr + ESDHC_TUNING_CTRL); in sdhci_esdhc_imx_hwinit()
1519 if (imx_data->boarddata.tuning_start_tap) in sdhci_esdhc_imx_hwinit()
1520 tmp |= imx_data->boarddata.tuning_start_tap; in sdhci_esdhc_imx_hwinit()
1524 if (imx_data->boarddata.tuning_step) { in sdhci_esdhc_imx_hwinit()
1525 tmp |= imx_data->boarddata.tuning_step in sdhci_esdhc_imx_hwinit()
1532 /* Disable the CMD CRC check for tuning, if not, need to in sdhci_esdhc_imx_hwinit()
1533 * add some delay after every tuning command, because in sdhci_esdhc_imx_hwinit()
1535 * step once it detect the CMD CRC error, will not wait for in sdhci_esdhc_imx_hwinit()
1543 writel(tmp, host->ioaddr + ESDHC_TUNING_CTRL); in sdhci_esdhc_imx_hwinit()
1544 } else if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) { in sdhci_esdhc_imx_hwinit()
1550 tmp = readl(host->ioaddr + ESDHC_TUNING_CTRL); in sdhci_esdhc_imx_hwinit()
1552 writel(tmp, host->ioaddr + ESDHC_TUNING_CTRL); in sdhci_esdhc_imx_hwinit()
1575 struct cqhci_host *cq_host = mmc->cqe_private; in esdhc_cqe_enable()
1578 int count = 10; in esdhc_cqe_enable()
1588 if (count-- == 0) { in esdhc_cqe_enable()
1589 dev_warn(mmc_dev(host->mmc), in esdhc_cqe_enable()
1602 if (host->flags & SDHCI_REQ_USE_DMA) in esdhc_cqe_enable()
1604 if (!(host->quirks2 & SDHCI_QUIRK2_SUPPORT_SINGLE)) in esdhc_cqe_enable()
1616 dev_err(mmc_dev(host->mmc), in esdhc_cqe_enable()
1634 static int
1639 struct device_node *np = pdev->dev.of_node; in sdhci_esdhc_imx_probe_dt()
1640 struct esdhc_platform_data *boarddata = &imx_data->boarddata; in sdhci_esdhc_imx_probe_dt()
1641 int ret; in sdhci_esdhc_imx_probe_dt()
1643 if (of_property_read_bool(np, "fsl,wp-controller")) in sdhci_esdhc_imx_probe_dt()
1644 boarddata->wp_type = ESDHC_WP_CONTROLLER; in sdhci_esdhc_imx_probe_dt()
1651 if (of_property_present(np, "wp-gpios")) in sdhci_esdhc_imx_probe_dt()
1652 boarddata->wp_type = ESDHC_WP_GPIO; in sdhci_esdhc_imx_probe_dt()
1654 of_property_read_u32(np, "fsl,tuning-step", &boarddata->tuning_step); in sdhci_esdhc_imx_probe_dt()
1655 of_property_read_u32(np, "fsl,tuning-start-tap", in sdhci_esdhc_imx_probe_dt()
1656 &boarddata->tuning_start_tap); in sdhci_esdhc_imx_probe_dt()
1658 of_property_read_u32(np, "fsl,strobe-dll-delay-target", in sdhci_esdhc_imx_probe_dt()
1659 &boarddata->strobe_dll_delay_target); in sdhci_esdhc_imx_probe_dt()
1660 if (of_property_read_bool(np, "no-1-8-v")) in sdhci_esdhc_imx_probe_dt()
1661 host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V; in sdhci_esdhc_imx_probe_dt()
1663 if (of_property_read_u32(np, "fsl,delay-line", &boarddata->delay_line)) in sdhci_esdhc_imx_probe_dt()
1664 boarddata->delay_line = 0; in sdhci_esdhc_imx_probe_dt()
1666 mmc_of_parse_voltage(host->mmc, &host->ocr_mask); in sdhci_esdhc_imx_probe_dt()
1668 if (esdhc_is_usdhc(imx_data) && !IS_ERR(imx_data->pinctrl)) { in sdhci_esdhc_imx_probe_dt()
1669 imx_data->pins_100mhz = pinctrl_lookup_state(imx_data->pinctrl, in sdhci_esdhc_imx_probe_dt()
1671 imx_data->pins_200mhz = pinctrl_lookup_state(imx_data->pinctrl, in sdhci_esdhc_imx_probe_dt()
1676 ret = mmc_of_parse(host->mmc); in sdhci_esdhc_imx_probe_dt()
1680 /* HS400/HS400ES require 8 bit bus */ in sdhci_esdhc_imx_probe_dt()
1681 if (!(host->mmc->caps & MMC_CAP_8_BIT_DATA)) in sdhci_esdhc_imx_probe_dt()
1682 host->mmc->caps2 &= ~(MMC_CAP2_HS400 | MMC_CAP2_HS400_ES); in sdhci_esdhc_imx_probe_dt()
1684 if (mmc_gpio_get_cd(host->mmc) >= 0) in sdhci_esdhc_imx_probe_dt()
1685 host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION; in sdhci_esdhc_imx_probe_dt()
1690 static int sdhci_esdhc_imx_probe(struct platform_device *pdev) in sdhci_esdhc_imx_probe()
1695 int err; in sdhci_esdhc_imx_probe()
1707 imx_data->socdata = device_get_match_data(&pdev->dev); in sdhci_esdhc_imx_probe()
1709 host->quirks |= imx_data->socdata->quirks; in sdhci_esdhc_imx_probe()
1710 if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS) in sdhci_esdhc_imx_probe()
1711 cpu_latency_qos_add_request(&imx_data->pm_qos_req, 0); in sdhci_esdhc_imx_probe()
1713 imx_data->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); in sdhci_esdhc_imx_probe()
1714 if (IS_ERR(imx_data->clk_ipg)) { in sdhci_esdhc_imx_probe()
1715 err = PTR_ERR(imx_data->clk_ipg); in sdhci_esdhc_imx_probe()
1719 imx_data->clk_ahb = devm_clk_get(&pdev->dev, "ahb"); in sdhci_esdhc_imx_probe()
1720 if (IS_ERR(imx_data->clk_ahb)) { in sdhci_esdhc_imx_probe()
1721 err = PTR_ERR(imx_data->clk_ahb); in sdhci_esdhc_imx_probe()
1725 imx_data->clk_per = devm_clk_get(&pdev->dev, "per"); in sdhci_esdhc_imx_probe()
1726 if (IS_ERR(imx_data->clk_per)) { in sdhci_esdhc_imx_probe()
1727 err = PTR_ERR(imx_data->clk_per); in sdhci_esdhc_imx_probe()
1731 pltfm_host->clk = imx_data->clk_per; in sdhci_esdhc_imx_probe()
1732 err = clk_prepare_enable(imx_data->clk_per); in sdhci_esdhc_imx_probe()
1735 err = clk_prepare_enable(imx_data->clk_ipg); in sdhci_esdhc_imx_probe()
1738 err = clk_prepare_enable(imx_data->clk_ahb); in sdhci_esdhc_imx_probe()
1742 pltfm_host->clock = clk_get_rate(pltfm_host->clk); in sdhci_esdhc_imx_probe()
1743 if (!pltfm_host->clock) { in sdhci_esdhc_imx_probe()
1744 dev_err(mmc_dev(host->mmc), "could not get clk rate\n"); in sdhci_esdhc_imx_probe()
1745 err = -EINVAL; in sdhci_esdhc_imx_probe()
1749 imx_data->pinctrl = devm_pinctrl_get(&pdev->dev); in sdhci_esdhc_imx_probe()
1750 if (IS_ERR(imx_data->pinctrl)) in sdhci_esdhc_imx_probe()
1751 dev_warn(mmc_dev(host->mmc), "could not get pinctrl\n"); in sdhci_esdhc_imx_probe()
1754 host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN; in sdhci_esdhc_imx_probe()
1755 host->mmc->caps |= MMC_CAP_1_8V_DDR | MMC_CAP_3_3V_DDR; in sdhci_esdhc_imx_probe()
1758 if (!(imx_data->socdata->flags & ESDHC_FLAG_SKIP_CD_WAKE)) in sdhci_esdhc_imx_probe()
1759 host->mmc->caps |= MMC_CAP_CD_WAKE; in sdhci_esdhc_imx_probe()
1761 if (!(imx_data->socdata->flags & ESDHC_FLAG_HS200)) in sdhci_esdhc_imx_probe()
1762 host->quirks2 |= SDHCI_QUIRK2_BROKEN_HS200; in sdhci_esdhc_imx_probe()
1765 writel(0x0, host->ioaddr + ESDHC_MIX_CTRL); in sdhci_esdhc_imx_probe()
1766 writel(0x0, host->ioaddr + SDHCI_AUTO_CMD_STATUS); in sdhci_esdhc_imx_probe()
1767 writel(0x0, host->ioaddr + ESDHC_TUNE_CTRL_STATUS); in sdhci_esdhc_imx_probe()
1773 host->mmc_host_ops.execute_tuning = usdhc_execute_tuning; in sdhci_esdhc_imx_probe()
1779 host->mmc_host_ops.init_card = usdhc_init_card; in sdhci_esdhc_imx_probe()
1782 if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) in sdhci_esdhc_imx_probe()
1786 if (imx_data->socdata->flags & ESDHC_FLAG_ERR004536) in sdhci_esdhc_imx_probe()
1787 host->quirks |= SDHCI_QUIRK_BROKEN_ADMA; in sdhci_esdhc_imx_probe()
1789 if (imx_data->socdata->flags & ESDHC_FLAG_HS400) in sdhci_esdhc_imx_probe()
1790 host->mmc->caps2 |= MMC_CAP2_HS400; in sdhci_esdhc_imx_probe()
1792 if (imx_data->socdata->flags & ESDHC_FLAG_BROKEN_AUTO_CMD23) in sdhci_esdhc_imx_probe()
1793 host->quirks2 |= SDHCI_QUIRK2_ACMD23_BROKEN; in sdhci_esdhc_imx_probe()
1795 if (imx_data->socdata->flags & ESDHC_FLAG_HS400_ES) { in sdhci_esdhc_imx_probe()
1796 host->mmc->caps2 |= MMC_CAP2_HS400_ES; in sdhci_esdhc_imx_probe()
1797 host->mmc_host_ops.hs400_enhanced_strobe = in sdhci_esdhc_imx_probe()
1801 if (imx_data->socdata->flags & ESDHC_FLAG_CQHCI) { in sdhci_esdhc_imx_probe()
1802 host->mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD; in sdhci_esdhc_imx_probe()
1803 cq_host = devm_kzalloc(&pdev->dev, sizeof(*cq_host), GFP_KERNEL); in sdhci_esdhc_imx_probe()
1805 err = -ENOMEM; in sdhci_esdhc_imx_probe()
1809 cq_host->mmio = host->ioaddr + ESDHC_CQHCI_ADDR_OFFSET; in sdhci_esdhc_imx_probe()
1810 cq_host->ops = &esdhc_cqhci_ops; in sdhci_esdhc_imx_probe()
1812 err = cqhci_init(cq_host, host->mmc, false); in sdhci_esdhc_imx_probe()
1831 if ((host->mmc->pm_caps & MMC_PM_KEEP_POWER) && in sdhci_esdhc_imx_probe()
1832 (host->mmc->pm_caps & MMC_PM_WAKE_SDIO_IRQ)) in sdhci_esdhc_imx_probe()
1833 device_set_wakeup_capable(&pdev->dev, true); in sdhci_esdhc_imx_probe()
1835 pm_runtime_set_active(&pdev->dev); in sdhci_esdhc_imx_probe()
1836 pm_runtime_set_autosuspend_delay(&pdev->dev, 50); in sdhci_esdhc_imx_probe()
1837 pm_runtime_use_autosuspend(&pdev->dev); in sdhci_esdhc_imx_probe()
1838 pm_suspend_ignore_children(&pdev->dev, 1); in sdhci_esdhc_imx_probe()
1839 pm_runtime_enable(&pdev->dev); in sdhci_esdhc_imx_probe()
1844 clk_disable_unprepare(imx_data->clk_ahb); in sdhci_esdhc_imx_probe()
1846 clk_disable_unprepare(imx_data->clk_ipg); in sdhci_esdhc_imx_probe()
1848 clk_disable_unprepare(imx_data->clk_per); in sdhci_esdhc_imx_probe()
1850 if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS) in sdhci_esdhc_imx_probe()
1851 cpu_latency_qos_remove_request(&imx_data->pm_qos_req); in sdhci_esdhc_imx_probe()
1861 int dead; in sdhci_esdhc_imx_remove()
1863 pm_runtime_get_sync(&pdev->dev); in sdhci_esdhc_imx_remove()
1864 dead = (readl(host->ioaddr + SDHCI_INT_STATUS) == 0xffffffff); in sdhci_esdhc_imx_remove()
1865 pm_runtime_disable(&pdev->dev); in sdhci_esdhc_imx_remove()
1866 pm_runtime_put_noidle(&pdev->dev); in sdhci_esdhc_imx_remove()
1870 clk_disable_unprepare(imx_data->clk_per); in sdhci_esdhc_imx_remove()
1871 clk_disable_unprepare(imx_data->clk_ipg); in sdhci_esdhc_imx_remove()
1872 clk_disable_unprepare(imx_data->clk_ahb); in sdhci_esdhc_imx_remove()
1874 if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS) in sdhci_esdhc_imx_remove()
1875 cpu_latency_qos_remove_request(&imx_data->pm_qos_req); in sdhci_esdhc_imx_remove()
1881 static int sdhci_esdhc_suspend(struct device *dev) in sdhci_esdhc_suspend()
1886 int ret; in sdhci_esdhc_suspend()
1888 if (host->mmc->caps2 & MMC_CAP2_CQE) { in sdhci_esdhc_suspend()
1889 ret = cqhci_suspend(host->mmc); in sdhci_esdhc_suspend()
1894 if ((imx_data->socdata->flags & ESDHC_FLAG_STATE_LOST_IN_LPMODE) && in sdhci_esdhc_suspend()
1895 (host->tuning_mode != SDHCI_TUNING_MODE_1)) { in sdhci_esdhc_suspend()
1896 mmc_retune_timer_stop(host->mmc); in sdhci_esdhc_suspend()
1897 mmc_retune_needed(host->mmc); in sdhci_esdhc_suspend()
1900 if (host->tuning_mode != SDHCI_TUNING_MODE_3) in sdhci_esdhc_suspend()
1901 mmc_retune_needed(host->mmc); in sdhci_esdhc_suspend()
1911 ret = mmc_gpio_set_cd_wake(host->mmc, true); in sdhci_esdhc_suspend()
1916 static int sdhci_esdhc_resume(struct device *dev) in sdhci_esdhc_resume()
1919 int ret; in sdhci_esdhc_resume()
1925 /* re-initialize hw state in case it's lost in low power mode */ in sdhci_esdhc_resume()
1932 if (host->mmc->caps2 & MMC_CAP2_CQE) in sdhci_esdhc_resume()
1933 ret = cqhci_resume(host->mmc); in sdhci_esdhc_resume()
1936 ret = mmc_gpio_set_cd_wake(host->mmc, false); in sdhci_esdhc_resume()
1943 static int sdhci_esdhc_runtime_suspend(struct device *dev) in sdhci_esdhc_runtime_suspend()
1948 int ret; in sdhci_esdhc_runtime_suspend()
1950 if (host->mmc->caps2 & MMC_CAP2_CQE) { in sdhci_esdhc_runtime_suspend()
1951 ret = cqhci_suspend(host->mmc); in sdhci_esdhc_runtime_suspend()
1960 if (host->tuning_mode != SDHCI_TUNING_MODE_3) in sdhci_esdhc_runtime_suspend()
1961 mmc_retune_needed(host->mmc); in sdhci_esdhc_runtime_suspend()
1963 imx_data->actual_clock = host->mmc->actual_clock; in sdhci_esdhc_runtime_suspend()
1965 clk_disable_unprepare(imx_data->clk_per); in sdhci_esdhc_runtime_suspend()
1966 clk_disable_unprepare(imx_data->clk_ipg); in sdhci_esdhc_runtime_suspend()
1967 clk_disable_unprepare(imx_data->clk_ahb); in sdhci_esdhc_runtime_suspend()
1969 if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS) in sdhci_esdhc_runtime_suspend()
1970 cpu_latency_qos_remove_request(&imx_data->pm_qos_req); in sdhci_esdhc_runtime_suspend()
1975 static int sdhci_esdhc_runtime_resume(struct device *dev) in sdhci_esdhc_runtime_resume()
1980 int err; in sdhci_esdhc_runtime_resume()
1982 if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS) in sdhci_esdhc_runtime_resume()
1983 cpu_latency_qos_add_request(&imx_data->pm_qos_req, 0); in sdhci_esdhc_runtime_resume()
1985 if (imx_data->socdata->flags & ESDHC_FLAG_CLK_RATE_LOST_IN_PM_RUNTIME) in sdhci_esdhc_runtime_resume()
1986 clk_set_rate(imx_data->clk_per, pltfm_host->clock); in sdhci_esdhc_runtime_resume()
1988 err = clk_prepare_enable(imx_data->clk_ahb); in sdhci_esdhc_runtime_resume()
1992 err = clk_prepare_enable(imx_data->clk_per); in sdhci_esdhc_runtime_resume()
1996 err = clk_prepare_enable(imx_data->clk_ipg); in sdhci_esdhc_runtime_resume()
2000 esdhc_pltfm_set_clock(host, imx_data->actual_clock); in sdhci_esdhc_runtime_resume()
2006 if (host->mmc->caps2 & MMC_CAP2_CQE) in sdhci_esdhc_runtime_resume()
2007 err = cqhci_resume(host->mmc); in sdhci_esdhc_runtime_resume()
2012 clk_disable_unprepare(imx_data->clk_ipg); in sdhci_esdhc_runtime_resume()
2014 clk_disable_unprepare(imx_data->clk_per); in sdhci_esdhc_runtime_resume()
2016 clk_disable_unprepare(imx_data->clk_ahb); in sdhci_esdhc_runtime_resume()
2018 if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS) in sdhci_esdhc_runtime_resume()
2019 cpu_latency_qos_remove_request(&imx_data->pm_qos_req); in sdhci_esdhc_runtime_resume()
2032 .name = "sdhci-esdhc-imx",