702 static void sdr_clr_bits(void __iomem *reg, u32 bs)  in sdr_clr_bits()  function
937 	sdr_clr_bits(host->top_base + LOOP_TEST_CONTROL,  in msdc_new_tx_setting()
948 		sdr_clr_bits(host->top_base + LOOP_TEST_CONTROL,  in msdc_new_tx_setting()
978 		sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN);  in msdc_set_mclk()
988 	sdr_clr_bits(host->base + MSDC_INTEN, flags);  in msdc_set_mclk()
990 		sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_HS400_CK_MODE);  in msdc_set_mclk()
992 		sdr_clr_bits(host->base + MSDC_CFG,  in msdc_set_mclk()
1036 	sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN);  in msdc_set_mclk()
1172 		sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_PIO);  in msdc_cmd_prepare_raw_cmd()
1339 	sdr_clr_bits(host->base + MSDC_INTEN, cmd_ints_mask);  in msdc_cmd_done()
1557 		sdr_clr_bits(host->base + MSDC_INTEN, data_ints_mask);  in msdc_data_xfer_done()
1676 		sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ);  in __msdc_enable_sdio_irq()
1677 		sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE);  in __msdc_enable_sdio_irq()
1831 		sdr_clr_bits(host->base + SDC_ADV_CFG0, SDC_NEW_TX_EN);  in msdc_init_hw()
1836 		sdr_clr_bits(host->base + MSDC_NEW_RX_CFG, MSDC_NEW_RX_PATH_SEL);  in msdc_init_hw()
1859 		sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP);  in msdc_init_hw()
1860 		sdr_clr_bits(host->base + MSDC_PS, MSDC_PS_CDEN);  in msdc_init_hw()
1861 		sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_CDSC);  in msdc_init_hw()
1888 		sdr_clr_bits(host->base + SDC_FIFO_CFG,  in msdc_init_hw()
1890 		sdr_clr_bits(host->base + SDC_FIFO_CFG,  in msdc_init_hw()
1895 		sdr_clr_bits(host->base + MSDC_PATCH_BIT1, BIT(7));  in msdc_init_hw()
1914 		sdr_clr_bits(host->base + MSDC_PATCH_BIT2,  in msdc_init_hw()
1927 			sdr_clr_bits(host->top_base + EMMC_TOP_CONTROL,  in msdc_init_hw()
1957 		sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIO);  in msdc_init_hw()
1958 		sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ);  in msdc_init_hw()
1959 		sdr_clr_bits(host->base + SDC_ADV_CFG0, SDC_DAT1_IRQ_TRIGGER);  in msdc_init_hw()
1965 		sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE);  in msdc_init_hw()
1996 		sdr_clr_bits(host->base + MSDC_PS, MSDC_PS_CDEN);  in msdc_deinit_hw()
1997 		sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP);  in msdc_deinit_hw()
2230 	sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);  in msdc_tune_response()
2279 		sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);  in msdc_tune_response()
2326 		sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);  in hs400_tune_response()
2419 	sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);  in msdc_tune_together()
2448 		sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);  in msdc_tune_together()
2527 	sdr_clr_bits(host->base + MSDC_PATCH_BIT2, MSDC_PATCH_BIT2_CFGCRCSTS);  in msdc_prepare_hs400_tuning()
2545 		sdr_clr_bits(host->top_base + EMMC50_PAD_DS_TUNE,  in msdc_execute_hs400_tuning()
2549 		sdr_clr_bits(host->base + PAD_DS_TUNE, PAD_DS_TUNE_DLY2_SEL);  in msdc_execute_hs400_tuning()
2600 	sdr_clr_bits(host->base + EMMC_IOCON, 1);  in msdc_hw_reset()
2642 		sdr_clr_bits(host->base + CQHCI_SETTING, CQHCI_RD_CMD_WND_SEL);  in msdc_hs400_enhanced_strobe()
2643 		sdr_clr_bits(host->base + CQHCI_SETTING, CQHCI_WR_CMD_WND_SEL);  in msdc_hs400_enhanced_strobe()
2644 		sdr_clr_bits(host->base + EMMC51_CFG0, CMDQ_RDAT_CNT);  in msdc_hs400_enhanced_strobe()
2719 	sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INT_CMDQ);  in msdc_cqe_disable()
2721 	sdr_clr_bits(host->base + MSDC_PATCH_BIT1, MSDC_PB1_BUSY_CHECK_SEL);  in msdc_cqe_disable()
3163 		sdr_clr_bits(host->base + SDC_ADV_CFG0, SDC_NEW_TX_EN);  in msdc_restore_reg()
3167 		sdr_clr_bits(host->base + MSDC_NEW_RX_CFG, MSDC_NEW_RX_PATH_SEL);  in msdc_restore_reg()