Lines Matching +full:0 +full:x240a
23 STATE_IDLE = 0,
34 EVENT_CMD_COMPLETE = 0,
49 TRANS_MODE_PIO = 0,
128 * @cmd11_timer: Timer for SD3.0 voltage switch over scheme.
268 * Override fifo depth. If 0, autodetect it from the FIFOTH register,
283 #define DW_MMC_QUIRK_EXTENDED_TMOUT BIT(0)
287 #define DW_MMC_240A 0x240a
288 #define DW_MMC_280A 0x280a
290 #define SDMMC_CTRL 0x000
291 #define SDMMC_PWREN 0x004
292 #define SDMMC_CLKDIV 0x008
293 #define SDMMC_CLKSRC 0x00c
294 #define SDMMC_CLKENA 0x010
295 #define SDMMC_TMOUT 0x014
296 #define SDMMC_CTYPE 0x018
297 #define SDMMC_BLKSIZ 0x01c
298 #define SDMMC_BYTCNT 0x020
299 #define SDMMC_INTMASK 0x024
300 #define SDMMC_CMDARG 0x028
301 #define SDMMC_CMD 0x02c
302 #define SDMMC_RESP0 0x030
303 #define SDMMC_RESP1 0x034
304 #define SDMMC_RESP2 0x038
305 #define SDMMC_RESP3 0x03c
306 #define SDMMC_MINTSTS 0x040
307 #define SDMMC_RINTSTS 0x044
308 #define SDMMC_STATUS 0x048
309 #define SDMMC_FIFOTH 0x04c
310 #define SDMMC_CDETECT 0x050
311 #define SDMMC_WRTPRT 0x054
312 #define SDMMC_GPIO 0x058
313 #define SDMMC_TCBCNT 0x05c
314 #define SDMMC_TBBCNT 0x060
315 #define SDMMC_DEBNCE 0x064
316 #define SDMMC_USRID 0x068
317 #define SDMMC_VERID 0x06c
318 #define SDMMC_HCON 0x070
319 #define SDMMC_UHS_REG 0x074
320 #define SDMMC_RST_N 0x078
321 #define SDMMC_BMOD 0x080
322 #define SDMMC_PLDMND 0x084
323 #define SDMMC_DBADDR 0x088
324 #define SDMMC_IDSTS 0x08c
325 #define SDMMC_IDINTEN 0x090
326 #define SDMMC_DSCADDR 0x094
327 #define SDMMC_BUFADDR 0x098
328 #define SDMMC_CDTHRCTL 0x100
329 #define SDMMC_UHS_REG_EXT 0x108
330 #define SDMMC_DDR_REG 0x10c
331 #define SDMMC_ENABLE_SHIFT 0x110
336 #define SDMMC_DBADDRL 0x088
337 #define SDMMC_DBADDRU 0x08c
338 #define SDMMC_IDSTS64 0x090
339 #define SDMMC_IDINTEN64 0x094
340 #define SDMMC_DSCADDRL 0x098
341 #define SDMMC_DSCADDRU 0x09c
342 #define SDMMC_BUFADDRL 0x0A0
343 #define SDMMC_BUFADDRU 0x0A4
347 * Lower than 2.40a : data register offest is 0x100
349 #define DATA_OFFSET 0x100
350 #define DATA_240A_OFFSET 0x200
367 #define SDMMC_CTRL_RESET BIT(0)
370 #define SDMMC_CLKEN_ENABLE BIT(0)
373 #define SDMMC_TMOUT_DATA_MSK 0xFFFFFF00
374 #define SDMMC_TMOUT_RESP(n) ((n) & 0xFF)
375 #define SDMMC_TMOUT_RESP_MSK 0xFF
378 #define SDMMC_CTYPE_4BIT BIT(0)
379 #define SDMMC_CTYPE_1BIT 0
398 #define SDMMC_INT_CD BIT(0)
399 #define SDMMC_INT_ERROR 0xbfc2
417 #define SDMMC_CMD_INDX(n) ((n) & 0x1F)
419 #define SDMMC_GET_FCNT(x) (((x)>>17) & 0x1FFF)
423 #define SDMMC_SET_FIFOTH(m, r, t) (((m) & 0x7) << 28 | \
424 ((r) & 0xFFF) << 16 | \
425 ((t) & 0xFFF))
427 #define DMA_INTERFACE_IDMA (0x0)
428 #define DMA_INTERFACE_DWDMA (0x1)
429 #define DMA_INTERFACE_GDMA (0x2)
430 #define DMA_INTERFACE_NODMA (0x3)
431 #define SDMMC_GET_TRANS_MODE(x) (((x)>>16) & 0x3)
432 #define SDMMC_GET_SLOT_NUM(x) ((((x)>>1) & 0x1F) + 1)
433 #define SDMMC_GET_HDATA_WIDTH(x) (((x)>>7) & 0x7)
434 #define SDMMC_GET_ADDR_CONFIG(x) (((x)>>27) & 0x1)
442 #define SDMMC_IDMAC_INT_TI BIT(0)
446 #define SDMMC_IDMAC_SWRESET BIT(0)
448 #define SDMMC_RST_HWACTIVE 0x1
450 #define SDMMC_GET_VERID(x) ((x) & 0xFFFF)
452 #define SDMMC_SET_THLD(v, x) (((v) & 0xFFF) << 16 | (x))
454 #define SDMMC_CARD_RD_THR_EN BIT(0)
457 #define SDMMC_UHS_18V BIT(0)
461 #define SDMMC_ENABLE_PHASE BIT(0)
487 proxy[0] = mci_fifo_readl(addr); in mci_fifo_l_readq()
498 mci_fifo_writel(addr, proxy[0]); in mci_fifo_l_writeq()
575 #define DW_MMC_CARD_PRESENT 0