1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <linux/blk-crypto.h>
9 #include <linux/blk-crypto-profile.h>
10 #include <linux/mmc/host.h>
12 #include "cqhci-crypto.h"
14 /* Map from blk-crypto modes to CQHCI crypto algorithm IDs and key sizes */
28 	return mmc_from_crypto_profile(profile)->cqe_private;  in cqhci_host_from_crypto_profile()
33 				     int slot)  in cqhci_crypto_program_key()  argument
35 	u32 slot_offset = cq_host->crypto_cfg_register + slot * sizeof(*cfg);  in cqhci_crypto_program_key()
39 	cqhci_writel(cq_host, 0, slot_offset + 16 * sizeof(cfg->reg_val[0]));  in cqhci_crypto_program_key()
43 		cqhci_writel(cq_host, le32_to_cpu(cfg->reg_val[i]),  in cqhci_crypto_program_key()
44 			     slot_offset + i * sizeof(cfg->reg_val[0]));  in cqhci_crypto_program_key()
47 	cqhci_writel(cq_host, le32_to_cpu(cfg->reg_val[17]),  in cqhci_crypto_program_key()
48 		     slot_offset + 17 * sizeof(cfg->reg_val[0]));  in cqhci_crypto_program_key()
50 	cqhci_writel(cq_host, le32_to_cpu(cfg->reg_val[16]),  in cqhci_crypto_program_key()
51 		     slot_offset + 16 * sizeof(cfg->reg_val[0]));  in cqhci_crypto_program_key()
56 					unsigned int slot)  in cqhci_crypto_keyslot_program()  argument
61 		cq_host->crypto_cap_array;  in cqhci_crypto_keyslot_program()
63 			&cqhci_crypto_algs[key->crypto_cfg.crypto_mode];  in cqhci_crypto_keyslot_program()
64 	u8 data_unit_mask = key->crypto_cfg.data_unit_size / 512;  in cqhci_crypto_keyslot_program()
66 	int cap_idx = -1;  in cqhci_crypto_keyslot_program()
70 	for (i = 0; i < cq_host->crypto_capabilities.num_crypto_cap; i++) {  in cqhci_crypto_keyslot_program()
71 		if (ccap_array[i].algorithm_id == alg->alg &&  in cqhci_crypto_keyslot_program()
72 		    ccap_array[i].key_size == alg->key_size &&  in cqhci_crypto_keyslot_program()
79 		return -EOPNOTSUPP;  in cqhci_crypto_keyslot_program()
87 		memcpy(cfg.crypto_key, key->raw, key->size/2);  in cqhci_crypto_keyslot_program()
89 		       key->raw + key->size/2, key->size/2);  in cqhci_crypto_keyslot_program()
91 		memcpy(cfg.crypto_key, key->raw, key->size);  in cqhci_crypto_keyslot_program()
94 	cqhci_crypto_program_key(cq_host, &cfg, slot);  in cqhci_crypto_keyslot_program()
100 static int cqhci_crypto_clear_keyslot(struct cqhci_host *cq_host, int slot)  in cqhci_crypto_clear_keyslot()  argument
108 	cqhci_crypto_program_key(cq_host, &cfg, slot);  in cqhci_crypto_clear_keyslot()
114 				      unsigned int slot)  in cqhci_crypto_keyslot_evict()  argument
118 	return cqhci_crypto_clear_keyslot(cq_host, slot);  in cqhci_crypto_keyslot_evict()
125  * controller is runtime-suspended.  However, the CQE won't necessarily be
149  * cqhci_crypto_init - initialize CQHCI crypto support
155  * all keyslots, and enabling 128-bit task descriptors.
163 	struct mmc_host *mmc = cq_host->mmc;  in cqhci_crypto_init()  local
164 	struct device *dev = mmc_dev(mmc);  in cqhci_crypto_init()
165 	struct blk_crypto_profile *profile = &mmc->crypto_profile;  in cqhci_crypto_init()
168 	unsigned int slot;  in cqhci_crypto_init()  local
171 	if (!(mmc->caps2 & MMC_CAP2_CRYPTO) ||  in cqhci_crypto_init()
175 	if (cq_host->ops->uses_custom_crypto_profile)  in cqhci_crypto_init()
178 	cq_host->crypto_capabilities.reg_val =  in cqhci_crypto_init()
181 	cq_host->crypto_cfg_register =  in cqhci_crypto_init()
182 		(u32)cq_host->crypto_capabilities.config_array_ptr * 0x100;  in cqhci_crypto_init()
184 	cq_host->crypto_cap_array =  in cqhci_crypto_init()
185 		devm_kcalloc(dev, cq_host->crypto_capabilities.num_crypto_cap,  in cqhci_crypto_init()
186 			     sizeof(cq_host->crypto_cap_array[0]), GFP_KERNEL);  in cqhci_crypto_init()
187 	if (!cq_host->crypto_cap_array) {  in cqhci_crypto_init()
188 		err = -ENOMEM;  in cqhci_crypto_init()
197 		dev, profile, cq_host->crypto_capabilities.config_count + 1);  in cqhci_crypto_init()
201 	profile->ll_ops = cqhci_crypto_ops;  in cqhci_crypto_init()
202 	profile->dev = dev;  in cqhci_crypto_init()
205 	profile->max_dun_bytes_supported = 4;  in cqhci_crypto_init()
211 	for (cap_idx = 0; cap_idx < cq_host->crypto_capabilities.num_crypto_cap;  in cqhci_crypto_init()
213 		cq_host->crypto_cap_array[cap_idx].reg_val =  in cqhci_crypto_init()
218 					cq_host->crypto_cap_array[cap_idx]);  in cqhci_crypto_init()
221 		profile->modes_supported[blk_mode_num] |=  in cqhci_crypto_init()
222 			cq_host->crypto_cap_array[cap_idx].sdus_mask * 512;  in cqhci_crypto_init()
228 	for (slot = 0; slot < profile->num_slots; slot++)  in cqhci_crypto_init()
229 		profile->ll_ops.keyslot_evict(profile, NULL, slot);  in cqhci_crypto_init()
231 	/* CQHCI crypto requires the use of 128-bit task descriptors. */  in cqhci_crypto_init()
232 	cq_host->caps |= CQHCI_TASK_DESC_SZ_128;  in cqhci_crypto_init()
237 	mmc->caps2 &= ~MMC_CAP2_CRYPTO;  in cqhci_crypto_init()