Lines Matching +full:host +full:- +full:only

1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
3  * Copyright (c) 2003-2022, Intel Corporation. All rights reserved.
53 #define MEI_DEV_ID_LPT_W      0x8D3A  /* Lynx Point - Wellsburg */
126 /* Host Firmware Status Registers in PCI Config Space */
132 #  define PCI_CFG_HFS_2_PM_CMOFF_TO_CMX_ERROR 0x1000000 /* CMoff->CMx wake after an error */
146 /* H_CB_WW - Host Circular Buffer (CB) Write Window register */
148 /* H_CSR - Host Control Status register */
150 /* ME_CB_RW - ME Circular Buffer Read Window register (read only) */
152 /* ME_CSR_HA - ME Control Status Host Access register (read only) */
154 /* H_HGC_CSR - PGI register */
156 /* H_D0I3C - D0I3 Control  */
164 /* register bits of H_CSR (Host Control Status register) */
165 /* Host Circular Buffer Depth - maximum number of 32-bit entries in CB */
167 /* Host Circular Buffer Write Pointer */
169 /* Host Circular Buffer Read Pointer */
171 /* Host Reset */
173 /* Host Ready */
175 /* Host Interrupt Generate */
177 /* Host Interrupt Status */
179 /* Host Interrupt Enable */
181 /* Host D0I3 Interrupt Enable */
183 /* Host D0I3 Interrupt Status */
190 /* register bits of ME_CSR_HA (ME Control Status Host Access register) */
191 /* ME CB (Circular Buffer) Depth HRA (Host Read Access) - host read only
194 /* ME CB Write Pointer HRA - host read only access to ME_CBWP */
196 /* ME CB Read Pointer HRA - host read only access to ME_CBRP */
198 /* ME Power Gate Isolation Capability HRA  - host ready only access */
200 /* ME Reset HRA - host read only access to ME_RST */
202 /* ME Ready HRA - host read only access to ME_RDY */
204 /* ME Interrupt Generate HRA - host read only access to ME_IG */
206 /* ME Interrupt Status HRA - host read only access to ME_IS */
208 /* ME Interrupt Enable HRA - host read only access to ME_IE */