Lines Matching +full:lock +full:- +full:offset
1 // SPDX-License-Identifier: GPL-2.0
41 spinlock_t lock; member
49 int ret = -EINVAL; in pci1xxxx_gpio_get_direction()
51 data = readl(priv->reg_base + INP_EN_OFFSET(nr)); in pci1xxxx_gpio_get_direction()
55 data = readl(priv->reg_base + OUT_EN_OFFSET(nr)); in pci1xxxx_gpio_get_direction()
81 spin_lock_irqsave(&priv->lock, flags); in pci1xxxx_gpio_direction_input()
82 pci1xxx_assign_bit(priv->reg_base, INP_EN_OFFSET(nr), (nr % 32), true); in pci1xxxx_gpio_direction_input()
83 pci1xxx_assign_bit(priv->reg_base, OUT_EN_OFFSET(nr), (nr % 32), false); in pci1xxxx_gpio_direction_input()
84 spin_unlock_irqrestore(&priv->lock, flags); in pci1xxxx_gpio_direction_input()
93 return (readl(priv->reg_base + INP_OFFSET(nr)) >> (nr % 32)) & 1; in pci1xxxx_gpio_get()
103 spin_lock_irqsave(&priv->lock, flags); in pci1xxxx_gpio_direction_output()
104 pci1xxx_assign_bit(priv->reg_base, INP_EN_OFFSET(nr), (nr % 32), false); in pci1xxxx_gpio_direction_output()
105 pci1xxx_assign_bit(priv->reg_base, OUT_EN_OFFSET(nr), (nr % 32), true); in pci1xxxx_gpio_direction_output()
106 data = readl(priv->reg_base + OUT_OFFSET(nr)); in pci1xxxx_gpio_direction_output()
111 writel(data, priv->reg_base + OUT_OFFSET(nr)); in pci1xxxx_gpio_direction_output()
112 spin_unlock_irqrestore(&priv->lock, flags); in pci1xxxx_gpio_direction_output()
123 spin_lock_irqsave(&priv->lock, flags); in pci1xxxx_gpio_set()
124 pci1xxx_assign_bit(priv->reg_base, OUT_OFFSET(nr), (nr % 32), val); in pci1xxxx_gpio_set()
125 spin_unlock_irqrestore(&priv->lock, flags); in pci1xxxx_gpio_set()
128 static int pci1xxxx_gpio_set_config(struct gpio_chip *gpio, unsigned int offset, in pci1xxxx_gpio_set_config() argument
135 spin_lock_irqsave(&priv->lock, flags); in pci1xxxx_gpio_set_config()
138 pci1xxx_assign_bit(priv->reg_base, PULLUP_OFFSET(offset), (offset % 32), true); in pci1xxxx_gpio_set_config()
141 pci1xxx_assign_bit(priv->reg_base, PULLDOWN_OFFSET(offset), (offset % 32), true); in pci1xxxx_gpio_set_config()
144 pci1xxx_assign_bit(priv->reg_base, PULLUP_OFFSET(offset), (offset % 32), false); in pci1xxxx_gpio_set_config()
145 pci1xxx_assign_bit(priv->reg_base, PULLDOWN_OFFSET(offset), (offset % 32), false); in pci1xxxx_gpio_set_config()
148 pci1xxx_assign_bit(priv->reg_base, OPENDRAIN_OFFSET(offset), (offset % 32), true); in pci1xxxx_gpio_set_config()
151 pci1xxx_assign_bit(priv->reg_base, OPENDRAIN_OFFSET(offset), (offset % 32), false); in pci1xxxx_gpio_set_config()
154 ret = -ENOTSUPP; in pci1xxxx_gpio_set_config()
157 spin_unlock_irqrestore(&priv->lock, flags); in pci1xxxx_gpio_set_config()
169 spin_lock_irqsave(&priv->lock, flags); in pci1xxxx_gpio_irq_ack()
170 pci1xxx_assign_bit(priv->reg_base, INTR_STAT_OFFSET(gpio), (gpio % 32), true); in pci1xxxx_gpio_irq_ack()
171 spin_unlock_irqrestore(&priv->lock, flags); in pci1xxxx_gpio_irq_ack()
183 spin_lock_irqsave(&priv->lock, flags); in pci1xxxx_gpio_irq_set_mask()
184 pci1xxx_assign_bit(priv->reg_base, INTR_MASK_OFFSET(gpio), (gpio % 32), set); in pci1xxxx_gpio_irq_set_mask()
185 spin_unlock_irqrestore(&priv->lock, flags); in pci1xxxx_gpio_irq_set_mask()
208 pci1xxx_assign_bit(priv->reg_base, INTR_HI_TO_LO_EDGE_CONFIG(gpio), in pci1xxxx_gpio_set_type()
210 pci1xxx_assign_bit(priv->reg_base, MODE_OFFSET(gpio), in pci1xxxx_gpio_set_type()
214 pci1xxx_assign_bit(priv->reg_base, INTR_HI_TO_LO_EDGE_CONFIG(gpio), in pci1xxxx_gpio_set_type()
219 pci1xxx_assign_bit(priv->reg_base, INTR_LO_TO_HI_EDGE_CONFIG(gpio), in pci1xxxx_gpio_set_type()
221 pci1xxx_assign_bit(priv->reg_base, MODE_OFFSET(gpio), bitpos, in pci1xxxx_gpio_set_type()
225 pci1xxx_assign_bit(priv->reg_base, INTR_LO_TO_HI_EDGE_CONFIG(gpio), in pci1xxxx_gpio_set_type()
230 pci1xxx_assign_bit(priv->reg_base, INTR_LEVEL_CONFIG_OFFSET(gpio), in pci1xxxx_gpio_set_type()
232 pci1xxx_assign_bit(priv->reg_base, INTR_LEVEL_MASK_OFFSET(gpio), in pci1xxxx_gpio_set_type()
234 pci1xxx_assign_bit(priv->reg_base, MODE_OFFSET(gpio), bitpos, in pci1xxxx_gpio_set_type()
240 pci1xxx_assign_bit(priv->reg_base, INTR_LEVEL_CONFIG_OFFSET(gpio), in pci1xxxx_gpio_set_type()
242 pci1xxx_assign_bit(priv->reg_base, INTR_LEVEL_MASK_OFFSET(gpio), in pci1xxxx_gpio_set_type()
244 pci1xxx_assign_bit(priv->reg_base, MODE_OFFSET(gpio), bitpos, in pci1xxxx_gpio_set_type()
250 pci1xxx_assign_bit(priv->reg_base, INTR_LEVEL_MASK_OFFSET(gpio), bitpos, true); in pci1xxxx_gpio_set_type()
258 struct gpio_chip *gc = &priv->gpio; in pci1xxxx_gpio_irq_handler()
265 spin_lock_irqsave(&priv->lock, flags); in pci1xxxx_gpio_irq_handler()
266 pci1xxx_assign_bit(priv->reg_base, PIO_GLOBAL_CONFIG_OFFSET, 16, true); in pci1xxxx_gpio_irq_handler()
267 spin_unlock_irqrestore(&priv->lock, flags); in pci1xxxx_gpio_irq_handler()
269 spin_lock_irqsave(&priv->lock, flags); in pci1xxxx_gpio_irq_handler()
270 int_status = readl(priv->reg_base + INTR_STATUS_OFFSET(gpiobank)); in pci1xxxx_gpio_irq_handler()
271 spin_unlock_irqrestore(&priv->lock, flags); in pci1xxxx_gpio_irq_handler()
279 spin_lock_irqsave(&priv->lock, flags); in pci1xxxx_gpio_irq_handler()
280 writel(BIT(bit), priv->reg_base + INTR_STATUS_OFFSET(gpiobank)); in pci1xxxx_gpio_irq_handler()
281 spin_unlock_irqrestore(&priv->lock, flags); in pci1xxxx_gpio_irq_handler()
282 irq = irq_find_mapping(gc->irq.domain, (bit + (gpiobank * 32))); in pci1xxxx_gpio_irq_handler()
286 spin_lock_irqsave(&priv->lock, flags); in pci1xxxx_gpio_irq_handler()
287 pci1xxx_assign_bit(priv->reg_base, PIO_GLOBAL_CONFIG_OFFSET, 16, false); in pci1xxxx_gpio_irq_handler()
288 spin_unlock_irqrestore(&priv->lock, flags); in pci1xxxx_gpio_irq_handler()
308 spin_lock_irqsave(&priv->lock, flags); in pci1xxxx_gpio_suspend()
309 pci1xxx_assign_bit(priv->reg_base, PIO_GLOBAL_CONFIG_OFFSET, in pci1xxxx_gpio_suspend()
311 pci1xxx_assign_bit(priv->reg_base, PIO_GLOBAL_CONFIG_OFFSET, in pci1xxxx_gpio_suspend()
313 pci1xxx_assign_bit(priv->reg_base, PERI_GEN_RESET, 16, true); in pci1xxxx_gpio_suspend()
314 spin_unlock_irqrestore(&priv->lock, flags); in pci1xxxx_gpio_suspend()
324 spin_lock_irqsave(&priv->lock, flags); in pci1xxxx_gpio_resume()
325 pci1xxx_assign_bit(priv->reg_base, PIO_GLOBAL_CONFIG_OFFSET, in pci1xxxx_gpio_resume()
327 pci1xxx_assign_bit(priv->reg_base, PIO_GLOBAL_CONFIG_OFFSET, in pci1xxxx_gpio_resume()
329 pci1xxx_assign_bit(priv->reg_base, PERI_GEN_RESET, 16, false); in pci1xxxx_gpio_resume()
330 spin_unlock_irqrestore(&priv->lock, flags); in pci1xxxx_gpio_resume()
337 struct gpio_chip *gchip = &priv->gpio; in pci1xxxx_gpio_setup()
341 gchip->label = dev_name(&priv->aux_dev->dev); in pci1xxxx_gpio_setup()
342 gchip->parent = &priv->aux_dev->dev; in pci1xxxx_gpio_setup()
343 gchip->owner = THIS_MODULE; in pci1xxxx_gpio_setup()
344 gchip->direction_input = pci1xxxx_gpio_direction_input; in pci1xxxx_gpio_setup()
345 gchip->direction_output = pci1xxxx_gpio_direction_output; in pci1xxxx_gpio_setup()
346 gchip->get_direction = pci1xxxx_gpio_get_direction; in pci1xxxx_gpio_setup()
347 gchip->get = pci1xxxx_gpio_get; in pci1xxxx_gpio_setup()
348 gchip->set = pci1xxxx_gpio_set; in pci1xxxx_gpio_setup()
349 gchip->set_config = pci1xxxx_gpio_set_config; in pci1xxxx_gpio_setup()
350 gchip->dbg_show = NULL; in pci1xxxx_gpio_setup()
351 gchip->base = -1; in pci1xxxx_gpio_setup()
352 gchip->ngpio = PCI1XXXX_NR_PINS; in pci1xxxx_gpio_setup()
353 gchip->can_sleep = false; in pci1xxxx_gpio_setup()
355 retval = devm_request_threaded_irq(&priv->aux_dev->dev, irq, in pci1xxxx_gpio_setup()
362 girq = &priv->gpio.irq; in pci1xxxx_gpio_setup()
364 girq->parent_handler = NULL; in pci1xxxx_gpio_setup()
365 girq->num_parents = 0; in pci1xxxx_gpio_setup()
366 girq->parents = NULL; in pci1xxxx_gpio_setup()
367 girq->default_type = IRQ_TYPE_NONE; in pci1xxxx_gpio_setup()
368 girq->handler = handle_bad_irq; in pci1xxxx_gpio_setup()
385 pdata = &aux_dev_wrapper->gp_aux_data; in pci1xxxx_gpio_probe()
388 return -EINVAL; in pci1xxxx_gpio_probe()
390 priv = devm_kzalloc(&aux_dev->dev, sizeof(struct pci1xxxx_gpio), GFP_KERNEL); in pci1xxxx_gpio_probe()
392 return -ENOMEM; in pci1xxxx_gpio_probe()
394 spin_lock_init(&priv->lock); in pci1xxxx_gpio_probe()
395 priv->aux_dev = aux_dev; in pci1xxxx_gpio_probe()
397 if (!devm_request_mem_region(&aux_dev->dev, pdata->region_start, 0x800, aux_dev->name)) in pci1xxxx_gpio_probe()
398 return -EBUSY; in pci1xxxx_gpio_probe()
400 priv->reg_base = devm_ioremap(&aux_dev->dev, pdata->region_start, 0x800); in pci1xxxx_gpio_probe()
401 if (!priv->reg_base) in pci1xxxx_gpio_probe()
402 return -ENOMEM; in pci1xxxx_gpio_probe()
404 writel(0x0264, (priv->reg_base + 0x400 + 0xF0)); in pci1xxxx_gpio_probe()
406 retval = pci1xxxx_gpio_setup(priv, pdata->irq_num); in pci1xxxx_gpio_probe()
411 dev_set_drvdata(&aux_dev->dev, priv); in pci1xxxx_gpio_probe()
413 return devm_gpiochip_add_data(&aux_dev->dev, &priv->gpio, priv); in pci1xxxx_gpio_probe()