24 #define PCI_VENDOR_ID_KEBA		0xCEBA
25 #define PCI_DEVICE_ID_KEBA_CP035	0x2706
26 #define PCI_DEVICE_ID_KEBA_CP505	0x2703
27 #define PCI_DEVICE_ID_KEBA_CP520	0x2696
29 #define CP500_SYS_BAR		0
32 /* BAR 0 registers */
33 #define CP500_VERSION_REG	0x00
34 #define CP500_RECONFIG_REG	0x11	/* upper 8-bits of STARTUP register */
35 #define CP500_PRESENT_REG	0x20
36 #define CP500_AXI_REG		0x40
39 #define CP500_BUILD_TEST        0x8000	/* FPGA test version */
42 #define CP500_RECFG_REQ		0x01	/* reconfigure FPGA on next reset */
45 #define CP500_PRESENT_FAN0	0x01
57 #define CP500_EEPROM_DA_OFFSET		0x016F
58 #define CP500_EEPROM_DA_ESC_TYPE_MASK	0x01
59 #define CP500_EEPROM_ESC_LAN9252	0x00
60 #define CP500_EEPROM_ESC_ET1100		0x01
62 #define CP500_EEPROM_CPU_OFFSET		0
97 	.startup   = { 0x0000, SZ_4K },
98 	.spi       = { 0x1000, SZ_4K },
99 	.i2c       = { 0x4000, SZ_4K },
100 	.fan       = { 0x9000, SZ_4K },
101 	.batt      = { 0xA000, SZ_4K },
102 	.uart0_rfb = { 0xB000, SZ_4K, CP500_RFB_UART_MSIX },
103 	.uart2_si1 = { 0xD000, SZ_4K, CP500_SI1_UART_MSIX },
108 	.startup   = { 0x0000, SZ_4K },
109 	.spi       = { 0x4000, SZ_4K },
110 	.i2c       = { 0x5000, SZ_4K },
111 	.fan       = { 0x9000, SZ_4K },
112 	.batt      = { 0xA000, SZ_4K },
113 	.uart0_rfb = { 0xB000, SZ_4K, CP500_RFB_UART_MSIX },
114 	.uart2_si1 = { 0xD000, SZ_4K, CP500_SI1_UART_MSIX },
119 	.startup   = { 0x0000, SZ_4K },
120 	.spi       = { 0x4000, SZ_4K },
121 	.i2c       = { 0x5000, SZ_4K },
122 	.fan       = { 0x8000, SZ_4K },
123 	.batt      = { 0x9000, SZ_4K },
124 	.uart0_rfb = { 0xC000, SZ_4K, CP500_RFB_UART_MSIX },
125 	.uart1_dbg = { 0xD000, SZ_4K, CP500_DEBUG_UART_MSIX },
167 #define CP500_EEPROM_ADDR	0x50
170 		I2C_BOARD_INFO("emc1403", 0x4c),
190 	{	/* extension module 0 EEPROM (optional) */
209 		.offset     = 0,
210 		.mask_flags = 0
230 		.chip_select   = 0,
287 		keep_cfg = 0;  in keep_cfg_show()
298 	if (kstrtoul(buf, 10, &keep_cfg) < 0)  in keep_cfg_store()
306 	 * writing a "0" into the "keep_cfg" attribute. After a reset/reboot th  in keep_cfg_store()
310 		iowrite8(0, cp500->system_startup_addr + CP500_RECONFIG_REG);  in keep_cfg_store()
343 	cp500->i2c->auxdev.id = 0;  in cp500_register_i2c()
373 	return 0;  in cp500_register_i2c()
394 		cp500_spi_info[0].platform_data = &cp500_w25q32;  in cp500_register_spi()
401 	cp500->spi->auxdev.id = 0;  in cp500_register_spi()
431 	return 0;  in cp500_register_spi()
451 	cp500->fan->auxdev.id = 0;  in cp500_register_fan()
479 	return 0;  in cp500_register_fan()
499 	cp500->batt->auxdev.id = 0;  in cp500_register_batt()
527 	return 0;  in cp500_register_batt()
549 	(*uart)->auxdev.id = 0;  in cp500_register_uart()
576 	return 0;  in cp500_register_uart()
590 	return 0;  in cp500_nvmem_read()
604 	return 0;  in cp500_nvmem_write()
654 	return 0;  in cp500_nvmem_register()
685 		return 0;  in cp500_nvmem_match()
690 	return 0;  in cp500_nvmem_match()
828 	dev_err(&cp500->pci_dev->dev, "AXI response error at 0x%08x\n",  in cp500_axi_handler()
841 		ret = request_irq(axi_irq, cp500_axi_handler, 0,  in cp500_enable()
843 		if (ret != 0) {  in cp500_enable()
850 	return 0;  in cp500_enable()
914 	cp500->version.major = (cp500_vers & 0xff);  in cp500_probe()
915 	cp500->version.minor = (cp500_vers >> 8) & 0xff;  in cp500_probe()
916 	cp500->version.build = (cp500_vers >> 16) & 0xffff;  in cp500_probe()
925 	if (ret != 0)  in cp500_probe()
929 	if (ret != 0)  in cp500_probe()
934 	return 0;  in cp500_probe()
962 	pci_set_drvdata(pci_dev, 0);  in cp500_remove()