1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* Driver for Realtek PCI-Express card reader
4  * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
43 		drive_sel = pcr->sd30_drive_sel_3v3;  in rts5264_fill_driving()
46 		drive_sel = pcr->sd30_drive_sel_1v8;  in rts5264_fill_driving()
66 		rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3,  in rts5264_force_power_down()
72 		rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, 0x01, 0x00);  in rts5264_force_power_down()
78 		rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, 0x01, 0x01);  in rts5264_force_power_down()
79 		rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3,  in rts5264_force_power_down()
155 	struct rtsx_cr_option *option = &pcr->option;  in rts5264_card_power_on()
157 	if (option->ocp_en)  in rts5264_card_power_on()
189 	if (pcr->extra_caps & EXTRA_CAPS_SD_SDR50 ||  in rts5264_card_power_on()
190 	    pcr->extra_caps & EXTRA_CAPS_SD_SDR104)  in rts5264_card_power_on()
219 		return -EINVAL;  in rts5264_switch_output_voltage()
252 	if (pcr->option.ocp_en)  in rts5264_card_power_off()
314 	struct rtsx_cr_option *option = &pcr->option;  in rts5264_init_ocp()
316 	if (option->ocp_en) {  in rts5264_init_ocp()
320 			RTS5264_LDO1_OCP_THD_MASK, option->sd_800mA_ocp_thd);  in rts5264_init_ocp()
341 		val = pcr->hw_param.ocp_glitch;  in rts5264_init_ocp()
393 	if (!pcr->option.ocp_en)  in rts5264_process_ocp()
396 	rtsx_pci_get_ocpstat(pcr, &pcr->ocp_stat);  in rts5264_process_ocp()
397 	rts5264_get_ocpstat2(pcr, &pcr->ocp_stat2);  in rts5264_process_ocp()
398 	rts5264_get_ovpstat(pcr, &pcr->ovp_stat);  in rts5264_process_ocp()
400 	if ((pcr->ocp_stat & (SD_OC_NOW | SD_OC_EVER | SDVIO_OC_NOW | SDVIO_OC_EVER)) ||  in rts5264_process_ocp()
401 			(pcr->ocp_stat2 & (SD_VDD3_OC_NOW | SD_VDD3_OC_EVER)) ||  in rts5264_process_ocp()
402 			(pcr->ovp_stat & (RTS5264_OVP_NOW | RTS5264_OVP_EVER))) {  in rts5264_process_ocp()
406 		pcr->ocp_stat = 0;  in rts5264_process_ocp()
407 		pcr->ocp_stat2 = 0;  in rts5264_process_ocp()
408 		pcr->ovp_stat = 0;  in rts5264_process_ocp()
414 	struct pci_dev *pdev = pcr->pci;  in rts5264_init_from_hw()
474 	pcr->rtd3_en = rts5264_reg_to_rtd3(lval2);  in rts5264_init_from_hw()
477 		pcr->flags |= PCR_REVERSE_SOCKET;  in rts5264_init_from_hw()
482 	pcr->aspm_en = rts5264_reg_to_aspm(lval1);  in rts5264_init_from_hw()
483 	pcr->sd30_drive_sel_1v8 = rts5264_reg_to_sd30_drive_sel_1v8(lval1);  in rts5264_init_from_hw()
484 	pcr->sd30_drive_sel_3v3 = rts5264_reg_to_sd30_drive_sel_3v3(lval1);  in rts5264_init_from_hw()
504 	struct rtsx_cr_option *option = &pcr->option;  in rts5264_init_from_cfg()
514 	if (option->ltr_en) {  in rts5264_init_from_cfg()
515 		if (option->ltr_enabled)  in rts5264_init_from_cfg()
516 			rtsx_set_ltr_latency(pcr, option->ltr_active_latency);  in rts5264_init_from_cfg()
522 	struct rtsx_cr_option *option = &pcr->option;  in rts5264_extra_init_hw()
569 	if (pcr->flags & PCR_REVERSE_SOCKET)  in rts5264_extra_init_hw()
578 	if (option->force_clkreq_0)  in rts5264_extra_init_hw()
590 	if (pcr->rtd3_en) {  in rts5264_extra_init_hw()
591 		rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, 0x01, 0x00);  in rts5264_extra_init_hw()
595 		rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, 0x01, 0x00);  in rts5264_extra_init_hw()
599 	rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, D3_DELINK_MODE_EN, 0x00);  in rts5264_extra_init_hw()
613 	if (pcr->aspm_enabled == enable)  in rts5264_enable_aspm()
616 	val |= (pcr->aspm_en & 0x02);  in rts5264_enable_aspm()
618 	pcie_capability_clear_and_set_word(pcr->pci, PCI_EXP_LNKCTL,  in rts5264_enable_aspm()
619 					   PCI_EXP_LNKCTL_ASPMC, pcr->aspm_en);  in rts5264_enable_aspm()
620 	pcr->aspm_enabled = enable;  in rts5264_enable_aspm()
628 	if (pcr->aspm_enabled == enable)  in rts5264_disable_aspm()
631 	pcie_capability_clear_and_set_word(pcr->pci, PCI_EXP_LNKCTL,  in rts5264_disable_aspm()
636 	pcr->aspm_enabled = enable;  in rts5264_disable_aspm()
649 	struct rtsx_cr_option *option = &(pcr->option);  in rts5264_set_l1off_cfg_sub_d0()
662 			val = option->ltr_l1off_snooze_sspwrgate;  in rts5264_set_l1off_cfg_sub_d0()
666 			val = option->ltr_l1off_sspwrgate;  in rts5264_set_l1off_cfg_sub_d0()
703 	return ((depth > 1) ? (depth - 1) : depth);  in double_ssc_depth()
737 	pcr_dbg(pcr, "Internal SSC clock: %dMHz (cur_clock = %d)\n",  in rts5264_pci_switch_clock()
738 		clk, pcr->cur_clock);  in rts5264_pci_switch_clock()
740 	if (clk == pcr->cur_clock)  in rts5264_pci_switch_clock()
743 	if (pcr->ops->conv_clk_and_div_n)  in rts5264_pci_switch_clock()
744 		n = pcr->ops->conv_clk_and_div_n(clk, CLK_TO_DIV_N);  in rts5264_pci_switch_clock()
746 		n = clk - 4;  in rts5264_pci_switch_clock()
748 		return -EINVAL;  in rts5264_pci_switch_clock()
755 	while ((n < MIN_DIV_N_PCR - 4) && (div < CLK_DIV_8)) {  in rts5264_pci_switch_clock()
756 		if (pcr->ops->conv_clk_and_div_n) {  in rts5264_pci_switch_clock()
757 			int dbl_clk = pcr->ops->conv_clk_and_div_n(n,  in rts5264_pci_switch_clock()
759 			n = pcr->ops->conv_clk_and_div_n(dbl_clk,  in rts5264_pci_switch_clock()
762 			n = (n + 4) * 2 - 4;  in rts5264_pci_switch_clock()
767 	n = (n / 2) - 1;  in rts5264_pci_switch_clock()
777 				ssc_depth -= 1;  in rts5264_pci_switch_clock()
782 				ssc_depth -= 2;  in rts5264_pci_switch_clock()
787 				ssc_depth -= 3;  in rts5264_pci_switch_clock()
831 	/* Wait SSC clock stable */  in rts5264_pci_switch_clock()
837 	pcr->cur_clock = clk;  in rts5264_pci_switch_clock()
843 	struct rtsx_cr_option *option = &pcr->option;  in rts5264_init_params()
844 	struct rtsx_hw_param *hw_param = &pcr->hw_param;  in rts5264_init_params()
847 	pcr->extra_caps = EXTRA_CAPS_SD_SDR50 | EXTRA_CAPS_SD_SDR104;  in rts5264_init_params()
848 	pcr->extra_caps |= EXTRA_CAPS_NO_MMC;  in rts5264_init_params()
851 		pcr->extra_caps |= EXTRA_CAPS_SD_EXPRESS;  in rts5264_init_params()
852 	pcr->num_slots = 1;  in rts5264_init_params()
853 	pcr->ops = &rts5264_pcr_ops;  in rts5264_init_params()
855 	pcr->flags = 0;  in rts5264_init_params()
856 	pcr->card_drive_sel = RTSX_CARD_DRIVE_DEFAULT;  in rts5264_init_params()
857 	pcr->sd30_drive_sel_1v8 = 0x00;  in rts5264_init_params()
858 	pcr->sd30_drive_sel_3v3 = 0x00;  in rts5264_init_params()
859 	pcr->aspm_en = ASPM_L1_EN;  in rts5264_init_params()
860 	pcr->aspm_mode = ASPM_MODE_REG;  in rts5264_init_params()
861 	pcr->tx_initial_phase = SET_CLOCK_PHASE(24, 24, 11);  in rts5264_init_params()
862 	pcr->rx_initial_phase = SET_CLOCK_PHASE(24, 6, 5);  in rts5264_init_params()
864 	pcr->ic_version = rts5264_get_ic_version(pcr);  in rts5264_init_params()
865 	pcr->sd_pull_ctl_enable_tbl = rts5264_sd_pull_ctl_enable_tbl;  in rts5264_init_params()
866 	pcr->sd_pull_ctl_disable_tbl = rts5264_sd_pull_ctl_disable_tbl;  in rts5264_init_params()
868 	pcr->reg_pm_ctrl3 = RTS5264_AUTOLOAD_CFG3;  in rts5264_init_params()
870 	option->dev_flags = (LTR_L1SS_PWR_GATE_CHECK_CARD_EN  in rts5264_init_params()
872 	option->ltr_en = true;  in rts5264_init_params()
875 	option->ltr_active_latency = LTR_ACTIVE_LATENCY_DEF;  in rts5264_init_params()
876 	option->ltr_idle_latency = LTR_IDLE_LATENCY_DEF;  in rts5264_init_params()
877 	option->ltr_l1off_latency = LTR_L1OFF_LATENCY_DEF;  in rts5264_init_params()
878 	option->l1_snooze_delay = L1_SNOOZE_DELAY_DEF;  in rts5264_init_params()
879 	option->ltr_l1off_sspwrgate = 0x7F;  in rts5264_init_params()
880 	option->ltr_l1off_snooze_sspwrgate = 0x78;  in rts5264_init_params()
882 	option->ocp_en = 1;  in rts5264_init_params()
883 	hw_param->interrupt_en |= (SD_OC_INT_EN | SD_OVP_INT_EN);  in rts5264_init_params()
884 	hw_param->ocp_glitch =  SD_OCP_GLITCH_800U | SDVIO_OCP_GLITCH_800U;  in rts5264_init_params()
885 	option->sd_800mA_ocp_thd =  RTS5264_LDO1_OCP_THD_1150;  in rts5264_init_params()