1 // SPDX-License-Identifier: GPL-2.0-only
3  *  lpc_ich.c - LPC interface for Intel ICH
7  *  Power Management, System Management, GPIO, RTC, and LPC
12  *  Copyright (c) 2017, 2021-2022 Intel Corporation
14  *  Author: Aaron Sierra <asierra@xes-inc.com>
18  *	document number 290655-003, 290677-014: 82801AA (ICH), 82801AB (ICHO)
19  *	document number 290687-002, 298242-027: 82801BA (ICH2)
20  *	document number 290733-003, 290739-013: 82801CA (ICH3-S)
21  *	document number 290716-001, 290718-007: 82801CAM (ICH3-M)
22  *	document number 290744-001, 290745-025: 82801DB (ICH4)
23  *	document number 252337-001, 252663-008: 82801DBM (ICH4-M)
24  *	document number 273599-001, 273645-002: 82801E (C-ICH)
25  *	document number 252516-001, 252517-028: 82801EB (ICH5), 82801ER (ICH5R)
26  *	document number 300641-004, 300884-013: 6300ESB
27  *	document number 301473-002, 301474-026: 82801F (ICH6)
28  *	document number 313082-001, 313075-006: 631xESB, 632xESB
29  *	document number 307013-003, 307014-024: 82801G (ICH7)
30  *	document number 322896-001, 322897-001: NM10
31  *	document number 313056-003, 313057-017: 82801H (ICH8)
32  *	document number 316972-004, 316973-012: 82801I (ICH9)
33  *	document number 319973-002, 319974-002: 82801J (ICH10)
34  *	document number 322169-001, 322170-003: 5 Series, 3400 Series (PCH)
35  *	document number 320066-003, 320257-008: EP80597 (IICH)
36  *	document number 324645-001, 324646-001: Cougar Point (CPT)
90 	/* ACPI - TCO */
94 	/* ACPI - SMI */
109 	/* ACPI - GPE0 */
192 		.name = "apollolake-pinctrl",
199 		.name = "apollolake-pinctrl",
206 		.name = "apollolake-pinctrl",
213 		.name = "apollolake-pinctrl",
257 		.name = "denverton-pinctrl",
274 	.name = "intel-spi",
285 	LPC_ICH2M,	/* ICH2-M */
286 	LPC_ICH3,	/* ICH3-S */
287 	LPC_ICH3M,	/* ICH3-M */
289 	LPC_ICH4M,	/* ICH4-M */
290 	LPC_CICH,	/* C-ICH */
294 	LPC_ICH6M,	/* ICH6-M */
299 	LPC_ICH7M,	/* ICH7-M & ICH7-U */
300 	LPC_ICH7MDH,	/* ICH7-M DH */
306 	LPC_ICH8ME,	/* ICH8M-E */
312 	LPC_ICH9ME,	/* ICH9M-E */
340 	LPC_LPT_LP,	/* Lynx Point-LP */
345 	LPC_WPT_LP,	/* Wildcat Point-LP */
351 	LPC_GLK,	/* Gemini Lake SoC */
382 		.name = "ICH2-M",
386 		.name = "ICH3-S",
390 		.name = "ICH3-M",
398 		.name = "ICH4-M",
402 		.name = "C-ICH",
419 		.name = "ICH6-M",
444 		.name = "ICH7-M or ICH7-U",
449 		.name = "ICH7-M DH",
479 		.name = "ICH8M-E",
509 		.name = "ICH9M-E",
701 		.name = "Gemini Lake SoC",
962 	if (priv->abase_save >= 0) {  in lpc_ich_restore_config_space()
963 		pci_write_config_byte(dev, priv->abase, priv->abase_save);  in lpc_ich_restore_config_space()
964 		priv->abase_save = -1;  in lpc_ich_restore_config_space()
967 	if (priv->actrl_pbase_save >= 0) {  in lpc_ich_restore_config_space()
968 		pci_write_config_byte(dev, priv->actrl_pbase,  in lpc_ich_restore_config_space()
969 			priv->actrl_pbase_save);  in lpc_ich_restore_config_space()
970 		priv->actrl_pbase_save = -1;  in lpc_ich_restore_config_space()
973 	if (priv->gctrl_save >= 0) {  in lpc_ich_restore_config_space()
974 		pci_write_config_byte(dev, priv->gctrl, priv->gctrl_save);  in lpc_ich_restore_config_space()
975 		priv->gctrl_save = -1;  in lpc_ich_restore_config_space()
984 	switch (lpc_chipset_info[priv->chipset].iTCO_version) {  in lpc_ich_enable_acpi_space()
990 		pci_read_config_byte(dev, priv->abase, &reg_save);  in lpc_ich_enable_acpi_space()
991 		pci_write_config_byte(dev, priv->abase, reg_save | 0x2);  in lpc_ich_enable_acpi_space()
992 		priv->abase_save = reg_save;  in lpc_ich_enable_acpi_space()
999 		pci_read_config_byte(dev, priv->actrl_pbase, &reg_save);  in lpc_ich_enable_acpi_space()
1000 		pci_write_config_byte(dev, priv->actrl_pbase, reg_save | 0x80);  in lpc_ich_enable_acpi_space()
1001 		priv->actrl_pbase_save = reg_save;  in lpc_ich_enable_acpi_space()
1011 	pci_read_config_byte(dev, priv->gctrl, &reg_save);  in lpc_ich_enable_gpio_space()
1012 	pci_write_config_byte(dev, priv->gctrl, reg_save | 0x10);  in lpc_ich_enable_gpio_space()
1013 	priv->gctrl_save = reg_save;  in lpc_ich_enable_gpio_space()
1021 	pci_read_config_byte(dev, priv->actrl_pbase, &reg_save);  in lpc_ich_enable_pmc_space()
1022 	pci_write_config_byte(dev, priv->actrl_pbase, reg_save | 0x2);  in lpc_ich_enable_pmc_space()
1024 	priv->actrl_pbase_save = reg_save;  in lpc_ich_enable_pmc_space()
1034 	pdata = devm_kzalloc(&dev->dev, sizeof(*pdata), GFP_KERNEL);  in lpc_ich_finalize_wdt_cell()
1036 		return -ENOMEM;  in lpc_ich_finalize_wdt_cell()
1038 	info = &lpc_chipset_info[priv->chipset];  in lpc_ich_finalize_wdt_cell()
1040 	pdata->version = info->iTCO_version;  in lpc_ich_finalize_wdt_cell()
1041 	strscpy(pdata->name, info->name, sizeof(pdata->name));  in lpc_ich_finalize_wdt_cell()
1043 	cell->platform_data = pdata;  in lpc_ich_finalize_wdt_cell()
1044 	cell->pdata_size = sizeof(*pdata);  in lpc_ich_finalize_wdt_cell()
1053 	cell->platform_data = &lpc_chipset_info[priv->chipset];  in lpc_ich_finalize_gpio_cell()
1054 	cell->pdata_size = sizeof(struct lpc_ich_info);  in lpc_ich_finalize_gpio_cell()
1068 	    !acpi_check_region(res->start + 0x40, 0x10, "LPC ICH GPIO3"))  in lpc_ich_check_conflict_gpio()
1071 	if (!acpi_check_region(res->start + 0x30, 0x10, "LPC ICH GPIO2"))  in lpc_ich_check_conflict_gpio()
1074 	ret = acpi_check_region(res->start + 0x00, 0x30, "LPC ICH GPIO1");  in lpc_ich_check_conflict_gpio()
1091 	pci_read_config_dword(dev, priv->abase, &base_addr_cfg);  in lpc_ich_init_gpio()
1094 		dev_notice(&dev->dev, "I/O space for ACPI uninitialized\n");  in lpc_ich_init_gpio()
1095 		lpc_ich_gpio_cell.num_resources--;  in lpc_ich_init_gpio()
1100 	res->start = base_addr + ACPIBASE_GPE_OFF;  in lpc_ich_init_gpio()
1101 	res->end = base_addr + ACPIBASE_GPE_END;  in lpc_ich_init_gpio()
1109 		lpc_ich_gpio_cell.num_resources--;  in lpc_ich_init_gpio()
1117 	pci_read_config_dword(dev, priv->gbase, &base_addr_cfg);  in lpc_ich_init_gpio()
1120 		dev_notice(&dev->dev, "I/O space for GPIO uninitialized\n");  in lpc_ich_init_gpio()
1121 		ret = -ENODEV;  in lpc_ich_init_gpio()
1127 	res->start = base_addr;  in lpc_ich_init_gpio()
1128 	switch (lpc_chipset_info[priv->chipset].gpio_version) {  in lpc_ich_init_gpio()
1131 		res->end = res->start + 128 - 1;  in lpc_ich_init_gpio()
1134 		res->end = res->start + 64 - 1;  in lpc_ich_init_gpio()
1144 	lpc_chipset_info[priv->chipset].use_gpio = ret;  in lpc_ich_init_gpio()
1148 	ret = mfd_add_devices(&dev->dev, PLATFORM_DEVID_AUTO,  in lpc_ich_init_gpio()
1168 		return -ENODEV;  in lpc_ich_init_wdt()
1171 	pci_read_config_dword(dev, priv->abase, &base_addr_cfg);  in lpc_ich_init_wdt()
1174 		dev_notice(&dev->dev, "I/O space for ACPI uninitialized\n");  in lpc_ich_init_wdt()
1175 		ret = -ENODEV;  in lpc_ich_init_wdt()
1180 	res->start = base_addr + ACPIBASE_TCO_OFF;  in lpc_ich_init_wdt()
1181 	res->end = base_addr + ACPIBASE_TCO_END;  in lpc_ich_init_wdt()
1184 	res->start = base_addr + ACPIBASE_SMI_OFF;  in lpc_ich_init_wdt()
1185 	res->end = base_addr + ACPIBASE_SMI_END;  in lpc_ich_init_wdt()
1191 	 * Get the Memory-Mapped GCS register. To get access to it  in lpc_ich_init_wdt()
1200 	if (lpc_chipset_info[priv->chipset].iTCO_version == 1) {  in lpc_ich_init_wdt()
1202 		lpc_ich_wdt_cell.num_resources--;  in lpc_ich_init_wdt()
1203 	} else if (lpc_chipset_info[priv->chipset].iTCO_version == 2) {  in lpc_ich_init_wdt()
1207 			dev_notice(&dev->dev, "RCBA is disabled by "  in lpc_ich_init_wdt()
1209 			ret = -ENODEV;  in lpc_ich_init_wdt()
1213 		res->start = base_addr + ACPIBASE_GCS_OFF;  in lpc_ich_init_wdt()
1214 		res->end = base_addr + ACPIBASE_GCS_END;  in lpc_ich_init_wdt()
1215 	} else if (lpc_chipset_info[priv->chipset].iTCO_version == 3) {  in lpc_ich_init_wdt()
1221 		res->start = base_addr + ACPIBASE_PMC_OFF;  in lpc_ich_init_wdt()
1222 		res->end = base_addr + ACPIBASE_PMC_END;  in lpc_ich_init_wdt()
1229 	ret = mfd_add_devices(&dev->dev, PLATFORM_DEVID_AUTO,  in lpc_ich_init_wdt()
1239 	const struct lpc_ich_gpio_info *info = lpc_chipset_info[priv->chipset].gpio_info;  in lpc_ich_init_pinctrl()
1245 	if (acpi_dev_present(info->hid, NULL, -1))  in lpc_ich_init_pinctrl()
1246 		return -EEXIST;  in lpc_ich_init_pinctrl()
1248 	ret = p2sb_bar(dev->bus, 0, &base);  in lpc_ich_init_pinctrl()
1252 	for (i = 0; i < info->nr_resources; i++) {  in lpc_ich_init_pinctrl()
1253 		struct resource *mem = info->resources[i];  in lpc_ich_init_pinctrl()
1254 		resource_size_t offset = info->offsets[i];  in lpc_ich_init_pinctrl()
1257 		mem->start = base.start + offset;  in lpc_ich_init_pinctrl()
1258 		mem->end = base.start + offset + INTEL_GPIO_RESOURCE_SIZE - 1;  in lpc_ich_init_pinctrl()
1259 		mem->flags = base.flags;  in lpc_ich_init_pinctrl()
1262 	return mfd_add_devices(&dev->dev, 0, info->devices, info->nr_devices,  in lpc_ich_init_pinctrl()
1298 	return lpc_ich_set_writeable(pdev->bus, pdev->devfn);  in lpc_ich_lpt_set_writeable()
1305 	return lpc_ich_set_writeable(pdev->bus, PCI_DEVFN(13, 2));  in lpc_ich_bxt_set_writeable()
1316 	info = devm_kzalloc(&dev->dev, sizeof(*info), GFP_KERNEL);  in lpc_ich_init_spi()
1318 		return -ENOMEM;  in lpc_ich_init_spi()
1320 	info->type = lpc_chipset_info[priv->chipset].spi_type;  in lpc_ich_init_spi()
1322 	switch (info->type) {  in lpc_ich_init_spi()
1326 			res->start = ALIGN_DOWN(spi_base, SPIBASE_BYT_SZ);  in lpc_ich_init_spi()
1327 			res->end = res->start + SPIBASE_BYT_SZ - 1;  in lpc_ich_init_spi()
1329 			info->set_writeable = lpc_ich_byt_set_writeable;  in lpc_ich_init_spi()
1337 			res->start = spi_base + SPIBASE_LPT;  in lpc_ich_init_spi()
1338 			res->end = res->start + SPIBASE_LPT_SZ - 1;  in lpc_ich_init_spi()
1340 			info->set_writeable = lpc_ich_lpt_set_writeable;  in lpc_ich_init_spi()
1341 			info->data = dev;  in lpc_ich_init_spi()
1351 		ret = p2sb_bar(dev->bus, PCI_DEVFN(13, 2), res);  in lpc_ich_init_spi()
1355 		info->set_writeable = lpc_ich_bxt_set_writeable;  in lpc_ich_init_spi()
1356 		info->data = dev;  in lpc_ich_init_spi()
1360 		return -EINVAL;  in lpc_ich_init_spi()
1363 	if (!res->start)  in lpc_ich_init_spi()
1364 		return -ENODEV;  in lpc_ich_init_spi()
1369 	return mfd_add_devices(&dev->dev, PLATFORM_DEVID_NONE,  in lpc_ich_init_spi()
1380 	priv = devm_kzalloc(&dev->dev,  in lpc_ich_probe()
1383 		return -ENOMEM;  in lpc_ich_probe()
1385 	priv->chipset = id->driver_data;  in lpc_ich_probe()
1387 	priv->actrl_pbase_save = -1;  in lpc_ich_probe()
1388 	priv->abase_save = -1;  in lpc_ich_probe()
1390 	priv->abase = ACPIBASE;  in lpc_ich_probe()
1391 	priv->actrl_pbase = ACPICTRL_PMCBASE;  in lpc_ich_probe()
1393 	priv->gctrl_save = -1;  in lpc_ich_probe()
1394 	if (priv->chipset <= LPC_ICH5) {  in lpc_ich_probe()
1395 		priv->gbase = GPIOBASE_ICH0;  in lpc_ich_probe()
1396 		priv->gctrl = GPIOCTRL_ICH0;  in lpc_ich_probe()
1398 		priv->gbase = GPIOBASE_ICH6;  in lpc_ich_probe()
1399 		priv->gctrl = GPIOCTRL_ICH6;  in lpc_ich_probe()
1404 	if (lpc_chipset_info[priv->chipset].iTCO_version) {  in lpc_ich_probe()
1410 	if (lpc_chipset_info[priv->chipset].gpio_version) {  in lpc_ich_probe()
1416 	if (lpc_chipset_info[priv->chipset].gpio_info) {  in lpc_ich_probe()
1422 	if (lpc_chipset_info[priv->chipset].spi_type) {  in lpc_ich_probe()
1433 		dev_warn(&dev->dev, "No MFD cells added\n");  in lpc_ich_probe()
1435 		return -ENODEV;  in lpc_ich_probe()
1443 	mfd_remove_devices(&dev->dev);  in lpc_ich_remove()
1456 MODULE_AUTHOR("Aaron Sierra <asierra@xes-inc.com>");