Lines Matching +full:pulse +full:- +full:width
1 // SPDX-License-Identifier: GPL-2.0-or-later
15 #include <media/rc-core.h>
22 /* Bit to enable IR pulse width detection */
38 /* Fields containing pulse width data */
56 /* Number of registers to record the pulse width */
71 /* Register containing pulse width data */
100 * struct mtk_ir_data - This is the structure holding all differences among
128 * struct mtk_ir - This is the main datasructure for holding the state
150 return ir->data->regs[MTK_CHKDATA_REG] + 4 * i; in mtk_chkdata_reg()
161 val = DIV_ROUND_CLOSEST(clk_get_rate(ir->bus), in mtk_chk_period()
162 USEC_PER_SEC * ir->data->div / MTK_IR_SAMPLE); in mtk_chk_period()
164 dev_dbg(ir->dev, "@pwm clk = \t%lu\n", in mtk_chk_period()
165 clk_get_rate(ir->bus) / ir->data->div); in mtk_chk_period()
166 dev_dbg(ir->dev, "@chkperiod = %08x\n", val); in mtk_chk_period()
175 tmp = __raw_readl(ir->base + reg); in mtk_w32_mask()
177 __raw_writel(tmp, ir->base + reg); in mtk_w32_mask()
182 __raw_writel(val, ir->base + reg); in mtk_w32()
187 return __raw_readl(ir->base + reg); in mtk_r32()
194 val = mtk_r32(ir, ir->data->regs[MTK_IRINT_EN_REG]); in mtk_irq_disable()
195 mtk_w32(ir, val & ~mask, ir->data->regs[MTK_IRINT_EN_REG]); in mtk_irq_disable()
202 val = mtk_r32(ir, ir->data->regs[MTK_IRINT_EN_REG]); in mtk_irq_enable()
203 mtk_w32(ir, val | mask, ir->data->regs[MTK_IRINT_EN_REG]); in mtk_irq_enable()
214 * Each pulse and space is encoded as a single byte, each byte in mtk_ir_irq()
215 * alternating between pulse and space. If a pulse or space is longer in mtk_ir_irq()
227 /* Handle all pulse and space IR controller captures */ in mtk_ir_irq()
230 dev_dbg(ir->dev, "@reg%d=0x%08x\n", i, val); in mtk_ir_irq()
235 rawir.pulse = !rawir.pulse; in mtk_ir_irq()
237 ir_raw_event_store_with_filter(ir->rc, &rawir); in mtk_ir_irq()
246 * ir-rc-raw to decode. That helps it is possible that it in mtk_ir_irq()
250 if (!MTK_IR_END(wid, rawir.pulse)) { in mtk_ir_irq()
251 rawir.pulse = false; in mtk_ir_irq()
253 ir_raw_event_store_with_filter(ir->rc, &rawir); in mtk_ir_irq()
256 ir_raw_event_handle(ir->rc); in mtk_ir_irq()
262 mtk_w32_mask(ir, 0x1, MTK_IRCLR, ir->data->regs[MTK_IRCLR_REG]); in mtk_ir_irq()
266 ir->data->regs[MTK_IRINT_CLR_REG]); in mtk_ir_irq()
288 { .compatible = "mediatek,mt7623-cir", .data = &mt7623_data},
289 { .compatible = "mediatek,mt7622-cir", .data = &mt7622_data},
296 struct device *dev = &pdev->dev; in mtk_ir_probe()
297 struct device_node *dn = dev->of_node; in mtk_ir_probe()
305 return -ENOMEM; in mtk_ir_probe()
307 ir->dev = dev; in mtk_ir_probe()
308 ir->data = of_device_get_match_data(dev); in mtk_ir_probe()
310 ir->clk = devm_clk_get(dev, "clk"); in mtk_ir_probe()
311 if (IS_ERR(ir->clk)) { in mtk_ir_probe()
313 return PTR_ERR(ir->clk); in mtk_ir_probe()
316 ir->bus = devm_clk_get(dev, "bus"); in mtk_ir_probe()
317 if (IS_ERR(ir->bus)) { in mtk_ir_probe()
320 * ir->bus uses the same clock as ir->clock. in mtk_ir_probe()
322 ir->bus = ir->clk; in mtk_ir_probe()
325 ir->base = devm_platform_ioremap_resource(pdev, 0); in mtk_ir_probe()
326 if (IS_ERR(ir->base)) in mtk_ir_probe()
327 return PTR_ERR(ir->base); in mtk_ir_probe()
329 ir->rc = devm_rc_allocate_device(dev, RC_DRIVER_IR_RAW); in mtk_ir_probe()
330 if (!ir->rc) { in mtk_ir_probe()
332 return -ENOMEM; in mtk_ir_probe()
335 ir->rc->priv = ir; in mtk_ir_probe()
336 ir->rc->device_name = MTK_IR_DEV; in mtk_ir_probe()
337 ir->rc->input_phys = MTK_IR_DEV "/input0"; in mtk_ir_probe()
338 ir->rc->input_id.bustype = BUS_HOST; in mtk_ir_probe()
339 ir->rc->input_id.vendor = 0x0001; in mtk_ir_probe()
340 ir->rc->input_id.product = 0x0001; in mtk_ir_probe()
341 ir->rc->input_id.version = 0x0001; in mtk_ir_probe()
342 map_name = of_get_property(dn, "linux,rc-map-name", NULL); in mtk_ir_probe()
343 ir->rc->map_name = map_name ?: RC_MAP_EMPTY; in mtk_ir_probe()
344 ir->rc->dev.parent = dev; in mtk_ir_probe()
345 ir->rc->driver_name = MTK_IR_DEV; in mtk_ir_probe()
346 ir->rc->allowed_protocols = RC_PROTO_BIT_ALL_IR_DECODER; in mtk_ir_probe()
347 ir->rc->rx_resolution = MTK_IR_SAMPLE; in mtk_ir_probe()
348 ir->rc->timeout = MTK_MAX_SAMPLES * (MTK_IR_SAMPLE + 1); in mtk_ir_probe()
350 ret = devm_rc_register_device(dev, ir->rc); in mtk_ir_probe()
358 ir->irq = platform_get_irq(pdev, 0); in mtk_ir_probe()
359 if (ir->irq < 0) in mtk_ir_probe()
360 return -ENODEV; in mtk_ir_probe()
362 if (clk_prepare_enable(ir->clk)) { in mtk_ir_probe()
364 return -EINVAL; in mtk_ir_probe()
367 if (clk_prepare_enable(ir->bus)) { in mtk_ir_probe()
369 ret = -EINVAL; in mtk_ir_probe()
379 ret = devm_request_irq(dev, ir->irq, mtk_ir_irq, 0, MTK_IR_DEV, ir); in mtk_ir_probe()
388 val = (mtk_chk_period(ir) << ir->data->fields[MTK_CHK_PERIOD].offset) & in mtk_ir_probe()
389 ir->data->fields[MTK_CHK_PERIOD].mask; in mtk_ir_probe()
390 mtk_w32_mask(ir, val, ir->data->fields[MTK_CHK_PERIOD].mask, in mtk_ir_probe()
391 ir->data->fields[MTK_CHK_PERIOD].reg); in mtk_ir_probe()
397 val = (ir->data->hw_period << ir->data->fields[MTK_HW_PERIOD].offset) & in mtk_ir_probe()
398 ir->data->fields[MTK_HW_PERIOD].mask; in mtk_ir_probe()
399 mtk_w32_mask(ir, val, ir->data->fields[MTK_HW_PERIOD].mask, in mtk_ir_probe()
400 ir->data->fields[MTK_HW_PERIOD].reg); in mtk_ir_probe()
402 /* Set de-glitch counter */ in mtk_ir_probe()
407 val |= MTK_OK_COUNT(ir->data->ok_count) | MTK_PWM_EN | MTK_IR_EN; in mtk_ir_probe()
418 clk_disable_unprepare(ir->bus); in mtk_ir_probe()
420 clk_disable_unprepare(ir->clk); in mtk_ir_probe()
435 synchronize_irq(ir->irq); in mtk_ir_remove()
437 clk_disable_unprepare(ir->bus); in mtk_ir_remove()
438 clk_disable_unprepare(ir->clk); in mtk_ir_remove()