3  * Hantro VPU codec driver
358 	struct hantro_dev *vpu = dev_id;  in rockchip_vpu1_vepu_irq()  local
362 	status = vepu_read(vpu, H1_REG_INTERRUPT);  in rockchip_vpu1_vepu_irq()
366 	vepu_write(vpu, 0, H1_REG_INTERRUPT);  in rockchip_vpu1_vepu_irq()
367 	vepu_write(vpu, 0, H1_REG_AXI_CTRL);  in rockchip_vpu1_vepu_irq()
369 	hantro_irq_done(vpu, state);  in rockchip_vpu1_vepu_irq()
376 	struct hantro_dev *vpu = dev_id;  in rockchip_vpu2_vdpu_irq()  local
380 	status = vdpu_read(vpu, VDPU_REG_INTERRUPT);  in rockchip_vpu2_vdpu_irq()
384 	vdpu_write(vpu, 0, VDPU_REG_INTERRUPT);  in rockchip_vpu2_vdpu_irq()
385 	vdpu_write(vpu, 0, VDPU_REG_AXI_CTRL);  in rockchip_vpu2_vdpu_irq()
387 	hantro_irq_done(vpu, state);  in rockchip_vpu2_vdpu_irq()
394 	struct hantro_dev *vpu = dev_id;  in rockchip_vpu2_vepu_irq()  local
398 	status = vepu_read(vpu, VEPU_REG_INTERRUPT);  in rockchip_vpu2_vepu_irq()
402 	vepu_write(vpu, 0, VEPU_REG_INTERRUPT);  in rockchip_vpu2_vepu_irq()
403 	vepu_write(vpu, 0, VEPU_REG_AXI_CTRL);  in rockchip_vpu2_vepu_irq()
405 	hantro_irq_done(vpu, state);  in rockchip_vpu2_vepu_irq()
412 	struct hantro_dev *vpu = dev_id;  in rk3588_vpu981_irq()  local
416 	status = vdpu_read(vpu, AV1_REG_INTERRUPT);  in rk3588_vpu981_irq()
420 	vdpu_write(vpu, 0, AV1_REG_INTERRUPT);  in rk3588_vpu981_irq()
421 	vdpu_write(vpu, AV1_REG_CONFIG_DEC_CLK_GATE_E, AV1_REG_CONFIG);  in rk3588_vpu981_irq()
423 	hantro_irq_done(vpu, state);  in rk3588_vpu981_irq()
428 static int rk3036_vpu_hw_init(struct hantro_dev *vpu)  in rk3036_vpu_hw_init()  argument
431 	clk_set_rate(vpu->clocks[0].clk, RK3066_ACLK_MAX_FREQ);  in rk3036_vpu_hw_init()
435 static int rk3066_vpu_hw_init(struct hantro_dev *vpu)  in rk3066_vpu_hw_init()  argument
438 	clk_set_rate(vpu->clocks[0].clk, RK3066_ACLK_MAX_FREQ);  in rk3066_vpu_hw_init()
439 	clk_set_rate(vpu->clocks[2].clk, RK3066_ACLK_MAX_FREQ);  in rk3066_vpu_hw_init()
443 static int rk3588_vpu981_hw_init(struct hantro_dev *vpu)  in rk3588_vpu981_hw_init()  argument
446 	clk_set_rate(vpu->clocks[0].clk, RK3588_ACLK_MAX_FREQ);  in rk3588_vpu981_hw_init()
450 static int rockchip_vpu_hw_init(struct hantro_dev *vpu)  in rockchip_vpu_hw_init()  argument
453 	clk_set_rate(vpu->clocks[0].clk, RK3288_ACLK_MAX_FREQ);  in rockchip_vpu_hw_init()
459 	struct hantro_dev *vpu = ctx->dev;  in rk3066_vpu_dec_reset()  local
461 	vdpu_write(vpu, G1_REG_INTERRUPT_DEC_IRQ_DIS, G1_REG_INTERRUPT);  in rk3066_vpu_dec_reset()
462 	vdpu_write(vpu, G1_REG_CONFIG_DEC_CLK_GATE_E, G1_REG_CONFIG);  in rk3066_vpu_dec_reset()
467 	struct hantro_dev *vpu = ctx->dev;  in rockchip_vpu1_enc_reset()  local
469 	vepu_write(vpu, H1_REG_INTERRUPT_DIS_BIT, H1_REG_INTERRUPT);  in rockchip_vpu1_enc_reset()
470 	vepu_write(vpu, 0, H1_REG_ENC_CTRL);  in rockchip_vpu1_enc_reset()
471 	vepu_write(vpu, 0, H1_REG_AXI_CTRL);  in rockchip_vpu1_enc_reset()
476 	struct hantro_dev *vpu = ctx->dev;  in rockchip_vpu2_dec_reset()  local
478 	vdpu_write(vpu, VDPU_REG_INTERRUPT_DEC_IRQ_DIS, VDPU_REG_INTERRUPT);  in rockchip_vpu2_dec_reset()
479 	vdpu_write(vpu, 0, VDPU_REG_EN_FLAGS);  in rockchip_vpu2_dec_reset()
480 	vdpu_write(vpu, 1, VDPU_REG_SOFT_RESET);  in rockchip_vpu2_dec_reset()
485 	struct hantro_dev *vpu = ctx->dev;  in rockchip_vpu2_enc_reset()  local
487 	vepu_write(vpu, VEPU_REG_INTERRUPT_DIS_BIT, VEPU_REG_INTERRUPT);  in rockchip_vpu2_enc_reset()
488 	vepu_write(vpu, 0, VEPU_REG_ENCODE_START);  in rockchip_vpu2_enc_reset()
489 	vepu_write(vpu, 0, VEPU_REG_AXI_CTRL);  in rockchip_vpu2_enc_reset()
611  * VPU variant.