3  * Hantro VPU codec driver
28 static void imx8m_soft_reset(struct hantro_dev *vpu, u32 reset_bits)  in imx8m_soft_reset()  argument
33 	val = readl(vpu->ctrl_base + CTRL_SOFT_RESET);  in imx8m_soft_reset()
35 	writel(val, vpu->ctrl_base + CTRL_SOFT_RESET);  in imx8m_soft_reset()
40 	val = readl(vpu->ctrl_base + CTRL_SOFT_RESET);  in imx8m_soft_reset()
42 	writel(val, vpu->ctrl_base + CTRL_SOFT_RESET);  in imx8m_soft_reset()
45 static void imx8m_clk_enable(struct hantro_dev *vpu, u32 clock_bits)  in imx8m_clk_enable()  argument
49 	val = readl(vpu->ctrl_base + CTRL_CLOCK_ENABLE);  in imx8m_clk_enable()
51 	writel(val, vpu->ctrl_base + CTRL_CLOCK_ENABLE);  in imx8m_clk_enable()
54 static int imx8mq_runtime_resume(struct hantro_dev *vpu)  in imx8mq_runtime_resume()  argument
58 	ret = clk_bulk_prepare_enable(vpu->variant->num_clocks, vpu->clocks);  in imx8mq_runtime_resume()
60 		dev_err(vpu->dev, "Failed to enable clocks\n");  in imx8mq_runtime_resume()
64 	imx8m_soft_reset(vpu, RESET_G1 | RESET_G2);  in imx8mq_runtime_resume()
65 	imx8m_clk_enable(vpu, CLOCK_G1 | CLOCK_G2);  in imx8mq_runtime_resume()
68 	writel(0xffffffff, vpu->ctrl_base + CTRL_G1_DEC_FUSE);  in imx8mq_runtime_resume()
69 	writel(0xffffffff, vpu->ctrl_base + CTRL_G1_PP_FUSE);  in imx8mq_runtime_resume()
70 	writel(0xffffffff, vpu->ctrl_base + CTRL_G2_DEC_FUSE);  in imx8mq_runtime_resume()
72 	clk_bulk_disable_unprepare(vpu->variant->num_clocks, vpu->clocks);  in imx8mq_runtime_resume()
239 	struct hantro_dev *vpu = dev_id;  in imx8m_vpu_g1_irq()  local
243 	status = vdpu_read(vpu, G1_REG_INTERRUPT);  in imx8m_vpu_g1_irq()
247 	vdpu_write(vpu, 0, G1_REG_INTERRUPT);  in imx8m_vpu_g1_irq()
248 	vdpu_write(vpu, G1_REG_CONFIG_DEC_CLK_GATE_E, G1_REG_CONFIG);  in imx8m_vpu_g1_irq()
250 	hantro_irq_done(vpu, state);  in imx8m_vpu_g1_irq()
255 static int imx8mq_vpu_hw_init(struct hantro_dev *vpu)  in imx8mq_vpu_hw_init()  argument
257 	vpu->ctrl_base = vpu->reg_bases[vpu->variant->num_regs - 1];  in imx8mq_vpu_hw_init()
264 	struct hantro_dev *vpu = ctx->dev;  in imx8m_vpu_g1_reset()  local
266 	imx8m_soft_reset(vpu, RESET_G1);  in imx8m_vpu_g1_reset()
327  * VPU variants.