Lines Matching +full:0 +full:x3d00
17 #define VI6_CMD(n) (0x0000 + (n) * 4)
19 #define VI6_CMD_STRCMD BIT(0)
21 #define VI6_CLK_DCSWT 0x0018
22 #define VI6_CLK_DCSWT_CSTPW_MASK (0xff << 8)
24 #define VI6_CLK_DCSWT_CSTRW_MASK (0xff << 0)
25 #define VI6_CLK_DCSWT_CSTRW_SHIFT 0
27 #define VI6_SRESET 0x0028
30 #define VI6_STATUS 0x0038
34 #define VI6_WPF_IRQ_ENB(n) (0x0048 + (n) * 12)
37 #define VI6_WPF_IRQ_ENB_FREE BIT(0)
39 #define VI6_WPF_IRQ_STA(n) (0x004c + (n) * 12)
42 #define VI6_WPF_IRQ_STA_FRE BIT(0)
44 #define VI6_DISP_IRQ_ENB(n) (0x0078 + (n) * 60)
49 #define VI6_DISP_IRQ_STA(n) (0x007c + (n) * 60)
54 #define VI6_WPF_LINE_COUNT(n) (0x0084 + (n) * 4)
55 #define VI6_WPF_LINE_COUNT_MASK (0x1fffff << 0)
61 #define VI6_DL_CTRL 0x0100
62 #define VI6_DL_CTRL_AR_WAIT_MASK (0xffff << 16)
69 #define VI6_DL_CTRL_DLE BIT(0)
71 #define VI6_DL_HDR_ADDR(n) (0x0104 + (n) * 4)
73 #define VI6_DL_SWAP 0x0114
76 #define VI6_DL_SWAP_BTS BIT(0)
78 #define VI6_DL_EXT_CTRL(n) (0x011c + (n) * 36)
80 #define VI6_DL_EXT_CTRL_POLINT_MASK (0x3f << 8)
84 #define VI6_DL_EXT_CTRL_EXT BIT(0)
86 #define VI6_DL_EXT_AUTOFLD_INT BIT(0)
88 #define VI6_DL_BODY_SIZE 0x0120
90 #define VI6_DL_BODY_SIZE_BS_MASK (0x1ffff << 0)
91 #define VI6_DL_BODY_SIZE_BS_SHIFT 0
97 #define VI6_RPF_OFFSET 0x100
99 #define VI6_RPF_SRC_BSIZE 0x0300
100 #define VI6_RPF_SRC_BSIZE_BHSIZE_MASK (0x1fff << 16)
102 #define VI6_RPF_SRC_BSIZE_BVSIZE_MASK (0x1fff << 0)
103 #define VI6_RPF_SRC_BSIZE_BVSIZE_SHIFT 0
105 #define VI6_RPF_SRC_ESIZE 0x0304
106 #define VI6_RPF_SRC_ESIZE_EHSIZE_MASK (0x1fff << 16)
108 #define VI6_RPF_SRC_ESIZE_EVSIZE_MASK (0x1fff << 0)
109 #define VI6_RPF_SRC_ESIZE_EVSIZE_SHIFT 0
111 #define VI6_RPF_INFMT 0x0308
116 #define VI6_RPF_INFMT_CEXT_ZERO (0 << 12)
120 #define VI6_RPF_INFMT_RDTM_BT601 (0 << 9)
126 #define VI6_RPF_INFMT_RDFMT_MASK (0x7f << 0)
127 #define VI6_RPF_INFMT_RDFMT_SHIFT 0
129 #define VI6_RPF_DSWAP 0x030c
137 #define VI6_RPF_DSWAP_P_BTS BIT(0)
139 #define VI6_RPF_LOC 0x0310
140 #define VI6_RPF_LOC_HCOORD_MASK (0x1fff << 16)
142 #define VI6_RPF_LOC_VCOORD_MASK (0x1fff << 0)
143 #define VI6_RPF_LOC_VCOORD_SHIFT 0
145 #define VI6_RPF_ALPH_SEL 0x0314
146 #define VI6_RPF_ALPH_SEL_ASEL_PACKED (0 << 28)
153 #define VI6_RPF_ALPH_SEL_IROP_MASK (0xf << 24)
156 #define VI6_RPF_ALPH_SEL_AEXT_ZERO (0 << 18)
160 #define VI6_RPF_ALPH_SEL_ALPHA1_MASK (0xff << 8)
162 #define VI6_RPF_ALPH_SEL_ALPHA0_MASK (0xff << 0)
163 #define VI6_RPF_ALPH_SEL_ALPHA0_SHIFT 0
165 #define VI6_RPF_VRTCOL_SET 0x0318
166 #define VI6_RPF_VRTCOL_SET_LAYA_MASK (0xff << 24)
168 #define VI6_RPF_VRTCOL_SET_LAYR_MASK (0xff << 16)
170 #define VI6_RPF_VRTCOL_SET_LAYG_MASK (0xff << 8)
172 #define VI6_RPF_VRTCOL_SET_LAYB_MASK (0xff << 0)
173 #define VI6_RPF_VRTCOL_SET_LAYB_SHIFT 0
175 #define VI6_RPF_MSK_CTRL 0x031c
177 #define VI6_RPF_MSK_CTRL_MGR_MASK (0xff << 16)
179 #define VI6_RPF_MSK_CTRL_MGG_MASK (0xff << 8)
181 #define VI6_RPF_MSK_CTRL_MGB_MASK (0xff << 0)
182 #define VI6_RPF_MSK_CTRL_MGB_SHIFT 0
184 #define VI6_RPF_MSK_SET0 0x0320
185 #define VI6_RPF_MSK_SET1 0x0324
186 #define VI6_RPF_MSK_SET_MSA_MASK (0xff << 24)
188 #define VI6_RPF_MSK_SET_MSR_MASK (0xff << 16)
190 #define VI6_RPF_MSK_SET_MSG_MASK (0xff << 8)
192 #define VI6_RPF_MSK_SET_MSB_MASK (0xff << 0)
193 #define VI6_RPF_MSK_SET_MSB_SHIFT 0
195 #define VI6_RPF_CKEY_CTRL 0x0328
198 #define VI6_RPF_CKEY_CTRL_SAPE0 BIT(0)
200 #define VI6_RPF_CKEY_SET0 0x032c
201 #define VI6_RPF_CKEY_SET1 0x0330
202 #define VI6_RPF_CKEY_SET_AP_MASK (0xff << 24)
204 #define VI6_RPF_CKEY_SET_R_MASK (0xff << 16)
206 #define VI6_RPF_CKEY_SET_GY_MASK (0xff << 8)
208 #define VI6_RPF_CKEY_SET_B_MASK (0xff << 0)
209 #define VI6_RPF_CKEY_SET_B_SHIFT 0
211 #define VI6_RPF_SRCM_PSTRIDE 0x0334
213 #define VI6_RPF_SRCM_PSTRIDE_C_SHIFT 0
215 #define VI6_RPF_SRCM_ASTRIDE 0x0338
216 #define VI6_RPF_SRCM_PSTRIDE_A_SHIFT 0
218 #define VI6_RPF_SRCM_ADDR_Y 0x033c
219 #define VI6_RPF_SRCM_ADDR_C0 0x0340
220 #define VI6_RPF_SRCM_ADDR_C1 0x0344
221 #define VI6_RPF_SRCM_ADDR_AI 0x0348
223 #define VI6_RPF_MULT_ALPHA 0x036c
224 #define VI6_RPF_MULT_ALPHA_A_MMD_NONE (0 << 12)
226 #define VI6_RPF_MULT_ALPHA_P_MMD_NONE (0 << 8)
230 #define VI6_RPF_MULT_ALPHA_RATIO_MASK (0xff << 0)
231 #define VI6_RPF_MULT_ALPHA_RATIO_SHIFT 0
233 #define VI6_RPF_EXT_INFMT0 0x0370
235 #define VI6_RPF_EXT_INFMT0_IPBD_Y_8 (0 << 8)
238 #define VI6_RPF_EXT_INFMT0_IPBD_C_8 (0 << 4)
241 #define VI6_RPF_EXT_INFMT0_BYPP_M1_RGB10 (3 << 0)
243 #define VI6_RPF_EXT_INFMT1 0x0374
245 (((a) << 24) | ((b) << 16) | ((c) << 8) | ((d) << 0))
247 #define VI6_RPF_EXT_INFMT2 0x0378
249 (((a) << 24) | ((b) << 16) | ((c) << 8) | ((d) << 0))
251 #define VI6_RPF_BRDITH_CTRL 0x03e0
253 #define VI6_RPF_BRDITH_CTRL_CBRM BIT(0)
259 #define VI6_WPF_OFFSET 0x100
261 #define VI6_WPF_SRCRPF 0x1000
262 #define VI6_WPF_SRCRPF_VIRACT_DIS (0 << 28)
266 #define VI6_WPF_SRCRPF_VIRACT2_DIS (0 << 24)
270 #define VI6_WPF_SRCRPF_RPF_ACT_DIS(n) (0 << ((n) * 2))
275 #define VI6_WPF_HSZCLIP 0x1004
276 #define VI6_WPF_VSZCLIP 0x1008
278 #define VI6_WPF_SZCLIP_OFST_MASK (0xff << 16)
280 #define VI6_WPF_SZCLIP_SIZE_MASK (0xfff << 0)
281 #define VI6_WPF_SZCLIP_SIZE_SHIFT 0
283 #define VI6_WPF_OUTFMT 0x100c
284 #define VI6_WPF_OUTFMT_PDV_MASK (0xff << 24)
292 #define VI6_WPF_OUTFMT_DITH_DIS (0 << 12)
295 #define VI6_WPF_OUTFMT_WRTM_BT601 (0 << 9)
301 #define VI6_WPF_OUTFMT_WRFMT_MASK (0x7f << 0)
302 #define VI6_WPF_OUTFMT_WRFMT_SHIFT 0
304 #define VI6_WPF_DSWAP 0x1010
308 #define VI6_WPF_DSWAP_P_BTS BIT(0)
310 #define VI6_WPF_RNDCTRL 0x1014
312 #define VI6_WPF_RNDCTRL_ABRM_TRUNC (0 << 24)
316 #define VI6_WPF_RNDCTRL_ATHRESH_MASK (0xff << 16)
318 #define VI6_WPF_RNDCTRL_CLMD_FULL (0 << 12)
323 #define VI6_WPF_ROT_CTRL 0x1018
325 #define VI6_WPF_ROT_CTRL_LMEM_WD_MASK (0x1fff << 0)
326 #define VI6_WPF_ROT_CTRL_LMEM_WD_SHIFT 0
328 #define VI6_WPF_DSTM_STRIDE_Y 0x101c
329 #define VI6_WPF_DSTM_STRIDE_C 0x1020
330 #define VI6_WPF_DSTM_ADDR_Y 0x1024
331 #define VI6_WPF_DSTM_ADDR_C0 0x1028
332 #define VI6_WPF_DSTM_ADDR_C1 0x102c
334 #define VI6_WPF_WRBCK_CTRL(n) (0x1034 + (n) * 0x100)
335 #define VI6_WPF_WRBCK_CTRL_WBMD BIT(0)
341 #define VI6_UIF_OFFSET 0x100
343 #define VI6_UIF_DISCOM_DOCMCR 0x1c00
345 #define VI6_UIF_DISCOM_DOCMCR_CMPR BIT(0)
347 #define VI6_UIF_DISCOM_DOCMSTR 0x1c04
349 #define VI6_UIF_DISCOM_DOCMSTR_CMPST BIT(0)
351 #define VI6_UIF_DISCOM_DOCMCLSTR 0x1c08
353 #define VI6_UIF_DISCOM_DOCMCLSTR_CMPCLST BIT(0)
355 #define VI6_UIF_DISCOM_DOCMIENR 0x1c0c
357 #define VI6_UIF_DISCOM_DOCMIENR_CMPIEN BIT(0)
359 #define VI6_UIF_DISCOM_DOCMMDR 0x1c10
362 #define VI6_UIF_DISCOM_DOCMPMR 0x1c14
366 #define VI6_UIF_DISCOM_DOCMPMR_SEL(n) ((n) << 0)
368 #define VI6_UIF_DISCOM_DOCMECRCR 0x1c18
369 #define VI6_UIF_DISCOM_DOCMCCRCR 0x1c1c
370 #define VI6_UIF_DISCOM_DOCMSPXR 0x1c20
371 #define VI6_UIF_DISCOM_DOCMSPYR 0x1c24
372 #define VI6_UIF_DISCOM_DOCMSZXR 0x1c28
373 #define VI6_UIF_DISCOM_DOCMSZYR 0x1c2c
379 #define VI6_DPR_RPF_ROUTE(n) (0x2000 + (n) * 4)
381 #define VI6_DPR_WPF_FPORCH(n) (0x2014 + (n) * 4)
384 #define VI6_DPR_SRU_ROUTE 0x2024
385 #define VI6_DPR_UDS_ROUTE(n) (0x2028 + (n) * 4)
386 #define VI6_DPR_LUT_ROUTE 0x203c
387 #define VI6_DPR_CLU_ROUTE 0x2040
388 #define VI6_DPR_HST_ROUTE 0x2044
389 #define VI6_DPR_HSI_ROUTE 0x2048
390 #define VI6_DPR_BRU_ROUTE 0x204c
391 #define VI6_DPR_ILV_BRS_ROUTE 0x2050
393 #define VI6_DPR_ROUTE_FXA_MASK (0xff << 16)
395 #define VI6_DPR_ROUTE_FP_MASK (0x3f << 8)
397 #define VI6_DPR_ROUTE_RT_MASK (0x3f << 0)
398 #define VI6_DPR_ROUTE_RT_SHIFT 0
400 #define VI6_DPR_HGO_SMPPT 0x2054
401 #define VI6_DPR_HGT_SMPPT 0x2058
404 #define VI6_DPR_SMPPT_PT_MASK (0x3f << 0)
405 #define VI6_DPR_SMPPT_PT_SHIFT 0
407 #define VI6_DPR_UIF_ROUTE(n) (0x2074 + (n) * 4)
428 #define VI6_SRU_CTRL0 0x2200
429 #define VI6_SRU_CTRL0_PARAM0_MASK (0x1ff << 16)
431 #define VI6_SRU_CTRL0_PARAM1_MASK (0x1f << 8)
437 #define VI6_SRU_CTRL0_EN BIT(0)
439 #define VI6_SRU_CTRL1 0x2204
440 #define VI6_SRU_CTRL1_PARAM5 0x7ff
442 #define VI6_SRU_CTRL2 0x2208
445 #define VI6_SRU_CTRL2_PARAM8_SHIFT 0
451 #define VI6_UDS_OFFSET 0x100
453 #define VI6_UDS_CTRL 0x2300
467 #define VI6_UDS_SCALE 0x2304
468 #define VI6_UDS_SCALE_HMANT_MASK (0xf << 28)
470 #define VI6_UDS_SCALE_HFRAC_MASK (0xfff << 16)
472 #define VI6_UDS_SCALE_VMANT_MASK (0xf << 12)
474 #define VI6_UDS_SCALE_VFRAC_MASK (0xfff << 0)
475 #define VI6_UDS_SCALE_VFRAC_SHIFT 0
477 #define VI6_UDS_ALPTH 0x2308
478 #define VI6_UDS_ALPTH_TH1_MASK (0xff << 8)
480 #define VI6_UDS_ALPTH_TH0_MASK (0xff << 0)
481 #define VI6_UDS_ALPTH_TH0_SHIFT 0
483 #define VI6_UDS_ALPVAL 0x230c
484 #define VI6_UDS_ALPVAL_VAL2_MASK (0xff << 16)
486 #define VI6_UDS_ALPVAL_VAL1_MASK (0xff << 8)
488 #define VI6_UDS_ALPVAL_VAL0_MASK (0xff << 0)
489 #define VI6_UDS_ALPVAL_VAL0_SHIFT 0
491 #define VI6_UDS_PASS_BWIDTH 0x2310
492 #define VI6_UDS_PASS_BWIDTH_H_MASK (0x7f << 16)
494 #define VI6_UDS_PASS_BWIDTH_V_MASK (0x7f << 0)
495 #define VI6_UDS_PASS_BWIDTH_V_SHIFT 0
497 #define VI6_UDS_HPHASE 0x2314
498 #define VI6_UDS_HPHASE_HSTP_MASK (0xfff << 16)
500 #define VI6_UDS_HPHASE_HEDP_MASK (0xfff << 0)
501 #define VI6_UDS_HPHASE_HEDP_SHIFT 0
503 #define VI6_UDS_IPC 0x2318
505 #define VI6_UDS_IPC_VEDP_MASK (0xfff << 0)
506 #define VI6_UDS_IPC_VEDP_SHIFT 0
508 #define VI6_UDS_HSZCLIP 0x231c
510 #define VI6_UDS_HSZCLIP_HCL_OFST_MASK (0xff << 16)
512 #define VI6_UDS_HSZCLIP_HCL_SIZE_MASK (0x1fff << 0)
513 #define VI6_UDS_HSZCLIP_HCL_SIZE_SHIFT 0
515 #define VI6_UDS_CLIP_SIZE 0x2324
516 #define VI6_UDS_CLIP_SIZE_HSIZE_MASK (0x1fff << 16)
518 #define VI6_UDS_CLIP_SIZE_VSIZE_MASK (0x1fff << 0)
519 #define VI6_UDS_CLIP_SIZE_VSIZE_SHIFT 0
521 #define VI6_UDS_FILL_COLOR 0x2328
522 #define VI6_UDS_FILL_COLOR_RFILC_MASK (0xff << 16)
524 #define VI6_UDS_FILL_COLOR_GFILC_MASK (0xff << 8)
526 #define VI6_UDS_FILL_COLOR_BFILC_MASK (0xff << 0)
527 #define VI6_UDS_FILL_COLOR_BFILC_SHIFT 0
533 #define VI6_LUT_CTRL 0x2800
534 #define VI6_LUT_CTRL_EN BIT(0)
540 #define VI6_CLU_CTRL 0x2900
549 #define VI6_CLU_CTRL_EN BIT(0)
555 #define VI6_HST_CTRL 0x2a00
556 #define VI6_HST_CTRL_EN BIT(0)
562 #define VI6_HSI_CTRL 0x2b00
563 #define VI6_HSI_CTRL_EN BIT(0)
569 #define VI6_ROP_NOP 0
586 #define VI6_BRU_BASE 0x2c00
587 #define VI6_BRS_BASE 0x3900
589 #define VI6_BRU_INCTRL 0x0000
592 #define VI6_BRU_INCTRL_DITHn_OFF (0 << ((n) * 4))
601 #define VI6_BRU_VIRRPF_SIZE 0x0004
602 #define VI6_BRU_VIRRPF_SIZE_HSIZE_MASK (0x1fff << 16)
604 #define VI6_BRU_VIRRPF_SIZE_VSIZE_MASK (0x1fff << 0)
605 #define VI6_BRU_VIRRPF_SIZE_VSIZE_SHIFT 0
607 #define VI6_BRU_VIRRPF_LOC 0x0008
608 #define VI6_BRU_VIRRPF_LOC_HCOORD_MASK (0x1fff << 16)
610 #define VI6_BRU_VIRRPF_LOC_VCOORD_MASK (0x1fff << 0)
611 #define VI6_BRU_VIRRPF_LOC_VCOORD_SHIFT 0
613 #define VI6_BRU_VIRRPF_COL 0x000c
614 #define VI6_BRU_VIRRPF_COL_A_MASK (0xff << 24)
616 #define VI6_BRU_VIRRPF_COL_RCR_MASK (0xff << 16)
618 #define VI6_BRU_VIRRPF_COL_GY_MASK (0xff << 8)
620 #define VI6_BRU_VIRRPF_COL_BCB_MASK (0xff << 0)
621 #define VI6_BRU_VIRRPF_COL_BCB_SHIFT 0
623 #define VI6_BRU_CTRL(n) (0x0010 + (n) * 8 + ((n) <= 3 ? 0 : 4))
632 #define VI6_BRU_CTRL_CROP_MASK (0xf << 4)
633 #define VI6_BRU_CTRL_AROP(rop) ((rop) << 0)
634 #define VI6_BRU_CTRL_AROP_MASK (0xf << 0)
636 #define VI6_BRU_BLD(n) (0x0014 + (n) * 8 + ((n) <= 3 ? 0 : 4))
638 #define VI6_BRU_BLD_CCMDX_DST_A (0 << 28)
644 #define VI6_BRU_BLD_CCMDY_DST_A (0 << 24)
652 #define VI6_BRU_BLD_ACMDX_DST_A (0 << 20)
658 #define VI6_BRU_BLD_ACMDY_DST_A (0 << 16)
664 #define VI6_BRU_BLD_COEFX_MASK (0xff << 8)
666 #define VI6_BRU_BLD_COEFY_MASK (0xff << 0)
667 #define VI6_BRU_BLD_COEFY_SHIFT 0
669 #define VI6_BRU_ROP 0x0030 /* Only available on BRU */
674 #define VI6_BRU_ROP_CROP_MASK (0xf << 4)
675 #define VI6_BRU_ROP_AROP(rop) ((rop) << 0)
676 #define VI6_BRU_ROP_AROP_MASK (0xf << 0)
682 #define VI6_HGO_OFFSET 0x3000
684 #define VI6_HGO_OFFSET_VOFFSET_SHIFT 0
685 #define VI6_HGO_SIZE 0x3004
687 #define VI6_HGO_SIZE_VSIZE_SHIFT 0
688 #define VI6_HGO_MODE 0x3008
695 #define VI6_HGO_MODE_VRATIO_SHIFT 0
696 #define VI6_HGO_LB_TH 0x300c
697 #define VI6_HGO_LBn_H(n) (0x3010 + (n) * 8)
698 #define VI6_HGO_LBn_V(n) (0x3014 + (n) * 8)
699 #define VI6_HGO_R_HISTO(n) (0x3030 + (n) * 4)
700 #define VI6_HGO_R_MAXMIN 0x3130
701 #define VI6_HGO_R_SUM 0x3134
702 #define VI6_HGO_R_LB_DET 0x3138
703 #define VI6_HGO_G_HISTO(n) (0x3140 + (n) * 4)
704 #define VI6_HGO_G_MAXMIN 0x3240
705 #define VI6_HGO_G_SUM 0x3244
706 #define VI6_HGO_G_LB_DET 0x3248
707 #define VI6_HGO_B_HISTO(n) (0x3250 + (n) * 4)
708 #define VI6_HGO_B_MAXMIN 0x3350
709 #define VI6_HGO_B_SUM 0x3354
710 #define VI6_HGO_B_LB_DET 0x3358
711 #define VI6_HGO_EXT_HIST_ADDR 0x335c
712 #define VI6_HGO_EXT_HIST_DATA 0x3360
713 #define VI6_HGO_REGRST 0x33fc
714 #define VI6_HGO_REGRST_RCLEA BIT(0)
720 #define VI6_HGT_OFFSET 0x3400
722 #define VI6_HGT_OFFSET_VOFFSET_SHIFT 0
723 #define VI6_HGT_SIZE 0x3404
725 #define VI6_HGT_SIZE_VSIZE_SHIFT 0
726 #define VI6_HGT_MODE 0x3408
728 #define VI6_HGT_MODE_VRATIO_SHIFT 0
729 #define VI6_HGT_HUE_AREA(n) (0x340c + (n) * 4)
731 #define VI6_HGT_HUE_AREA_UPPER_SHIFT 0
732 #define VI6_HGT_LB_TH 0x3424
733 #define VI6_HGT_LBn_H(n) (0x3428 + (n) * 8)
734 #define VI6_HGT_LBn_V(n) (0x342c + (n) * 8)
735 #define VI6_HGT_HISTO(m, n) (0x3450 + (m) * 128 + (n) * 4)
736 #define VI6_HGT_MAXMIN 0x3750
737 #define VI6_HGT_SUM 0x3754
738 #define VI6_HGT_LB_DET 0x3758
739 #define VI6_HGT_REGRST 0x37fc
740 #define VI6_HGT_REGRST_RCLEA BIT(0)
746 #define VI6_LIF_OFFSET (-0x100)
748 #define VI6_LIF_CTRL 0x3b00
749 #define VI6_LIF_CTRL_OBTH_MASK (0x7ff << 16)
753 #define VI6_LIF_CTRL_LIF_EN BIT(0)
755 #define VI6_LIF_CSBTH 0x3b04
756 #define VI6_LIF_CSBTH_HBTH_MASK (0x7ff << 16)
758 #define VI6_LIF_CSBTH_LBTH_MASK (0x7ff << 0)
759 #define VI6_LIF_CSBTH_LBTH_SHIFT 0
761 #define VI6_LIF_LBA 0x3b0c
763 #define VI6_LIF_LBA_LBA1_MASK (0xfff << 16)
770 #define VI6_SECURITY_CTRL0 0x3d00
771 #define VI6_SECURITY_CTRL1 0x3d04
777 #define VI6_IP_VERSION 0x3f00
778 #define VI6_IP_VERSION_MASK (0xffff << 0)
779 #define VI6_IP_VERSION_MODEL_MASK (0xff << 8)
780 #define VI6_IP_VERSION_MODEL_VSPS_H2 (0x09 << 8)
781 #define VI6_IP_VERSION_MODEL_VSPR_H2 (0x0a << 8)
782 #define VI6_IP_VERSION_MODEL_VSPD_GEN2 (0x0b << 8)
783 #define VI6_IP_VERSION_MODEL_VSPS_M2 (0x0c << 8)
784 #define VI6_IP_VERSION_MODEL_VSPS_V2H (0x12 << 8)
785 #define VI6_IP_VERSION_MODEL_VSPD_V2H (0x13 << 8)
786 #define VI6_IP_VERSION_MODEL_VSPI_GEN3 (0x14 << 8)
787 #define VI6_IP_VERSION_MODEL_VSPBD_GEN3 (0x15 << 8)
788 #define VI6_IP_VERSION_MODEL_VSPBC_GEN3 (0x16 << 8)
789 #define VI6_IP_VERSION_MODEL_VSPD_GEN3 (0x17 << 8)
790 #define VI6_IP_VERSION_MODEL_VSPD_V3 (0x18 << 8)
791 #define VI6_IP_VERSION_MODEL_VSPDL_GEN3 (0x19 << 8)
792 #define VI6_IP_VERSION_MODEL_VSPBS_GEN3 (0x1a << 8)
793 #define VI6_IP_VERSION_MODEL_VSPD_GEN4 (0x1c << 8)
794 /* RZ/G2L SoCs have no version register, So use 0x80 as the model version */
795 #define VI6_IP_VERSION_MODEL_VSPD_RZG2L (0x80 << 8)
797 #define VI6_IP_VERSION_SOC_MASK (0xff << 0)
798 #define VI6_IP_VERSION_SOC_H2 (0x01 << 0)
799 #define VI6_IP_VERSION_SOC_V2H (0x01 << 0)
800 #define VI6_IP_VERSION_SOC_V3M (0x01 << 0)
801 #define VI6_IP_VERSION_SOC_M2 (0x02 << 0)
802 #define VI6_IP_VERSION_SOC_M3W (0x02 << 0)
803 #define VI6_IP_VERSION_SOC_V3H (0x02 << 0)
804 #define VI6_IP_VERSION_SOC_H3 (0x03 << 0)
805 #define VI6_IP_VERSION_SOC_D3 (0x04 << 0)
806 #define VI6_IP_VERSION_SOC_M3N (0x04 << 0)
807 #define VI6_IP_VERSION_SOC_E3 (0x04 << 0)
808 #define VI6_IP_VERSION_SOC_V3U (0x05 << 0)
809 #define VI6_IP_VERSION_SOC_V4H (0x06 << 0)
810 /* RZ/G2L SoCs have no version register, So use 0x80 for SoC Identification */
811 #define VI6_IP_VERSION_SOC_RZG2L (0x80 << 0)
813 #define VI6_IP_VERSION_VSP_SW (0xfffe << 16) /* SW VSP version */
819 #define VI6_CLUT_TABLE 0x4000
825 #define VI6_LUT_TABLE 0x7000
831 #define VI6_CLU_ADDR 0x7400
832 #define VI6_CLU_DATA 0x7404
838 #define VI6_FMT_RGB_332 0x00
839 #define VI6_FMT_XRGB_4444 0x01
840 #define VI6_FMT_RGBX_4444 0x02
841 #define VI6_FMT_XRGB_1555 0x04
842 #define VI6_FMT_RGBX_5551 0x05
843 #define VI6_FMT_RGB_565 0x06
844 #define VI6_FMT_AXRGB_86666 0x07
845 #define VI6_FMT_RGBXA_66668 0x08
846 #define VI6_FMT_XRGBA_66668 0x09
847 #define VI6_FMT_ARGBX_86666 0x0a
848 #define VI6_FMT_AXRXGXB_8262626 0x0b
849 #define VI6_FMT_XRXGXBA_2626268 0x0c
850 #define VI6_FMT_ARXGXBX_8626262 0x0d
851 #define VI6_FMT_RXGXBXA_6262628 0x0e
852 #define VI6_FMT_XRGB_6666 0x0f
853 #define VI6_FMT_RGBX_6666 0x10
854 #define VI6_FMT_XRXGXB_262626 0x11
855 #define VI6_FMT_RXGXBX_626262 0x12
856 #define VI6_FMT_ARGB_8888 0x13
857 #define VI6_FMT_RGBA_8888 0x14
858 #define VI6_FMT_RGB_888 0x15
859 #define VI6_FMT_XRGXGB_763763 0x16
860 #define VI6_FMT_XXRGB_86666 0x17
861 #define VI6_FMT_BGR_888 0x18
862 #define VI6_FMT_ARGB_4444 0x19
863 #define VI6_FMT_RGBA_4444 0x1a
864 #define VI6_FMT_ARGB_1555 0x1b
865 #define VI6_FMT_RGBA_5551 0x1c
866 #define VI6_FMT_ABGR_4444 0x1d
867 #define VI6_FMT_BGRA_4444 0x1e
868 #define VI6_FMT_ABGR_1555 0x1f
869 #define VI6_FMT_BGRA_5551 0x20
870 #define VI6_FMT_XBXGXR_262626 0x21
871 #define VI6_FMT_ABGR_8888 0x22
872 #define VI6_FMT_XXRGB_88565 0x23
873 #define VI6_FMT_RGB10_RGB10A2_A2RGB10 0x30
875 #define VI6_FMT_Y_UV_444 0x40
876 #define VI6_FMT_Y_UV_422 0x41
877 #define VI6_FMT_Y_UV_420 0x42
878 #define VI6_FMT_YUV_444 0x46
879 #define VI6_FMT_YUYV_422 0x47
880 #define VI6_FMT_YYUV_422 0x48
881 #define VI6_FMT_YUV_420 0x49
882 #define VI6_FMT_Y_U_V_444 0x4a
883 #define VI6_FMT_Y_U_V_422 0x4b
884 #define VI6_FMT_Y_U_V_420 0x4c