Lines Matching full:vin
3 * Driver for Renesas R-Car VIN
19 #include "rcar-vin.h"
25 /* Register offsets for R-Car VIN */
82 /* Register bit fields for R-Car VIN */
161 static void rvin_write(struct rvin_dev *vin, u32 value, u32 offset) in rvin_write() argument
163 iowrite32(value, vin->base + offset); in rvin_write()
166 static u32 rvin_read(struct rvin_dev *vin, u32 offset) in rvin_read() argument
168 return ioread32(vin->base + offset); in rvin_read()
175 static bool rvin_scaler_needed(const struct rvin_dev *vin) in rvin_scaler_needed() argument
177 return !(vin->crop.width == vin->format.width && in rvin_scaler_needed()
178 vin->compose.width == vin->format.width && in rvin_scaler_needed()
179 vin->crop.height == vin->format.height && in rvin_scaler_needed()
180 vin->compose.height == vin->format.height); in rvin_scaler_needed()
501 static void rvin_set_coeff(struct rvin_dev *vin, unsigned short xs) in rvin_set_coeff() argument
522 rvin_write(vin, p_set->coeff_set[0], VNC1A_REG); in rvin_set_coeff()
523 rvin_write(vin, p_set->coeff_set[1], VNC1B_REG); in rvin_set_coeff()
524 rvin_write(vin, p_set->coeff_set[2], VNC1C_REG); in rvin_set_coeff()
526 rvin_write(vin, p_set->coeff_set[3], VNC2A_REG); in rvin_set_coeff()
527 rvin_write(vin, p_set->coeff_set[4], VNC2B_REG); in rvin_set_coeff()
528 rvin_write(vin, p_set->coeff_set[5], VNC2C_REG); in rvin_set_coeff()
530 rvin_write(vin, p_set->coeff_set[6], VNC3A_REG); in rvin_set_coeff()
531 rvin_write(vin, p_set->coeff_set[7], VNC3B_REG); in rvin_set_coeff()
532 rvin_write(vin, p_set->coeff_set[8], VNC3C_REG); in rvin_set_coeff()
534 rvin_write(vin, p_set->coeff_set[9], VNC4A_REG); in rvin_set_coeff()
535 rvin_write(vin, p_set->coeff_set[10], VNC4B_REG); in rvin_set_coeff()
536 rvin_write(vin, p_set->coeff_set[11], VNC4C_REG); in rvin_set_coeff()
538 rvin_write(vin, p_set->coeff_set[12], VNC5A_REG); in rvin_set_coeff()
539 rvin_write(vin, p_set->coeff_set[13], VNC5B_REG); in rvin_set_coeff()
540 rvin_write(vin, p_set->coeff_set[14], VNC5C_REG); in rvin_set_coeff()
542 rvin_write(vin, p_set->coeff_set[15], VNC6A_REG); in rvin_set_coeff()
543 rvin_write(vin, p_set->coeff_set[16], VNC6B_REG); in rvin_set_coeff()
544 rvin_write(vin, p_set->coeff_set[17], VNC6C_REG); in rvin_set_coeff()
546 rvin_write(vin, p_set->coeff_set[18], VNC7A_REG); in rvin_set_coeff()
547 rvin_write(vin, p_set->coeff_set[19], VNC7B_REG); in rvin_set_coeff()
548 rvin_write(vin, p_set->coeff_set[20], VNC7C_REG); in rvin_set_coeff()
550 rvin_write(vin, p_set->coeff_set[21], VNC8A_REG); in rvin_set_coeff()
551 rvin_write(vin, p_set->coeff_set[22], VNC8B_REG); in rvin_set_coeff()
552 rvin_write(vin, p_set->coeff_set[23], VNC8C_REG); in rvin_set_coeff()
555 void rvin_scaler_gen2(struct rvin_dev *vin) in rvin_scaler_gen2() argument
561 crop_height = vin->crop.height; in rvin_scaler_gen2()
562 if (V4L2_FIELD_HAS_BOTH(vin->format.field)) in rvin_scaler_gen2()
566 if (crop_height != vin->compose.height) in rvin_scaler_gen2()
567 ys = (4096 * crop_height) / vin->compose.height; in rvin_scaler_gen2()
568 rvin_write(vin, ys, VNYS_REG); in rvin_scaler_gen2()
571 if (vin->crop.width != vin->compose.width) in rvin_scaler_gen2()
572 xs = (4096 * vin->crop.width) / vin->compose.width; in rvin_scaler_gen2()
578 rvin_write(vin, xs, VNXS_REG); in rvin_scaler_gen2()
584 rvin_set_coeff(vin, xs); in rvin_scaler_gen2()
587 rvin_write(vin, 0, VNSPPOC_REG); in rvin_scaler_gen2()
588 rvin_write(vin, 0, VNSLPOC_REG); in rvin_scaler_gen2()
589 rvin_write(vin, vin->format.width - 1, VNEPPOC_REG); in rvin_scaler_gen2()
591 if (V4L2_FIELD_HAS_BOTH(vin->format.field)) in rvin_scaler_gen2()
592 rvin_write(vin, vin->format.height / 2 - 1, VNELPOC_REG); in rvin_scaler_gen2()
594 rvin_write(vin, vin->format.height - 1, VNELPOC_REG); in rvin_scaler_gen2()
596 vin_dbg(vin, in rvin_scaler_gen2()
598 vin->crop.width, vin->crop.height, vin->crop.left, in rvin_scaler_gen2()
599 vin->crop.top, ys, xs, vin->format.width, vin->format.height, in rvin_scaler_gen2()
619 void rvin_scaler_gen3(struct rvin_dev *vin) in rvin_scaler_gen3() argument
625 vnmc = rvin_read(vin, VNMC_REG); in rvin_scaler_gen3()
628 if (!rvin_scaler_needed(vin)) { in rvin_scaler_gen3()
629 rvin_write(vin, vnmc & ~VNMC_SCLE, VNMC_REG); in rvin_scaler_gen3()
633 ratio_h = rvin_uds_scale_ratio(vin->crop.width, vin->compose.width); in rvin_scaler_gen3()
636 ratio_v = rvin_uds_scale_ratio(vin->crop.height, vin->compose.height); in rvin_scaler_gen3()
639 clip_size = vin->compose.width << 16; in rvin_scaler_gen3()
641 switch (vin->format.field) { in rvin_scaler_gen3()
647 clip_size |= vin->compose.height / 2; in rvin_scaler_gen3()
650 clip_size |= vin->compose.height; in rvin_scaler_gen3()
654 rvin_write(vin, vnmc | VNMC_SCLE, VNMC_REG); in rvin_scaler_gen3()
655 rvin_write(vin, VNUDS_CTRL_AMD, VNUDS_CTRL_REG); in rvin_scaler_gen3()
656 rvin_write(vin, (ratio_h << 16) | ratio_v, VNUDS_SCALE_REG); in rvin_scaler_gen3()
657 rvin_write(vin, (bwidth_h << 16) | bwidth_v, VNUDS_PASS_BWIDTH_REG); in rvin_scaler_gen3()
658 rvin_write(vin, clip_size, VNUDS_CLIP_SIZE_REG); in rvin_scaler_gen3()
660 vin_dbg(vin, "Pre-Clip: %ux%u@%u:%u Post-Clip: %ux%u@%u:%u\n", in rvin_scaler_gen3()
661 vin->crop.width, vin->crop.height, vin->crop.left, in rvin_scaler_gen3()
662 vin->crop.top, vin->compose.width, vin->compose.height, in rvin_scaler_gen3()
663 vin->compose.left, vin->compose.top); in rvin_scaler_gen3()
666 void rvin_crop_scale_comp(struct rvin_dev *vin) in rvin_crop_scale_comp() argument
672 rvin_write(vin, vin->crop.left, VNSPPRC_REG); in rvin_crop_scale_comp()
673 rvin_write(vin, vin->crop.left + vin->crop.width - 1, VNEPPRC_REG); in rvin_crop_scale_comp()
674 rvin_write(vin, vin->crop.top, VNSLPRC_REG); in rvin_crop_scale_comp()
675 rvin_write(vin, vin->crop.top + vin->crop.height - 1, VNELPRC_REG); in rvin_crop_scale_comp()
677 if (vin->scaler) in rvin_crop_scale_comp()
678 vin->scaler(vin); in rvin_crop_scale_comp()
680 fmt = rvin_format_from_pixel(vin, vin->format.pixelformat); in rvin_crop_scale_comp()
681 stride = vin->format.bytesperline / fmt->bpp; in rvin_crop_scale_comp()
686 switch (vin->format.pixelformat) { in rvin_crop_scale_comp()
698 rvin_write(vin, stride, VNIS_REG); in rvin_crop_scale_comp()
705 static int rvin_setup(struct rvin_dev *vin) in rvin_setup() argument
710 switch (vin->format.field) { in rvin_setup()
721 if (!vin->info->use_mc && vin->std & V4L2_STD_525_60) in rvin_setup()
745 switch (vin->mbus_code) { in rvin_setup()
747 if (vin->is_csi) in rvin_setup()
756 if (vin->is_csi) in rvin_setup()
767 if (!vin->is_csi && in rvin_setup()
768 vin->parallel.mbus_type == V4L2_MBUS_BT656) in rvin_setup()
780 if (!vin->is_csi && in rvin_setup()
781 vin->parallel.mbus_type == V4L2_MBUS_BT656) in rvin_setup()
806 if (vin->info->model == RCAR_GEN3) { in rvin_setup()
812 if (vin->is_csi) { in rvin_setup()
813 vin_err(vin, "Invalid setting in MIPI CSI2\n"); in rvin_setup()
818 if (!vin->is_csi) { in rvin_setup()
819 vin_err(vin, "Invalid setting in Digital Pins\n"); in rvin_setup()
829 if (vin->info->model == RCAR_GEN3) in rvin_setup()
834 if (!vin->is_csi) { in rvin_setup()
836 if (!(vin->parallel.bus.flags & V4L2_MBUS_HSYNC_ACTIVE_LOW)) in rvin_setup()
840 if (!(vin->parallel.bus.flags & V4L2_MBUS_VSYNC_ACTIVE_LOW)) in rvin_setup()
844 if (vin->parallel.bus.flags & V4L2_MBUS_DATA_ENABLE_LOW) in rvin_setup()
847 switch (vin->mbus_code) { in rvin_setup()
849 if (vin->parallel.bus.bus_width == 8 && in rvin_setup()
850 vin->parallel.bus.data_shift == 8) in rvin_setup()
861 switch (vin->format.pixelformat) { in rvin_setup()
864 rvin_write(vin, in rvin_setup()
865 ALIGN(vin->format.bytesperline * vin->format.height, in rvin_setup()
867 dmr = vin->format.pixelformat == V4L2_PIX_FMT_NV12 ? in rvin_setup()
890 dmr = (vin->alpha ? VNDMR_ABIT : 0) | VNDMR_DTMD_ARGB; in rvin_setup()
893 dmr = VNDMR_A8BIT(vin->alpha) | VNDMR_EXRGB | VNDMR_DTMD_ARGB; in rvin_setup()
916 vin_err(vin, "Invalid pixelformat (0x%x)\n", in rvin_setup()
917 vin->format.pixelformat); in rvin_setup()
924 if (!vin->info->use_isp) { in rvin_setup()
929 if (vin->info->model == RCAR_GEN3) { in rvin_setup()
931 if (vin->is_csi) in rvin_setup()
942 rvin_write(vin, interrupts, VNINTS_REG); in rvin_setup()
944 rvin_write(vin, interrupts, VNIE_REG); in rvin_setup()
946 rvin_write(vin, dmr, VNDMR_REG); in rvin_setup()
947 rvin_write(vin, dmr2, VNDMR2_REG); in rvin_setup()
950 rvin_write(vin, vnmc | VNMC_ME, VNMC_REG); in rvin_setup()
955 static void rvin_disable_interrupts(struct rvin_dev *vin) in rvin_disable_interrupts() argument
957 rvin_write(vin, 0, VNIE_REG); in rvin_disable_interrupts()
960 static u32 rvin_get_interrupt_status(struct rvin_dev *vin) in rvin_get_interrupt_status() argument
962 return rvin_read(vin, VNINTS_REG); in rvin_get_interrupt_status()
965 static void rvin_ack_interrupt(struct rvin_dev *vin) in rvin_ack_interrupt() argument
967 rvin_write(vin, rvin_read(vin, VNINTS_REG), VNINTS_REG); in rvin_ack_interrupt()
970 static bool rvin_capture_active(struct rvin_dev *vin) in rvin_capture_active() argument
972 return rvin_read(vin, VNMS_REG) & VNMS_CA; in rvin_capture_active()
975 static enum v4l2_field rvin_get_active_field(struct rvin_dev *vin, u32 vnms) in rvin_get_active_field() argument
977 if (vin->format.field == V4L2_FIELD_ALTERNATE) { in rvin_get_active_field()
984 return vin->format.field; in rvin_get_active_field()
987 static void rvin_set_slot_addr(struct rvin_dev *vin, int slot, dma_addr_t addr) in rvin_set_slot_addr() argument
993 fmt = rvin_format_from_pixel(vin, vin->format.pixelformat); in rvin_set_slot_addr()
999 offsetx = vin->compose.left * fmt->bpp; in rvin_set_slot_addr()
1000 offsety = vin->compose.top * vin->format.bytesperline; in rvin_set_slot_addr()
1010 rvin_write(vin, offset, VNMB_REG(slot)); in rvin_set_slot_addr()
1019 static void rvin_fill_hw_slot(struct rvin_dev *vin, int slot) in rvin_fill_hw_slot() argument
1027 if (WARN_ON(vin->buf_hw[slot].buffer)) in rvin_fill_hw_slot()
1032 if (vin->buf_hw[prev].type == HALF_TOP) { in rvin_fill_hw_slot()
1033 vbuf = vin->buf_hw[prev].buffer; in rvin_fill_hw_slot()
1034 vin->buf_hw[slot].buffer = vbuf; in rvin_fill_hw_slot()
1035 vin->buf_hw[slot].type = HALF_BOTTOM; in rvin_fill_hw_slot()
1036 switch (vin->format.pixelformat) { in rvin_fill_hw_slot()
1039 phys_addr = vin->buf_hw[prev].phys + in rvin_fill_hw_slot()
1040 vin->format.sizeimage / 4; in rvin_fill_hw_slot()
1043 phys_addr = vin->buf_hw[prev].phys + in rvin_fill_hw_slot()
1044 vin->format.sizeimage / 2; in rvin_fill_hw_slot()
1047 } else if ((vin->state != STOPPED && vin->state != RUNNING) || in rvin_fill_hw_slot()
1048 list_empty(&vin->buf_list)) { in rvin_fill_hw_slot()
1049 vin->buf_hw[slot].buffer = NULL; in rvin_fill_hw_slot()
1050 vin->buf_hw[slot].type = FULL; in rvin_fill_hw_slot()
1051 phys_addr = vin->scratch_phys; in rvin_fill_hw_slot()
1054 buf = list_entry(vin->buf_list.next, struct rvin_buffer, list); in rvin_fill_hw_slot()
1057 vin->buf_hw[slot].buffer = vbuf; in rvin_fill_hw_slot()
1059 vin->buf_hw[slot].type = in rvin_fill_hw_slot()
1060 V4L2_FIELD_IS_SEQUENTIAL(vin->format.field) ? in rvin_fill_hw_slot()
1067 vin_dbg(vin, "Filling HW slot: %d type: %d buffer: %p\n", in rvin_fill_hw_slot()
1068 slot, vin->buf_hw[slot].type, vin->buf_hw[slot].buffer); in rvin_fill_hw_slot()
1070 vin->buf_hw[slot].phys = phys_addr; in rvin_fill_hw_slot()
1071 rvin_set_slot_addr(vin, slot, phys_addr); in rvin_fill_hw_slot()
1074 static int rvin_capture_start(struct rvin_dev *vin) in rvin_capture_start() argument
1079 vin->buf_hw[slot].buffer = NULL; in rvin_capture_start()
1080 vin->buf_hw[slot].type = FULL; in rvin_capture_start()
1084 rvin_fill_hw_slot(vin, slot); in rvin_capture_start()
1086 ret = rvin_setup(vin); in rvin_capture_start()
1090 rvin_crop_scale_comp(vin); in rvin_capture_start()
1092 vin_dbg(vin, "Starting to capture\n"); in rvin_capture_start()
1095 rvin_write(vin, VNFC_C_FRAME, VNFC_REG); in rvin_capture_start()
1097 vin->state = STARTING; in rvin_capture_start()
1102 static void rvin_capture_stop(struct rvin_dev *vin) in rvin_capture_stop() argument
1105 rvin_write(vin, 0, VNFC_REG); in rvin_capture_stop()
1108 rvin_write(vin, rvin_read(vin, VNMC_REG) & ~VNMC_ME, VNMC_REG); in rvin_capture_stop()
1120 struct rvin_dev *vin = data; in rvin_irq() local
1126 spin_lock_irqsave(&vin->qlock, flags); in rvin_irq()
1128 int_status = rvin_get_interrupt_status(vin); in rvin_irq()
1132 rvin_ack_interrupt(vin); in rvin_irq()
1140 if (vin->state == STOPPED) { in rvin_irq()
1141 vin_dbg(vin, "IRQ while state stopped\n"); in rvin_irq()
1146 vnms = rvin_read(vin, VNMS_REG); in rvin_irq()
1153 if (vin->state == STARTING) { in rvin_irq()
1155 vin_dbg(vin, "Starting sync slot: %d\n", slot); in rvin_irq()
1159 vin_dbg(vin, "Capture start synced!\n"); in rvin_irq()
1160 vin->state = RUNNING; in rvin_irq()
1164 if (vin->buf_hw[slot].buffer) { in rvin_irq()
1169 if (vin->buf_hw[slot].type == HALF_TOP) { in rvin_irq()
1170 vin->buf_hw[slot].buffer = NULL; in rvin_irq()
1171 rvin_fill_hw_slot(vin, slot); in rvin_irq()
1175 vin->buf_hw[slot].buffer->field = in rvin_irq()
1176 rvin_get_active_field(vin, vnms); in rvin_irq()
1177 vin->buf_hw[slot].buffer->sequence = vin->sequence; in rvin_irq()
1178 vin->buf_hw[slot].buffer->vb2_buf.timestamp = ktime_get_ns(); in rvin_irq()
1179 vb2_buffer_done(&vin->buf_hw[slot].buffer->vb2_buf, in rvin_irq()
1181 vin->buf_hw[slot].buffer = NULL; in rvin_irq()
1184 vin_dbg(vin, "Dropping frame %u\n", vin->sequence); in rvin_irq()
1187 vin->sequence++; in rvin_irq()
1190 rvin_fill_hw_slot(vin, slot); in rvin_irq()
1192 spin_unlock_irqrestore(&vin->qlock, flags); in rvin_irq()
1197 static void return_unused_buffers(struct rvin_dev *vin, in return_unused_buffers() argument
1203 spin_lock_irqsave(&vin->qlock, flags); in return_unused_buffers()
1205 list_for_each_entry_safe(buf, node, &vin->buf_list, list) { in return_unused_buffers()
1210 spin_unlock_irqrestore(&vin->qlock, flags); in return_unused_buffers()
1218 struct rvin_dev *vin = vb2_get_drv_priv(vq); in rvin_queue_setup() local
1222 return sizes[0] < vin->format.sizeimage ? -EINVAL : 0; in rvin_queue_setup()
1225 sizes[0] = vin->format.sizeimage; in rvin_queue_setup()
1232 struct rvin_dev *vin = vb2_get_drv_priv(vb->vb2_queue); in rvin_buffer_prepare() local
1233 unsigned long size = vin->format.sizeimage; in rvin_buffer_prepare()
1236 vin_err(vin, "buffer too small (%lu < %lu)\n", in rvin_buffer_prepare()
1249 struct rvin_dev *vin = vb2_get_drv_priv(vb->vb2_queue); in rvin_buffer_queue() local
1252 spin_lock_irqsave(&vin->qlock, flags); in rvin_buffer_queue()
1254 list_add_tail(to_buf_list(vbuf), &vin->buf_list); in rvin_buffer_queue()
1256 spin_unlock_irqrestore(&vin->qlock, flags); in rvin_buffer_queue()
1259 static int rvin_mc_validate_format(struct rvin_dev *vin, struct v4l2_subdev *sd, in rvin_mc_validate_format() argument
1278 if (vin->format.pixelformat != V4L2_PIX_FMT_SBGGR8) in rvin_mc_validate_format()
1282 if (vin->format.pixelformat != V4L2_PIX_FMT_SGBRG8) in rvin_mc_validate_format()
1286 if (vin->format.pixelformat != V4L2_PIX_FMT_SGRBG8) in rvin_mc_validate_format()
1290 if (vin->format.pixelformat != V4L2_PIX_FMT_SRGGB8) in rvin_mc_validate_format()
1294 if (vin->format.pixelformat != V4L2_PIX_FMT_GREY) in rvin_mc_validate_format()
1298 if (vin->format.pixelformat != V4L2_PIX_FMT_SBGGR10) in rvin_mc_validate_format()
1302 if (vin->format.pixelformat != V4L2_PIX_FMT_SGBRG10) in rvin_mc_validate_format()
1306 if (vin->format.pixelformat != V4L2_PIX_FMT_SGRBG10) in rvin_mc_validate_format()
1310 if (vin->format.pixelformat != V4L2_PIX_FMT_SRGGB10) in rvin_mc_validate_format()
1316 vin->mbus_code = fmt.format.code; in rvin_mc_validate_format()
1330 switch (vin->format.field) { in rvin_mc_validate_format()
1341 /* Use VIN hardware to combine the two fields */ in rvin_mc_validate_format()
1352 if (rvin_scaler_needed(vin)) { in rvin_mc_validate_format()
1354 if (vin->info->model == RCAR_GEN3 && in rvin_mc_validate_format()
1355 vin->format.pixelformat == V4L2_PIX_FMT_NV12) in rvin_mc_validate_format()
1358 if (!vin->scaler) in rvin_mc_validate_format()
1361 if (vin->format.pixelformat == V4L2_PIX_FMT_NV12) { in rvin_mc_validate_format()
1362 if (ALIGN(fmt.format.width, 32) != vin->format.width || in rvin_mc_validate_format()
1363 ALIGN(fmt.format.height, 32) != vin->format.height) in rvin_mc_validate_format()
1366 if (fmt.format.width != vin->format.width || in rvin_mc_validate_format()
1367 fmt.format.height != vin->format.height) in rvin_mc_validate_format()
1372 if (fmt.format.code != vin->mbus_code) in rvin_mc_validate_format()
1378 static int rvin_set_stream(struct rvin_dev *vin, int on) in rvin_set_stream() argument
1385 if (!vin->info->use_mc) { in rvin_set_stream()
1386 ret = v4l2_subdev_call(vin->parallel.subdev, video, s_stream, in rvin_set_stream()
1392 pad = media_pad_remote_pad_first(&vin->pad); in rvin_set_stream()
1399 video_device_pipeline_stop(&vin->vdev); in rvin_set_stream()
1403 ret = rvin_mc_validate_format(vin, sd, pad); in rvin_set_stream()
1407 ret = video_device_pipeline_alloc_start(&vin->vdev); in rvin_set_stream()
1415 video_device_pipeline_stop(&vin->vdev); in rvin_set_stream()
1420 int rvin_start_streaming(struct rvin_dev *vin) in rvin_start_streaming() argument
1425 ret = rvin_set_stream(vin, 1); in rvin_start_streaming()
1429 spin_lock_irqsave(&vin->qlock, flags); in rvin_start_streaming()
1431 vin->sequence = 0; in rvin_start_streaming()
1433 ret = rvin_capture_start(vin); in rvin_start_streaming()
1435 rvin_set_stream(vin, 0); in rvin_start_streaming()
1437 spin_unlock_irqrestore(&vin->qlock, flags); in rvin_start_streaming()
1444 struct rvin_dev *vin = vb2_get_drv_priv(vq); in rvin_start_streaming_vq() local
1448 vin->scratch = dma_alloc_coherent(vin->dev, vin->format.sizeimage, in rvin_start_streaming_vq()
1449 &vin->scratch_phys, GFP_KERNEL); in rvin_start_streaming_vq()
1450 if (!vin->scratch) in rvin_start_streaming_vq()
1453 ret = rvin_start_streaming(vin); in rvin_start_streaming_vq()
1459 dma_free_coherent(vin->dev, vin->format.sizeimage, vin->scratch, in rvin_start_streaming_vq()
1460 vin->scratch_phys); in rvin_start_streaming_vq()
1462 return_unused_buffers(vin, VB2_BUF_STATE_QUEUED); in rvin_start_streaming_vq()
1467 void rvin_stop_streaming(struct rvin_dev *vin) in rvin_stop_streaming() argument
1473 spin_lock_irqsave(&vin->qlock, flags); in rvin_stop_streaming()
1475 if (vin->state == STOPPED) { in rvin_stop_streaming()
1476 spin_unlock_irqrestore(&vin->qlock, flags); in rvin_stop_streaming()
1480 vin->state = STOPPING; in rvin_stop_streaming()
1487 if (vin->buf_hw[i].buffer) in rvin_stop_streaming()
1493 spin_unlock_irqrestore(&vin->qlock, flags); in rvin_stop_streaming()
1495 spin_lock_irqsave(&vin->qlock, flags); in rvin_stop_streaming()
1502 rvin_capture_stop(vin); in rvin_stop_streaming()
1505 if (!rvin_capture_active(vin)) { in rvin_stop_streaming()
1506 vin->state = STOPPED; in rvin_stop_streaming()
1510 spin_unlock_irqrestore(&vin->qlock, flags); in rvin_stop_streaming()
1512 spin_lock_irqsave(&vin->qlock, flags); in rvin_stop_streaming()
1515 if (!buffersFreed || vin->state != STOPPED) { in rvin_stop_streaming()
1521 vin_err(vin, "Failed stop HW, something is seriously broken\n"); in rvin_stop_streaming()
1522 vin->state = STOPPED; in rvin_stop_streaming()
1525 spin_unlock_irqrestore(&vin->qlock, flags); in rvin_stop_streaming()
1529 return_unused_buffers(vin, VB2_BUF_STATE_ERROR); in rvin_stop_streaming()
1531 if (vin->buf_hw[i].buffer) in rvin_stop_streaming()
1532 vb2_buffer_done(&vin->buf_hw[i].buffer->vb2_buf, in rvin_stop_streaming()
1537 rvin_set_stream(vin, 0); in rvin_stop_streaming()
1540 rvin_disable_interrupts(vin); in rvin_stop_streaming()
1545 struct rvin_dev *vin = vb2_get_drv_priv(vq); in rvin_stop_streaming_vq() local
1547 rvin_stop_streaming(vin); in rvin_stop_streaming_vq()
1550 dma_free_coherent(vin->dev, vin->format.sizeimage, vin->scratch, in rvin_stop_streaming_vq()
1551 vin->scratch_phys); in rvin_stop_streaming_vq()
1553 return_unused_buffers(vin, VB2_BUF_STATE_ERROR); in rvin_stop_streaming_vq()
1564 void rvin_dma_unregister(struct rvin_dev *vin) in rvin_dma_unregister() argument
1566 mutex_destroy(&vin->lock); in rvin_dma_unregister()
1568 v4l2_device_unregister(&vin->v4l2_dev); in rvin_dma_unregister()
1571 int rvin_dma_register(struct rvin_dev *vin, int irq) in rvin_dma_register() argument
1573 struct vb2_queue *q = &vin->queue; in rvin_dma_register()
1577 ret = v4l2_device_register(vin->dev, &vin->v4l2_dev); in rvin_dma_register()
1581 mutex_init(&vin->lock); in rvin_dma_register()
1582 INIT_LIST_HEAD(&vin->buf_list); in rvin_dma_register()
1584 spin_lock_init(&vin->qlock); in rvin_dma_register()
1586 vin->state = STOPPED; in rvin_dma_register()
1589 vin->buf_hw[i].buffer = NULL; in rvin_dma_register()
1594 q->lock = &vin->lock; in rvin_dma_register()
1595 q->drv_priv = vin; in rvin_dma_register()
1601 q->dev = vin->dev; in rvin_dma_register()
1605 vin_err(vin, "failed to initialize VB2 queue\n"); in rvin_dma_register()
1610 ret = devm_request_irq(vin->dev, irq, rvin_irq, IRQF_SHARED, in rvin_dma_register()
1611 KBUILD_MODNAME, vin); in rvin_dma_register()
1613 vin_err(vin, "failed to request irq\n"); in rvin_dma_register()
1619 rvin_dma_unregister(vin); in rvin_dma_register()
1630 * as it's only possible to do so when no VIN in the group is
1633 int rvin_set_channel_routing(struct rvin_dev *vin, u8 chsel) in rvin_set_channel_routing() argument
1640 ret = pm_runtime_resume_and_get(vin->dev); in rvin_set_channel_routing()
1645 vnmc = rvin_read(vin, VNMC_REG); in rvin_set_channel_routing()
1646 rvin_write(vin, vnmc & ~VNMC_VUP, VNMC_REG); in rvin_set_channel_routing()
1654 for (route = vin->info->routes; route->chsel; route++) { in rvin_set_channel_routing()
1666 rvin_write(vin, ifmd, VNCSI_IFMD_REG); in rvin_set_channel_routing()
1669 vin_dbg(vin, "Set IFMD 0x%x\n", ifmd); in rvin_set_channel_routing()
1671 vin->chsel = chsel; in rvin_set_channel_routing()
1674 rvin_write(vin, vnmc, VNMC_REG); in rvin_set_channel_routing()
1676 pm_runtime_put(vin->dev); in rvin_set_channel_routing()
1681 void rvin_set_alpha(struct rvin_dev *vin, unsigned int alpha) in rvin_set_alpha() argument
1686 spin_lock_irqsave(&vin->qlock, flags); in rvin_set_alpha()
1688 vin->alpha = alpha; in rvin_set_alpha()
1690 if (vin->state == STOPPED) in rvin_set_alpha()
1693 switch (vin->format.pixelformat) { in rvin_set_alpha()
1695 dmr = rvin_read(vin, VNDMR_REG) & ~VNDMR_ABIT; in rvin_set_alpha()
1696 if (vin->alpha) in rvin_set_alpha()
1700 dmr = rvin_read(vin, VNDMR_REG) & ~VNDMR_A8BIT_MASK; in rvin_set_alpha()
1701 dmr |= VNDMR_A8BIT(vin->alpha); in rvin_set_alpha()
1707 rvin_write(vin, dmr, VNDMR_REG); in rvin_set_alpha()
1709 spin_unlock_irqrestore(&vin->qlock, flags); in rvin_set_alpha()