22 #define HFI_MASK_QHDR_TX_TYPE		0xff000000
23 #define HFI_MASK_QHDR_RX_TYPE		0x00ff0000
24 #define HFI_MASK_QHDR_PRI_TYPE		0x0000ff00
25 #define HFI_MASK_QHDR_ID_TYPE		0x000000ff
27 #define HFI_HOST_TO_CTRL_CMD_Q		0
30 #define HFI_MASK_QHDR_STATUS		0x000000ff
33 #define IFACEQ_CMD_IDX			0
38 #define IFACEQ_DFLT_QHDR		0x01010000
205 	qhdr->tx_req = 0;  in venus_write_queue()
231 	*rx_req = qhdr->rx_req ? 1 : 0;  in venus_write_queue()
236 	return 0;  in venus_write_queue()
246 	u32 recv_request = 0;  in venus_read_queue()
247 	int ret = 0;  in venus_read_queue()
279 		*tx_req = 0;  in venus_read_queue()
326 		qhdr->rx_req = 0;  in venus_read_queue()
330 	*tx_req = qhdr->tx_req ? 1 : 0;  in venus_read_queue()
353 	return 0;  in venus_alloc()
370 	for (i = 0; i < count; i++)  in venus_set_registers()
424 	return 0;  in venus_iface_cmdq_write_nolock()
447 		return 0;  in venus_hfi_core_set_resource()
459 	return 0;  in venus_hfi_core_set_resource()
466 	u32 ctrl_status = 0, mask_val = 0;  in venus_boot_core()
467 	unsigned int count = 0;  in venus_boot_core()
470 	int ret = 0;  in venus_boot_core()
501 		writel(0x1, cpu_cs_base + CPU_CS_H2XSOFTINTEN_V6);  in venus_boot_core()
502 		writel(0x0, cpu_cs_base + CPU_CS_X2RPMH_V6);  in venus_boot_core()
542 	writel(0x01, cpu_cs_base + CPU_CS_SCIACMDARG1);  in venus_run()
554 	return 0;  in venus_run()
569 		writel(0x3, cpu_cs_base + CPU_CS_X2RPMH_V6);  in venus_halt_axi()
574 		writel(0x1, aon_base + AON_WRAPPER_MVP_NOC_LPI_CONTROL);  in venus_halt_axi()
577 					 val & BIT(0),  in venus_halt_axi()
584 		mask_val = (BIT(2) | BIT(1) | BIT(0));  in venus_halt_axi()
587 		writel(0x00, wrapper_base + WRAPPER_DEBUG_BRIDGE_LPI_CONTROL_V6);  in venus_halt_axi()
590 					 val == 0,  in venus_halt_axi()
598 		return 0;  in venus_halt_axi()
616 		return 0;  in venus_halt_axi()
634 	return 0;  in venus_halt_axi()
642 		return 0;  in venus_power_off()
654 	return 0;  in venus_power_off()
662 		return 0;  in venus_power_on()
674 	return 0;  in venus_power_on()
702 	return 0;  in venus_iface_msgq_read_nolock()
736 	return 0;  in venus_iface_dbgq_read_nolock()
758 	qhdr->pkt_size = 0;  in venus_set_qhdr_defaults()
762 	qhdr->tx_req = 0;  in venus_set_qhdr_defaults()
763 	qhdr->rx_irq_status = 0;  in venus_set_qhdr_defaults()
764 	qhdr->tx_irq_status = 0;  in venus_set_qhdr_defaults()
765 	qhdr->read_idx = 0;  in venus_set_qhdr_defaults()
766 	qhdr->write_idx = 0;  in venus_set_qhdr_defaults()
776 	memset(hdev->queues, 0, sizeof(hdev->queues));  in venus_interface_queues_release()
777 	memset(&hdev->ifaceq_table, 0, sizeof(hdev->ifaceq_table));  in venus_interface_queues_release()
778 	memset(&hdev->sfr, 0, sizeof(hdev->sfr));  in venus_interface_queues_release()
788 	struct mem_desc desc = {0};  in venus_interface_queues_init()
800 	for (i = 0; i < IFACEQ_NUM; i++) {  in venus_interface_queues_init()
822 	tbl_hdr->version = 0;  in venus_interface_queues_init()
834 	queue->qhdr->rx_req = 0;  in venus_interface_queues_init()
838 		hdev->sfr.da = 0;  in venus_interface_queues_init()
848 	return 0;  in venus_interface_queues_init()
882 		return 0;  in venus_sys_set_idle_message()
919 	return 0;  in venus_sys_set_ubwc_config()
1011 		return 0;  in venus_prepare_power_collapse()
1019 	return 0;  in venus_prepare_power_collapse()
1027 	if (ret1 < 0)  in venus_are_queues_empty()
1031 	if (ret2 < 0)  in venus_are_queues_empty()
1037 	return 0;  in venus_are_queues_empty()
1057 	p = memchr(sfr->data, '\0', size);  in venus_sfr_print()
1063 		sfr->data[size - 1] = '\0';  in venus_sfr_print()
1181 	return 0;  in venus_core_init()
1192 	return 0;  in venus_core_deinit()
1227 	return 0;  in venus_session_init()
1337 		return 0;  in venus_session_set_buffers()
1357 		return 0;  in venus_session_unset_buffers()
1396 	return 0;  in venus_session_parse_seq_hdr()
1428 		return 0;  in venus_session_set_property()
1451 	int ret = 0;  in venus_resume()
1478 		return 0;  in venus_suspend_1xx()
1503 	if (ret < 0 || !ret) {  in venus_suspend_1xx()
1524 	return 0;  in venus_suspend_1xx()
1577 		return 0;  in venus_suspend_3xx()
1595 	 *    (bit 0) in CPU status register and by checking Idle (bit 30) in  in venus_suspend_3xx()
1632 	return 0;  in venus_suspend_3xx()
1704 	return 0;  in venus_hfi_create()
1723 	for (i = 0; i < IFACEQ_NUM; i++) {  in venus_hfi_queues_reinit()
1741 	tbl_hdr->version = 0;  in venus_hfi_queues_reinit()
1753 	queue->qhdr->rx_req = 0;  in venus_hfi_queues_reinit()