21 #define VFE_0_HW_VERSION		0x000
23 #define VFE_0_GLOBAL_RESET_CMD		0x018
24 #define VFE_0_GLOBAL_RESET_CMD_CORE	BIT(0)
35 #define VFE_0_MODULE_LENS_EN		0x040
39 #define VFE_0_MODULE_ZOOM_EN		0x04c
44 #define VFE_0_CORE_CFG			0x050
45 #define VFE_0_CORE_CFG_PIXEL_PATTERN_YCBYCR	0x4
46 #define VFE_0_CORE_CFG_PIXEL_PATTERN_YCRYCB	0x5
47 #define VFE_0_CORE_CFG_PIXEL_PATTERN_CBYCRY	0x6
48 #define VFE_0_CORE_CFG_PIXEL_PATTERN_CRYCBY	0x7
51 #define VFE_0_IRQ_CMD			0x058
52 #define VFE_0_IRQ_CMD_GLOBAL_CLEAR	BIT(0)
54 #define VFE_0_IRQ_MASK_0		0x05c
55 #define VFE_0_IRQ_MASK_0_CAMIF_SOF			BIT(0)
63 #define VFE_0_IRQ_MASK_1		0x060
64 #define VFE_0_IRQ_MASK_1_CAMIF_ERROR			BIT(0)
70 #define VFE_0_IRQ_CLEAR_0		0x064
71 #define VFE_0_IRQ_CLEAR_1		0x068
73 #define VFE_0_IRQ_STATUS_0		0x06c
74 #define VFE_0_IRQ_STATUS_0_CAMIF_SOF			BIT(0)
81 #define VFE_0_IRQ_STATUS_1		0x070
86 #define VFE_0_IRQ_COMPOSITE_MASK_0	0x074
87 #define VFE_0_VIOLATION_STATUS		0x07c
89 #define VFE_0_BUS_CMD			0x80
92 #define VFE_0_BUS_CFG			0x084
94 #define VFE_0_BUS_XBAR_CFG_x(x)		(0x90 + 0x4 * ((x) / 2))
97 #define VFE_0_BUS_XBAR_CFG_x_M_PAIR_STREAM_SWAP_INTRA		(0x1 << 4)
98 #define VFE_0_BUS_XBAR_CFG_x_M_PAIR_STREAM_SWAP_INTER		(0x2 << 4)
99 #define VFE_0_BUS_XBAR_CFG_x_M_PAIR_STREAM_SWAP_INTER_INTRA	(0x3 << 4)
101 #define VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_LUMA		0x0
102 #define VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_VAL_RDI0	0xc
103 #define VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_VAL_RDI1	0xd
104 #define VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_VAL_RDI2	0xe
106 #define VFE_0_BUS_IMAGE_MASTER_n_WR_CFG(n)		(0x0a0 + 0x2c * (n))
107 #define VFE_0_BUS_IMAGE_MASTER_n_WR_CFG_WR_PATH_SHIFT	0
108 #define VFE_0_BUS_IMAGE_MASTER_n_WR_PING_ADDR(n)	(0x0a4 + 0x2c * (n))
109 #define VFE_0_BUS_IMAGE_MASTER_n_WR_PONG_ADDR(n)	(0x0ac + 0x2c * (n))
110 #define VFE_0_BUS_IMAGE_MASTER_n_WR_ADDR_CFG(n)		(0x0b4 + 0x2c * (n))
113 #define VFE_0_BUS_IMAGE_MASTER_n_WR_ADDR_CFG_FRM_DROP_PER_MASK	(0x1f << 2)
114 #define VFE_0_BUS_IMAGE_MASTER_n_WR_UB_CFG(n)		(0x0b8 + 0x2c * (n))
116 #define VFE_0_BUS_IMAGE_MASTER_n_WR_IMAGE_SIZE(n)	(0x0bc + 0x2c * (n))
117 #define VFE_0_BUS_IMAGE_MASTER_n_WR_BUFFER_CFG(n)	(0x0c0 + 0x2c * (n))
119 							(0x0c4 + 0x2c * (n))
121 							(0x0c8 + 0x2c * (n))
122 #define VFE_0_BUS_IMAGE_MASTER_n_WR_IRQ_SUBSAMPLE_PATTERN_DEF	0xffffffff
124 #define VFE_0_BUS_PING_PONG_STATUS	0x338
126 #define VFE_0_BUS_BDG_CMD		0x400
129 #define VFE_0_BUS_BDG_QOS_CFG_0		0x404
130 #define VFE_0_BUS_BDG_QOS_CFG_0_CFG	0xaaa9aaa9
131 #define VFE_0_BUS_BDG_QOS_CFG_1		0x408
132 #define VFE_0_BUS_BDG_QOS_CFG_2		0x40c
133 #define VFE_0_BUS_BDG_QOS_CFG_3		0x410
134 #define VFE_0_BUS_BDG_QOS_CFG_4		0x414
135 #define VFE_0_BUS_BDG_QOS_CFG_5		0x418
136 #define VFE_0_BUS_BDG_QOS_CFG_6		0x41c
137 #define VFE_0_BUS_BDG_QOS_CFG_7		0x420
138 #define VFE_0_BUS_BDG_QOS_CFG_7_CFG	0x0001aaa9
140 #define VFE48_0_BUS_BDG_QOS_CFG_0_CFG	0xaaa5aaa5
141 #define VFE48_0_BUS_BDG_QOS_CFG_3_CFG	0xaa55aaa5
142 #define VFE48_0_BUS_BDG_QOS_CFG_4_CFG	0xaa55aa55
143 #define VFE48_0_BUS_BDG_QOS_CFG_7_CFG	0x0005aa55
145 #define VFE_0_BUS_BDG_DS_CFG_0		0x424
146 #define VFE_0_BUS_BDG_DS_CFG_0_CFG	0xcccc0011
147 #define VFE_0_BUS_BDG_DS_CFG_1		0x428
148 #define VFE_0_BUS_BDG_DS_CFG_2		0x42c
149 #define VFE_0_BUS_BDG_DS_CFG_3		0x430
150 #define VFE_0_BUS_BDG_DS_CFG_4		0x434
151 #define VFE_0_BUS_BDG_DS_CFG_5		0x438
152 #define VFE_0_BUS_BDG_DS_CFG_6		0x43c
153 #define VFE_0_BUS_BDG_DS_CFG_7		0x440
154 #define VFE_0_BUS_BDG_DS_CFG_8		0x444
155 #define VFE_0_BUS_BDG_DS_CFG_9		0x448
156 #define VFE_0_BUS_BDG_DS_CFG_10		0x44c
157 #define VFE_0_BUS_BDG_DS_CFG_11		0x450
158 #define VFE_0_BUS_BDG_DS_CFG_12		0x454
159 #define VFE_0_BUS_BDG_DS_CFG_13		0x458
160 #define VFE_0_BUS_BDG_DS_CFG_14		0x45c
161 #define VFE_0_BUS_BDG_DS_CFG_15		0x460
162 #define VFE_0_BUS_BDG_DS_CFG_16		0x464
163 #define VFE_0_BUS_BDG_DS_CFG_16_CFG	0x40000103
165 #define VFE48_0_BUS_BDG_DS_CFG_0_CFG	0xcccc1111
166 #define VFE48_0_BUS_BDG_DS_CFG_16_CFG	0x00000110
168 #define VFE_0_RDI_CFG_x(x)		(0x46c + (0x4 * (x)))
170 #define VFE_0_RDI_CFG_x_RDI_STREAM_SEL_MASK	(0xf << 28)
172 #define VFE_0_RDI_CFG_x_RDI_M0_SEL_MASK		(0xf << 4)
174 #define VFE_0_RDI_CFG_x_MIPI_EN_BITS		0x3
176 #define VFE_0_CAMIF_CMD				0x478
177 #define VFE_0_CAMIF_CMD_DISABLE_FRAME_BOUNDARY	0
181 #define VFE_0_CAMIF_CFG				0x47c
183 #define VFE_0_CAMIF_FRAME_CFG			0x484
184 #define VFE_0_CAMIF_WINDOW_WIDTH_CFG		0x488
185 #define VFE_0_CAMIF_WINDOW_HEIGHT_CFG		0x48c
186 #define VFE_0_CAMIF_SUBSAMPLE_CFG		0x490
187 #define VFE_0_CAMIF_IRQ_FRAMEDROP_PATTERN	0x498
188 #define VFE_0_CAMIF_IRQ_SUBSAMPLE_PATTERN	0x49c
189 #define VFE_0_CAMIF_STATUS			0x4a4
192 #define VFE_0_REG_UPDATE		0x4ac
197 #define VFE_0_DEMUX_CFG				0x560
198 #define VFE_0_DEMUX_CFG_PERIOD			0x3
199 #define VFE_0_DEMUX_GAIN_0			0x564
200 #define VFE_0_DEMUX_GAIN_0_CH0_EVEN		(0x80 << 0)
201 #define VFE_0_DEMUX_GAIN_0_CH0_ODD		(0x80 << 16)
202 #define VFE_0_DEMUX_GAIN_1			0x568
203 #define VFE_0_DEMUX_GAIN_1_CH1			(0x80 << 0)
204 #define VFE_0_DEMUX_GAIN_1_CH2			(0x80 << 16)
205 #define VFE_0_DEMUX_EVEN_CFG			0x574
206 #define VFE_0_DEMUX_EVEN_CFG_PATTERN_YUYV	0x9cac
207 #define VFE_0_DEMUX_EVEN_CFG_PATTERN_YVYU	0xac9c
208 #define VFE_0_DEMUX_EVEN_CFG_PATTERN_UYVY	0xc9ca
209 #define VFE_0_DEMUX_EVEN_CFG_PATTERN_VYUY	0xcac9
210 #define VFE_0_DEMUX_ODD_CFG			0x578
211 #define VFE_0_DEMUX_ODD_CFG_PATTERN_YUYV	0x9cac
212 #define VFE_0_DEMUX_ODD_CFG_PATTERN_YVYU	0xac9c
213 #define VFE_0_DEMUX_ODD_CFG_PATTERN_UYVY	0xc9ca
214 #define VFE_0_DEMUX_ODD_CFG_PATTERN_VYUY	0xcac9
216 #define VFE_0_SCALE_ENC_Y_CFG			0x91c
217 #define VFE_0_SCALE_ENC_Y_H_IMAGE_SIZE		0x920
218 #define VFE_0_SCALE_ENC_Y_H_PHASE		0x924
219 #define VFE_0_SCALE_ENC_Y_V_IMAGE_SIZE		0x934
220 #define VFE_0_SCALE_ENC_Y_V_PHASE		0x938
221 #define VFE_0_SCALE_ENC_CBCR_CFG		0x948
222 #define VFE_0_SCALE_ENC_CBCR_H_IMAGE_SIZE	0x94c
223 #define VFE_0_SCALE_ENC_CBCR_H_PHASE		0x950
224 #define VFE_0_SCALE_ENC_CBCR_V_IMAGE_SIZE	0x960
225 #define VFE_0_SCALE_ENC_CBCR_V_PHASE		0x964
227 #define VFE_0_CROP_ENC_Y_WIDTH			0x974
228 #define VFE_0_CROP_ENC_Y_HEIGHT			0x978
229 #define VFE_0_CROP_ENC_CBCR_WIDTH		0x97c
230 #define VFE_0_CROP_ENC_CBCR_HEIGHT		0x980
232 #define VFE_0_CLAMP_ENC_MAX_CFG			0x984
233 #define VFE_0_CLAMP_ENC_MAX_CFG_CH0		(0xff << 0)
234 #define VFE_0_CLAMP_ENC_MAX_CFG_CH1		(0xff << 8)
235 #define VFE_0_CLAMP_ENC_MAX_CFG_CH2		(0xff << 16)
236 #define VFE_0_CLAMP_ENC_MIN_CFG			0x988
237 #define VFE_0_CLAMP_ENC_MIN_CFG_CH0		(0x0 << 0)
238 #define VFE_0_CLAMP_ENC_MIN_CFG_CH1		(0x0 << 8)
239 #define VFE_0_CLAMP_ENC_MIN_CFG_CH2		(0x0 << 16)
241 #define VFE_0_REALIGN_BUF_CFG			0xaac
246 #define VFE48_0_BUS_IMAGE_MASTER_CMD		0xcec
261 	dev_dbg(vfe->camss->dev, "VFE HW Version = 0x%08x\n", hw_version);  in vfe_hw_version()
268 	if (vfe_id == 0)  in vfe_get_ub_size()
273 	return 0;  in vfe_get_ub_size()
318 	writel_relaxed(0x0, vfe->base + VFE_0_BUS_BDG_CMD);  in vfe_halt_clear()
345 	int val = 0;  in vfe_word_per_line_by_pixel()
379 		*bytesperline = pix->plane_fmt[0].bytesperline;  in vfe_get_wm_sizes()
385 		*bytesperline = pix->plane_fmt[0].bytesperline;  in vfe_get_wm_sizes()
403 		u16 width = 0, height = 0, bytesperline = 0, wpl;  in vfe_wm_line_based()
417 		reg = 0x3;  in vfe_wm_line_based()
424 		writel_relaxed(0, vfe->base +  in vfe_wm_line_based()
426 		writel_relaxed(0, vfe->base +  in vfe_wm_line_based()
493 	return (reg >> wm) & 0x1;  in vfe_wm_get_ping_pong_status()
499 		writel_relaxed(0x101, vfe->base + VFE_0_BUS_CFG);  in vfe_bus_enable_wr_if()
501 		writel_relaxed(0, vfe->base + VFE_0_BUS_CFG);  in vfe_bus_enable_wr_if()
510 	vfe_reg_set(vfe, VFE_0_RDI_CFG_x(0), reg);  in vfe_bus_connect_wm_to_rdi()
591 		if (output->wm_idx[0] % 2 == 1)  in vfe_set_xbar_cfg()
596 				    VFE_0_BUS_XBAR_CFG_x(output->wm_idx[0]),  in vfe_set_xbar_cfg()
600 				    VFE_0_BUS_XBAR_CFG_x(output->wm_idx[0]),  in vfe_set_xbar_cfg()
629 		if (output->wm_idx[0] % 2 == 1)  in vfe_set_xbar_cfg()
634 				    VFE_0_BUS_XBAR_CFG_x(output->wm_idx[0]),  in vfe_set_xbar_cfg()
638 				    VFE_0_BUS_XBAR_CFG_x(output->wm_idx[0]),  in vfe_set_xbar_cfg()
724 	u32 comp_mask = 0;  in vfe_enable_irq_pix_line()
731 	for (i = 0; i < output->wm_num; i++) {  in vfe_enable_irq_pix_line()
802 	writel_relaxed(0x3, vfe->base + VFE_0_SCALE_ENC_Y_CFG);  in vfe_set_scale_cfg()
824 	writel_relaxed(0x3, vfe->base + VFE_0_SCALE_ENC_CBCR_CFG);  in vfe_set_scale_cfg()
972 	val = 0xffffffff;  in vfe_set_camif_cfg()
975 	val = 0xffffffff;  in vfe_set_camif_cfg()
978 	val = 0xffffffff;  in vfe_set_camif_cfg()
982 	vfe_reg_set(vfe, VFE_0_RDI_CFG_x(0), val);  in vfe_set_camif_cfg()
1032 	if (ret < 0)  in vfe_camif_wait_for_stop()
1055 	dev_dbg(vfe->camss->dev, "VFE: status0 = 0x%08x, status1 = 0x%08x\n",  in vfe_isr()
1078 	for (i = 0; i < MSM_VFE_COMPOSITE_IRQ_NUM; i++)  in vfe_isr()
1081 			for (j = 0; j < ARRAY_SIZE(vfe->wm_output_map); j++)  in vfe_isr()
1086 	for (i = 0; i < MSM_VFE_IMAGE_MASTERS_NUM; i++)  in vfe_isr()
1110 	pr_err_ratelimited("VFE: violation = 0x%08x\n", violation);  in vfe_violation_read()