19 #define VFE_0_HW_VERSION		0x000
21 #define VFE_0_GLOBAL_RESET_CMD		0x00c
22 #define VFE_0_GLOBAL_RESET_CMD_CORE	BIT(0)
32 #define VFE_0_MODULE_CFG		0x018
38 #define VFE_0_CORE_CFG			0x01c
39 #define VFE_0_CORE_CFG_PIXEL_PATTERN_YCBYCR	0x4
40 #define VFE_0_CORE_CFG_PIXEL_PATTERN_YCRYCB	0x5
41 #define VFE_0_CORE_CFG_PIXEL_PATTERN_CBYCRY	0x6
42 #define VFE_0_CORE_CFG_PIXEL_PATTERN_CRYCBY	0x7
44 #define VFE_0_IRQ_CMD			0x024
45 #define VFE_0_IRQ_CMD_GLOBAL_CLEAR	BIT(0)
47 #define VFE_0_IRQ_MASK_0		0x028
48 #define VFE_0_IRQ_MASK_0_CAMIF_SOF			BIT(0)
56 #define VFE_0_IRQ_MASK_1		0x02c
57 #define VFE_0_IRQ_MASK_1_CAMIF_ERROR			BIT(0)
63 #define VFE_0_IRQ_CLEAR_0		0x030
64 #define VFE_0_IRQ_CLEAR_1		0x034
66 #define VFE_0_IRQ_STATUS_0		0x038
67 #define VFE_0_IRQ_STATUS_0_CAMIF_SOF			BIT(0)
74 #define VFE_0_IRQ_STATUS_1		0x03c
79 #define VFE_0_IRQ_COMPOSITE_MASK_0	0x40
80 #define VFE_0_VIOLATION_STATUS		0x48
82 #define VFE_0_BUS_CMD			0x4c
85 #define VFE_0_BUS_CFG			0x050
87 #define VFE_0_BUS_XBAR_CFG_x(x)		(0x58 + 0x4 * ((x) / 2))
89 #define VFE_0_BUS_XBAR_CFG_x_M_PAIR_STREAM_SWAP_INTER_INTRA	(0x3 << 4)
91 #define VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_LUMA		0
96 #define VFE_0_BUS_IMAGE_MASTER_n_WR_CFG(n)		(0x06c + 0x24 * (n))
97 #define VFE_0_BUS_IMAGE_MASTER_n_WR_CFG_WR_PATH_SHIFT	0
99 #define VFE_0_BUS_IMAGE_MASTER_n_WR_PING_ADDR(n)	(0x070 + 0x24 * (n))
100 #define VFE_0_BUS_IMAGE_MASTER_n_WR_PONG_ADDR(n)	(0x074 + 0x24 * (n))
101 #define VFE_0_BUS_IMAGE_MASTER_n_WR_ADDR_CFG(n)		(0x078 + 0x24 * (n))
103 #define VFE_0_BUS_IMAGE_MASTER_n_WR_ADDR_CFG_FRM_DROP_PER_MASK	(0x1f << 2)
105 #define VFE_0_BUS_IMAGE_MASTER_n_WR_UB_CFG(n)		(0x07c + 0x24 * (n))
107 #define VFE_0_BUS_IMAGE_MASTER_n_WR_IMAGE_SIZE(n)	(0x080 + 0x24 * (n))
108 #define VFE_0_BUS_IMAGE_MASTER_n_WR_BUFFER_CFG(n)	(0x084 + 0x24 * (n))
110 							(0x088 + 0x24 * (n))
112 							(0x08c + 0x24 * (n))
113 #define VFE_0_BUS_IMAGE_MASTER_n_WR_IRQ_SUBSAMPLE_PATTERN_DEF	0xffffffff
115 #define VFE_0_BUS_PING_PONG_STATUS	0x268
117 #define VFE_0_BUS_BDG_CMD		0x2c0
120 #define VFE_0_BUS_BDG_QOS_CFG_0		0x2c4
121 #define VFE_0_BUS_BDG_QOS_CFG_0_CFG	0xaaa5aaa5
122 #define VFE_0_BUS_BDG_QOS_CFG_1		0x2c8
123 #define VFE_0_BUS_BDG_QOS_CFG_2		0x2cc
124 #define VFE_0_BUS_BDG_QOS_CFG_3		0x2d0
125 #define VFE_0_BUS_BDG_QOS_CFG_4		0x2d4
126 #define VFE_0_BUS_BDG_QOS_CFG_5		0x2d8
127 #define VFE_0_BUS_BDG_QOS_CFG_6		0x2dc
128 #define VFE_0_BUS_BDG_QOS_CFG_7		0x2e0
129 #define VFE_0_BUS_BDG_QOS_CFG_7_CFG	0x0001aaa5
131 #define VFE_0_RDI_CFG_x(x)		(0x2e8 + (0x4 * (x)))
133 #define VFE_0_RDI_CFG_x_RDI_STREAM_SEL_MASK	(0xf << 28)
135 #define VFE_0_RDI_CFG_x_RDI_M0_SEL_MASK		(0xf << 4)
137 #define VFE_0_RDI_CFG_x_MIPI_EN_BITS		0x3
140 #define VFE_0_CAMIF_CMD				0x2f4
141 #define VFE_0_CAMIF_CMD_DISABLE_FRAME_BOUNDARY	0
145 #define VFE_0_CAMIF_CFG				0x2f8
147 #define VFE_0_CAMIF_FRAME_CFG			0x300
148 #define VFE_0_CAMIF_WINDOW_WIDTH_CFG		0x304
149 #define VFE_0_CAMIF_WINDOW_HEIGHT_CFG		0x308
150 #define VFE_0_CAMIF_SUBSAMPLE_CFG_0		0x30c
151 #define VFE_0_CAMIF_IRQ_SUBSAMPLE_PATTERN	0x314
152 #define VFE_0_CAMIF_STATUS			0x31c
155 #define VFE_0_REG_UPDATE			0x378
160 #define VFE_0_DEMUX_CFG				0x424
161 #define VFE_0_DEMUX_CFG_PERIOD			0x3
162 #define VFE_0_DEMUX_GAIN_0			0x428
163 #define VFE_0_DEMUX_GAIN_0_CH0_EVEN		(0x80 << 0)
164 #define VFE_0_DEMUX_GAIN_0_CH0_ODD		(0x80 << 16)
165 #define VFE_0_DEMUX_GAIN_1			0x42c
166 #define VFE_0_DEMUX_GAIN_1_CH1			(0x80 << 0)
167 #define VFE_0_DEMUX_GAIN_1_CH2			(0x80 << 16)
168 #define VFE_0_DEMUX_EVEN_CFG			0x438
169 #define VFE_0_DEMUX_EVEN_CFG_PATTERN_YUYV	0x9cac
170 #define VFE_0_DEMUX_EVEN_CFG_PATTERN_YVYU	0xac9c
171 #define VFE_0_DEMUX_EVEN_CFG_PATTERN_UYVY	0xc9ca
172 #define VFE_0_DEMUX_EVEN_CFG_PATTERN_VYUY	0xcac9
173 #define VFE_0_DEMUX_ODD_CFG			0x43c
174 #define VFE_0_DEMUX_ODD_CFG_PATTERN_YUYV	0x9cac
175 #define VFE_0_DEMUX_ODD_CFG_PATTERN_YVYU	0xac9c
176 #define VFE_0_DEMUX_ODD_CFG_PATTERN_UYVY	0xc9ca
177 #define VFE_0_DEMUX_ODD_CFG_PATTERN_VYUY	0xcac9
179 #define VFE_0_SCALE_ENC_Y_CFG			0x75c
180 #define VFE_0_SCALE_ENC_Y_H_IMAGE_SIZE		0x760
181 #define VFE_0_SCALE_ENC_Y_H_PHASE		0x764
182 #define VFE_0_SCALE_ENC_Y_V_IMAGE_SIZE		0x76c
183 #define VFE_0_SCALE_ENC_Y_V_PHASE		0x770
184 #define VFE_0_SCALE_ENC_CBCR_CFG		0x778
185 #define VFE_0_SCALE_ENC_CBCR_H_IMAGE_SIZE	0x77c
186 #define VFE_0_SCALE_ENC_CBCR_H_PHASE		0x780
187 #define VFE_0_SCALE_ENC_CBCR_V_IMAGE_SIZE	0x790
188 #define VFE_0_SCALE_ENC_CBCR_V_PHASE		0x794
190 #define VFE_0_CROP_ENC_Y_WIDTH			0x854
191 #define VFE_0_CROP_ENC_Y_HEIGHT			0x858
192 #define VFE_0_CROP_ENC_CBCR_WIDTH		0x85c
193 #define VFE_0_CROP_ENC_CBCR_HEIGHT		0x860
195 #define VFE_0_CLAMP_ENC_MAX_CFG			0x874
196 #define VFE_0_CLAMP_ENC_MAX_CFG_CH0		(0xff << 0)
197 #define VFE_0_CLAMP_ENC_MAX_CFG_CH1		(0xff << 8)
198 #define VFE_0_CLAMP_ENC_MAX_CFG_CH2		(0xff << 16)
199 #define VFE_0_CLAMP_ENC_MIN_CFG			0x878
200 #define VFE_0_CLAMP_ENC_MIN_CFG_CH0		(0x0 << 0)
201 #define VFE_0_CLAMP_ENC_MIN_CFG_CH1		(0x0 << 8)
202 #define VFE_0_CLAMP_ENC_MIN_CFG_CH2		(0x0 << 16)
204 #define VFE_0_CGC_OVERRIDE_1			0x974
217 	dev_dbg(vfe->camss->dev, "VFE HW Version = 0x%08x\n", hw_version);  in vfe_hw_version()
224 	if (vfe_id == 0)  in vfe_get_ub_size()
227 	return 0;  in vfe_get_ub_size()
267 	writel_relaxed(0x0, vfe->base + VFE_0_BUS_BDG_CMD);  in vfe_halt_clear()
295 	*bytesperline = pix->plane_fmt[0].bytesperline;  in vfe_get_wm_sizes()
310 		u16 width = 0, height = 0, bytesperline = 0, wpl;  in vfe_wm_line_based()
324 		reg = 0x3;  in vfe_wm_line_based()
331 		writel_relaxed(0, vfe->base +  in vfe_wm_line_based()
333 		writel_relaxed(0, vfe->base +  in vfe_wm_line_based()
396 	return (reg >> wm) & 0x1;  in vfe_wm_get_ping_pong_status()
402 		writel_relaxed(0x10000009, vfe->base + VFE_0_BUS_CFG);  in vfe_bus_enable_wr_if()
404 		writel_relaxed(0, vfe->base + VFE_0_BUS_CFG);  in vfe_bus_enable_wr_if()
414 	vfe_reg_set(vfe, VFE_0_RDI_CFG_x(0), reg);  in vfe_bus_connect_wm_to_rdi()
456 	vfe_reg_clr(vfe, VFE_0_RDI_CFG_x(0), reg);  in vfe_bus_disconnect_wm_from_rdi()
491 	for (i = 0; i < output->wm_num; i++) {  in vfe_set_xbar_cfg()
492 		if (i == 0) {  in vfe_set_xbar_cfg()
570 	u32 comp_mask = 0;  in vfe_enable_irq_pix_line()
577 	for (i = 0; i < output->wm_num; i++) {  in vfe_enable_irq_pix_line()
648 	writel_relaxed(0x3, vfe->base + VFE_0_SCALE_ENC_Y_CFG);  in vfe_set_scale_cfg()
670 	writel_relaxed(0x3, vfe->base + VFE_0_SCALE_ENC_CBCR_CFG);  in vfe_set_scale_cfg()
805 	val = 0xffffffff;  in vfe_set_camif_cfg()
808 	val = 0xffffffff;  in vfe_set_camif_cfg()
812 	vfe_reg_set(vfe, VFE_0_RDI_CFG_x(0), val);  in vfe_set_camif_cfg()
844 		writel_relaxed(0x0, vfe->base + VFE_0_MODULE_CFG);  in vfe_set_module_cfg()
857 	if (ret < 0)  in vfe_camif_wait_for_stop()
879 	pr_err_ratelimited("VFE: violation = 0x%08x\n", violation);  in vfe_violation_read()
897 	dev_dbg(vfe->camss->dev, "VFE: status0 = 0x%08x, status1 = 0x%08x\n",  in vfe_isr()
920 	for (i = 0; i < MSM_VFE_COMPOSITE_IRQ_NUM; i++)  in vfe_isr()
923 			for (j = 0; j < ARRAY_SIZE(vfe->wm_output_map); j++)  in vfe_isr()
928 	for (i = 0; i < MSM_VFE_IMAGE_MASTERS_NUM; i++)  in vfe_isr()
954 		return 0;  in vfe_4_1_pm_domain_on()