52 	return readl_relaxed_poll_timeout(vde->mbe + 0x8C, tmp,  in tegra_vde_wait_mbe()
65 	tegra_vde_writel(vde, 0xD0000000 | (0 << 23), vde->mbe, 0x80);  in tegra_vde_setup_mbe_frame_idx()
66 	tegra_vde_writel(vde, 0xD0200000 | (0 << 23), vde->mbe, 0x80);  in tegra_vde_setup_mbe_frame_idx()
77 				 vde->mbe, 0x80);  in tegra_vde_setup_mbe_frame_idx()
79 				 vde->mbe, 0x80);  in tegra_vde_setup_mbe_frame_idx()
88 			tegra_vde_writel(vde, value, vde->mbe, 0x80);  in tegra_vde_setup_mbe_frame_idx()
104 			 vde->mbe, 0x80);  in tegra_vde_mbe_set_0xa_reg()
106 			 vde->mbe, 0x80);  in tegra_vde_mbe_set_0xa_reg()
279 	tegra_vde_set_bits(vde, 0x8002, vde->mbe, 0x50);  in tegra_vde_setup_hw_context()
280 	tegra_vde_set_bits(vde, 0x000A, vde->mbe, 0xA0);  in tegra_vde_setup_hw_context()
292 	tegra_vde_writel(vde, 0x00000000, vde->mbe, 0x84);  in tegra_vde_setup_hw_context()
404 	tegra_vde_writel(vde, value, vde->mbe, 0x80);  in tegra_vde_setup_hw_context()
411 	tegra_vde_writel(vde, value, vde->mbe, 0x80);  in tegra_vde_setup_hw_context()
413 	tegra_vde_writel(vde, 0xF4000001, vde->mbe, 0x80);  in tegra_vde_setup_hw_context()
414 	tegra_vde_writel(vde, 0x20000000, vde->mbe, 0x80);  in tegra_vde_setup_hw_context()
415 	tegra_vde_writel(vde, 0xF4000101, vde->mbe, 0x80);  in tegra_vde_setup_hw_context()
420 	tegra_vde_writel(vde, value, vde->mbe, 0x80);  in tegra_vde_setup_hw_context()
426 		dev_err(dev, "MBE frames setup failed %d\n", err);  in tegra_vde_setup_hw_context()
442 	tegra_vde_writel(vde, value, vde->mbe, 0x80);  in tegra_vde_setup_hw_context()
446 		dev_err(dev, "MBE programming failed %d\n", err);  in tegra_vde_setup_hw_context()