117 	else if (CFG_CHECK(MT8195, p_id))  in config_rdma_frame()
118 		reg = CFG_COMP(MT8195, ctx->param, rdma.src_ctrl);  in config_rdma_frame()
126 			else if (CFG_CHECK(MT8195, p_id))  in config_rdma_frame()
127 				reg = CFG_COMP(MT8195, ctx->param, rdma.ufo_dec_y);  in config_rdma_frame()
133 			else if (CFG_CHECK(MT8195, p_id))  in config_rdma_frame()
134 				reg = CFG_COMP(MT8195, ctx->param, rdma.ufo_dec_c);  in config_rdma_frame()
142 				else if (CFG_CHECK(MT8195, p_id))  in config_rdma_frame()
143 					reg = CFG_COMP(MT8195, ctx->param, rdma.mf_bkgd_in_pxl);  in config_rdma_frame()
153 	} else if (CFG_CHECK(MT8195, p_id)) {  in config_rdma_frame()
154 		reg = CFG_COMP(MT8195, ctx->param, rdma.control);  in config_rdma_frame()
162 	else if (CFG_CHECK(MT8195, p_id))  in config_rdma_frame()
163 		reg = CFG_COMP(MT8195, ctx->param, rdma.iova[0]);  in config_rdma_frame()
168 	else if (CFG_CHECK(MT8195, p_id))  in config_rdma_frame()
169 		reg = CFG_COMP(MT8195, ctx->param, rdma.iova[1]);  in config_rdma_frame()
174 	else if (CFG_CHECK(MT8195, p_id))  in config_rdma_frame()
175 		reg = CFG_COMP(MT8195, ctx->param, rdma.iova[2]);  in config_rdma_frame()
181 	else if (CFG_CHECK(MT8195, p_id))  in config_rdma_frame()
182 		reg = CFG_COMP(MT8195, ctx->param, rdma.iova_end[0]);  in config_rdma_frame()
187 	else if (CFG_CHECK(MT8195, p_id))  in config_rdma_frame()
188 		reg = CFG_COMP(MT8195, ctx->param, rdma.iova_end[1]);  in config_rdma_frame()
193 	else if (CFG_CHECK(MT8195, p_id))  in config_rdma_frame()
194 		reg = CFG_COMP(MT8195, ctx->param, rdma.iova_end[2]);  in config_rdma_frame()
200 	else if (CFG_CHECK(MT8195, p_id))  in config_rdma_frame()
201 		reg = CFG_COMP(MT8195, ctx->param, rdma.mf_bkgd);  in config_rdma_frame()
207 	else if (CFG_CHECK(MT8195, p_id))  in config_rdma_frame()
208 		reg = CFG_COMP(MT8195, ctx->param, rdma.sf_bkgd);  in config_rdma_frame()
215 	else if (CFG_CHECK(MT8195, p_id))  in config_rdma_frame()
216 		reg = CFG_COMP(MT8195, ctx->param, rdma.transform);  in config_rdma_frame()
223 	if (CFG_CHECK(MT8195, p_id))  in config_rdma_frame()
224 		reg = CFG_COMP(MT8195, ctx->param, rdma.dmabuf_con0);  in config_rdma_frame()
228 	if (CFG_CHECK(MT8195, p_id))  in config_rdma_frame()
229 		reg = CFG_COMP(MT8195, ctx->param, rdma.ultra_th_high_con0);  in config_rdma_frame()
233 	if (CFG_CHECK(MT8195, p_id))  in config_rdma_frame()
234 		reg = CFG_COMP(MT8195, ctx->param, rdma.ultra_th_low_con0);  in config_rdma_frame()
238 	if (CFG_CHECK(MT8195, p_id))  in config_rdma_frame()
239 		reg = CFG_COMP(MT8195, ctx->param, rdma.dmabuf_con1);  in config_rdma_frame()
243 	if (CFG_CHECK(MT8195, p_id))  in config_rdma_frame()
244 		reg = CFG_COMP(MT8195, ctx->param, rdma.ultra_th_high_con1);  in config_rdma_frame()
248 	if (CFG_CHECK(MT8195, p_id))  in config_rdma_frame()
249 		reg = CFG_COMP(MT8195, ctx->param, rdma.ultra_th_low_con1);  in config_rdma_frame()
253 	if (CFG_CHECK(MT8195, p_id))  in config_rdma_frame()
254 		reg = CFG_COMP(MT8195, ctx->param, rdma.dmabuf_con2);  in config_rdma_frame()
258 	if (CFG_CHECK(MT8195, p_id))  in config_rdma_frame()
259 		reg = CFG_COMP(MT8195, ctx->param, rdma.ultra_th_high_con2);  in config_rdma_frame()
263 	if (CFG_CHECK(MT8195, p_id))  in config_rdma_frame()
264 		reg = CFG_COMP(MT8195, ctx->param, rdma.ultra_th_low_con2);  in config_rdma_frame()
268 	if (CFG_CHECK(MT8195, p_id))  in config_rdma_frame()
269 		reg = CFG_COMP(MT8195, ctx->param, rdma.dmabuf_con3);  in config_rdma_frame()
295 	else if (CFG_CHECK(MT8195, p_id))  in config_rdma_subfrm()
296 		reg = CFG_COMP(MT8195, ctx->param, rdma.subfrms[index].offset[0]);  in config_rdma_subfrm()
304 			else if (CFG_CHECK(MT8195, p_id))  in config_rdma_subfrm()
305 				reg = CFG_COMP(MT8195, ctx->param, rdma.subfrms[index].offset_0_p);  in config_rdma_subfrm()
314 	else if (CFG_CHECK(MT8195, p_id))  in config_rdma_subfrm()
315 		reg = CFG_COMP(MT8195, ctx->param, rdma.subfrms[index].offset[1]);  in config_rdma_subfrm()
321 	else if (CFG_CHECK(MT8195, p_id))  in config_rdma_subfrm()
322 		reg = CFG_COMP(MT8195, ctx->param, rdma.subfrms[index].offset[2]);  in config_rdma_subfrm()
328 	else if (CFG_CHECK(MT8195, p_id))  in config_rdma_subfrm()
329 		reg = CFG_COMP(MT8195, ctx->param, rdma.subfrms[index].src);  in config_rdma_subfrm()
336 	else if (CFG_CHECK(MT8195, p_id))  in config_rdma_subfrm()
337 		reg = CFG_COMP(MT8195, ctx->param, rdma.subfrms[index].clip);  in config_rdma_subfrm()
344 	else if (CFG_CHECK(MT8195, p_id))  in config_rdma_subfrm()
345 		reg = CFG_COMP(MT8195, ctx->param, rdma.subfrms[index].clip_ofst);  in config_rdma_subfrm()
352 	} else if (CFG_CHECK(MT8195, p_id)) {  in config_rdma_subfrm()
353 		csf_l = CFG_COMP(MT8195, ctx->param, subfrms[index].in.left);  in config_rdma_subfrm()
354 		csf_r = CFG_COMP(MT8195, ctx->param, subfrms[index].in.right);  in config_rdma_subfrm()
405 	if (CFG_CHECK(MT8195, p_id)) {  in init_rsz()
430 	else if (CFG_CHECK(MT8195, p_id))  in config_rsz_frame()
431 		bypass = CFG_COMP(MT8195, ctx->param, frame.bypass);  in config_rsz_frame()
441 	else if (CFG_CHECK(MT8195, p_id))  in config_rsz_frame()
442 		reg = CFG_COMP(MT8195, ctx->param, rsz.control1);  in config_rsz_frame()
447 	else if (CFG_CHECK(MT8195, p_id))  in config_rsz_frame()
448 		reg = CFG_COMP(MT8195, ctx->param, rsz.control2);  in config_rsz_frame()
453 	else if (CFG_CHECK(MT8195, p_id))  in config_rsz_frame()
454 		reg = CFG_COMP(MT8195, ctx->param, rsz.coeff_step_x);  in config_rsz_frame()
460 	else if (CFG_CHECK(MT8195, p_id))  in config_rsz_frame()
461 		reg = CFG_COMP(MT8195, ctx->param, rsz.coeff_step_y);  in config_rsz_frame()
480 	else if (CFG_CHECK(MT8195, p_id))  in config_rsz_subfrm()
481 		reg = CFG_COMP(MT8195, ctx->param, rsz.subfrms[index].control2);  in config_rsz_subfrm()
486 	else if (CFG_CHECK(MT8195, p_id))  in config_rsz_subfrm()
487 		reg = CFG_COMP(MT8195, ctx->param, rsz.subfrms[index].src);  in config_rsz_subfrm()
493 	} else if (CFG_CHECK(MT8195, p_id)) {  in config_rsz_subfrm()
494 		csf_l = CFG_COMP(MT8195, ctx->param, subfrms[index].in.left);  in config_rsz_subfrm()
495 		csf_r = CFG_COMP(MT8195, ctx->param, subfrms[index].in.right);  in config_rsz_subfrm()
504 	else if (CFG_CHECK(MT8195, p_id))  in config_rsz_subfrm()
505 		reg = CFG_COMP(MT8195, ctx->param, subfrms[index].luma.left);  in config_rsz_subfrm()
511 	else if (CFG_CHECK(MT8195, p_id))  in config_rsz_subfrm()
512 		reg = CFG_COMP(MT8195, ctx->param, subfrms[index].luma.left_subpix);  in config_rsz_subfrm()
518 	else if (CFG_CHECK(MT8195, p_id))  in config_rsz_subfrm()
519 		reg = CFG_COMP(MT8195, ctx->param, subfrms[index].luma.top);  in config_rsz_subfrm()
525 	else if (CFG_CHECK(MT8195, p_id))  in config_rsz_subfrm()
526 		reg = CFG_COMP(MT8195, ctx->param, subfrms[index].luma.top_subpix);  in config_rsz_subfrm()
532 	else if (CFG_CHECK(MT8195, p_id))  in config_rsz_subfrm()
533 		reg = CFG_COMP(MT8195, ctx->param, subfrms[index].chroma.left);  in config_rsz_subfrm()
539 	else if (CFG_CHECK(MT8195, p_id))  in config_rsz_subfrm()
540 		reg = CFG_COMP(MT8195, ctx->param, subfrms[index].chroma.left_subpix);  in config_rsz_subfrm()
546 	else if (CFG_CHECK(MT8195, p_id))  in config_rsz_subfrm()
547 		reg = CFG_COMP(MT8195, ctx->param, rsz.subfrms[index].clip);  in config_rsz_subfrm()
550 	if (CFG_CHECK(MT8195, p_id)) {  in config_rsz_subfrm()
567 		if (CFG_CHECK(MT8195, p_id))  in config_rsz_subfrm()
568 			reg = CFG_COMP(MT8195, ctx->param, rsz.subfrms[index].rsz_switch);  in config_rsz_subfrm()
574 		if (CFG_CHECK(MT8195, p_id))  in config_rsz_subfrm()
575 			reg = CFG_COMP(MT8195, ctx->param, rsz.subfrms[index].merge_cfg);  in config_rsz_subfrm()
609 		} else if (CFG_CHECK(MT8195, p_id)) {  in advance_rsz_subfrm()
610 			csf_l = CFG_COMP(MT8195, ctx->param, subfrms[index].in.left);  in advance_rsz_subfrm()
611 			csf_r = CFG_COMP(MT8195, ctx->param, subfrms[index].in.right);  in advance_rsz_subfrm()
640 	if (CFG_CHECK(MT8195, p_id))  in init_wrot()
660 	else if (CFG_CHECK(MT8195, p_id))  in config_wrot_frame()
661 		reg = CFG_COMP(MT8195, ctx->param, wrot.iova[0]);  in config_wrot_frame()
666 	else if (CFG_CHECK(MT8195, p_id))  in config_wrot_frame()
667 		reg = CFG_COMP(MT8195, ctx->param, wrot.iova[1]);  in config_wrot_frame()
672 	else if (CFG_CHECK(MT8195, p_id))  in config_wrot_frame()
673 		reg = CFG_COMP(MT8195, ctx->param, wrot.iova[2]);  in config_wrot_frame()
677 		if (CFG_CHECK(MT8195, p_id))  in config_wrot_frame()
678 			reg = CFG_COMP(MT8195, ctx->param, wrot.scan_10bit);  in config_wrot_frame()
682 		if (CFG_CHECK(MT8195, p_id))  in config_wrot_frame()
683 			reg = CFG_COMP(MT8195, ctx->param, wrot.pending_zero);  in config_wrot_frame()
688 	if (CFG_CHECK(MT8195, p_id)) {  in config_wrot_frame()
689 		reg = CFG_COMP(MT8195, ctx->param, wrot.bit_number);  in config_wrot_frame()
697 	else if (CFG_CHECK(MT8195, p_id))  in config_wrot_frame()
698 		reg = CFG_COMP(MT8195, ctx->param, wrot.control);  in config_wrot_frame()
702 	if (CFG_CHECK(MT8195, p_id)) {  in config_wrot_frame()
703 		reg = CFG_COMP(MT8195, ctx->param, wrot.pre_ultra);  in config_wrot_frame()
711 	else if (CFG_CHECK(MT8195, p_id))  in config_wrot_frame()
712 		reg = CFG_COMP(MT8195, ctx->param, wrot.stride[0]);  in config_wrot_frame()
718 	else if (CFG_CHECK(MT8195, p_id))  in config_wrot_frame()
719 		reg = CFG_COMP(MT8195, ctx->param, wrot.stride[1]);  in config_wrot_frame()
724 	else if (CFG_CHECK(MT8195, p_id))  in config_wrot_frame()
725 		reg = CFG_COMP(MT8195, ctx->param, wrot.stride[2]);  in config_wrot_frame()
731 	else if (CFG_CHECK(MT8195, p_id))  in config_wrot_frame()
732 		reg = CFG_COMP(MT8195, ctx->param, wrot.mat_ctrl);  in config_wrot_frame()
745 	else if (CFG_CHECK(MT8195, p_id))  in config_wrot_frame()
746 		reg = CFG_COMP(MT8195, ctx->param, wrot.fifo_test);  in config_wrot_frame()
756 		else if (CFG_CHECK(MT8195, p_id))  in config_wrot_frame()
757 			reg = CFG_COMP(MT8195, ctx->param, wrot.filter);  in config_wrot_frame()
762 		if (CFG_CHECK(MT8195, p_id))  in config_wrot_frame()
780 	else if (CFG_CHECK(MT8195, p_id))  in config_wrot_subfrm()
781 		reg = CFG_COMP(MT8195, ctx->param, wrot.subfrms[index].offset[0]);  in config_wrot_subfrm()
787 	else if (CFG_CHECK(MT8195, p_id))  in config_wrot_subfrm()
788 		reg = CFG_COMP(MT8195, ctx->param, wrot.subfrms[index].offset[1]);  in config_wrot_subfrm()
794 	else if (CFG_CHECK(MT8195, p_id))  in config_wrot_subfrm()
795 		reg = CFG_COMP(MT8195, ctx->param, wrot.subfrms[index].offset[2]);  in config_wrot_subfrm()
802 	else if (CFG_CHECK(MT8195, p_id))  in config_wrot_subfrm()
803 		reg = CFG_COMP(MT8195, ctx->param, wrot.subfrms[index].src);  in config_wrot_subfrm()
809 	else if (CFG_CHECK(MT8195, p_id))  in config_wrot_subfrm()
810 		reg = CFG_COMP(MT8195, ctx->param, wrot.subfrms[index].clip);  in config_wrot_subfrm()
815 	else if (CFG_CHECK(MT8195, p_id))  in config_wrot_subfrm()
816 		reg = CFG_COMP(MT8195, ctx->param, wrot.subfrms[index].clip_ofst);  in config_wrot_subfrm()
821 	else if (CFG_CHECK(MT8195, p_id))  in config_wrot_subfrm()
822 		reg = CFG_COMP(MT8195, ctx->param, wrot.subfrms[index].main_buf);  in config_wrot_subfrm()
1029 	if (CFG_CHECK(MT8195, p_id))  in config_tdshp_frame()
1030 		reg = CFG_COMP(MT8195, ctx->param, tdshp.cfg);  in config_tdshp_frame()
1043 	if (CFG_CHECK(MT8195, p_id))  in config_tdshp_subfrm()
1044 		reg = CFG_COMP(MT8195, ctx->param, tdshp.subfrms[index].src);  in config_tdshp_subfrm()
1047 	if (CFG_CHECK(MT8195, p_id))  in config_tdshp_subfrm()
1048 		reg = CFG_COMP(MT8195, ctx->param, tdshp.subfrms[index].clip_ofst);  in config_tdshp_subfrm()
1052 	if (CFG_CHECK(MT8195, p_id))  in config_tdshp_subfrm()
1053 		reg = CFG_COMP(MT8195, ctx->param, tdshp.subfrms[index].clip);  in config_tdshp_subfrm()
1056 	if (CFG_CHECK(MT8195, p_id))  in config_tdshp_subfrm()
1057 		reg = CFG_COMP(MT8195, ctx->param, tdshp.subfrms[index].hist_cfg_0);  in config_tdshp_subfrm()
1060 	if (CFG_CHECK(MT8195, p_id))  in config_tdshp_subfrm()
1061 		reg = CFG_COMP(MT8195, ctx->param, tdshp.subfrms[index].hist_cfg_1);  in config_tdshp_subfrm()
1104 	if (CFG_CHECK(MT8195, p_id))  in config_color_frame()
1105 		reg = CFG_COMP(MT8195, ctx->param, color.start);  in config_color_frame()
1118 	if (CFG_CHECK(MT8195, p_id))  in config_color_subfrm()
1119 		reg = CFG_COMP(MT8195, ctx->param, color.subfrms[index].in_hsize);  in config_color_subfrm()
1123 	if (CFG_CHECK(MT8195, p_id))  in config_color_subfrm()
1124 		reg = CFG_COMP(MT8195, ctx->param, color.subfrms[index].in_vsize);  in config_color_subfrm()
1198 	if (CFG_CHECK(MT8195, p_id))  in config_aal_frame()
1199 		reg = CFG_COMP(MT8195, ctx->param, aal.cfg_main);  in config_aal_frame()
1202 	if (CFG_CHECK(MT8195, p_id))  in config_aal_frame()
1203 		reg = CFG_COMP(MT8195, ctx->param, aal.cfg);  in config_aal_frame()
1216 	if (CFG_CHECK(MT8195, p_id))  in config_aal_subfrm()
1217 		reg = CFG_COMP(MT8195, ctx->param, aal.subfrms[index].src);  in config_aal_subfrm()
1220 	if (CFG_CHECK(MT8195, p_id))  in config_aal_subfrm()
1221 		reg = CFG_COMP(MT8195, ctx->param, aal.subfrms[index].clip_ofst);  in config_aal_subfrm()
1225 	if (CFG_CHECK(MT8195, p_id))  in config_aal_subfrm()
1226 		reg = CFG_COMP(MT8195, ctx->param, aal.subfrms[index].clip);  in config_aal_subfrm()
1258 	if (CFG_CHECK(MT8195, p_id))  in config_hdr_frame()
1259 		reg = CFG_COMP(MT8195, ctx->param, hdr.top);  in config_hdr_frame()
1262 	if (CFG_CHECK(MT8195, p_id))  in config_hdr_frame()
1263 		reg = CFG_COMP(MT8195, ctx->param, hdr.relay);  in config_hdr_frame()
1276 	if (CFG_CHECK(MT8195, p_id))  in config_hdr_subfrm()
1277 		reg = CFG_COMP(MT8195, ctx->param, hdr.subfrms[index].win_size);  in config_hdr_subfrm()
1280 	if (CFG_CHECK(MT8195, p_id))  in config_hdr_subfrm()
1281 		reg = CFG_COMP(MT8195, ctx->param, hdr.subfrms[index].src);  in config_hdr_subfrm()
1284 	if (CFG_CHECK(MT8195, p_id))  in config_hdr_subfrm()
1285 		reg = CFG_COMP(MT8195, ctx->param, hdr.subfrms[index].clip_ofst0);  in config_hdr_subfrm()
1288 	if (CFG_CHECK(MT8195, p_id))  in config_hdr_subfrm()
1289 		reg = CFG_COMP(MT8195, ctx->param, hdr.subfrms[index].clip_ofst1);  in config_hdr_subfrm()
1292 	if (CFG_CHECK(MT8195, p_id))  in config_hdr_subfrm()
1293 		reg = CFG_COMP(MT8195, ctx->param, hdr.subfrms[index].hist_ctrl_0);  in config_hdr_subfrm()
1296 	if (CFG_CHECK(MT8195, p_id))  in config_hdr_subfrm()
1297 		reg = CFG_COMP(MT8195, ctx->param, hdr.subfrms[index].hist_ctrl_1);  in config_hdr_subfrm()
1300 	if (CFG_CHECK(MT8195, p_id))  in config_hdr_subfrm()
1301 		reg = CFG_COMP(MT8195, ctx->param, hdr.subfrms[index].hdr_top);  in config_hdr_subfrm()
1305 	if (CFG_CHECK(MT8195, p_id))  in config_hdr_subfrm()
1306 		reg = CFG_COMP(MT8195, ctx->param, hdr.subfrms[index].hist_addr);  in config_hdr_subfrm()
1338 	if (CFG_CHECK(MT8195, p_id))  in config_fg_frame()
1339 		reg = CFG_COMP(MT8195, ctx->param, fg.ctrl_0);  in config_fg_frame()
1342 	if (CFG_CHECK(MT8195, p_id))  in config_fg_frame()
1343 		reg = CFG_COMP(MT8195, ctx->param, fg.ck_en);  in config_fg_frame()
1356 	if (CFG_CHECK(MT8195, p_id))  in config_fg_subfrm()
1357 		reg = CFG_COMP(MT8195, ctx->param, fg.subfrms[index].info_0);  in config_fg_subfrm()
1360 	if (CFG_CHECK(MT8195, p_id))  in config_fg_subfrm()
1361 		reg = CFG_COMP(MT8195, ctx->param, fg.subfrms[index].info_1);  in config_fg_subfrm()
1396 	if (CFG_CHECK(MT8195, p_id))  in config_ovl_frame()
1397 		reg = CFG_COMP(MT8195, ctx->param, ovl.L0_con);  in config_ovl_frame()
1400 	if (CFG_CHECK(MT8195, p_id))  in config_ovl_frame()
1401 		reg = CFG_COMP(MT8195, ctx->param, ovl.src_con);  in config_ovl_frame()
1414 	if (CFG_CHECK(MT8195, p_id))  in config_ovl_subfrm()
1415 		reg = CFG_COMP(MT8195, ctx->param, ovl.subfrms[index].L0_src_size);  in config_ovl_subfrm()
1419 	if (CFG_CHECK(MT8195, p_id))  in config_ovl_subfrm()
1420 		reg = CFG_COMP(MT8195, ctx->param, ovl.subfrms[index].roi_size);  in config_ovl_subfrm()
1453 	if (CFG_CHECK(MT8195, p_id))  in config_pad_subfrm()
1454 		reg = CFG_COMP(MT8195, ctx->param, pad.subfrms[index].pic_size);  in config_pad_subfrm()
1498 		.compatible = "mediatek,mt8195-mdp3-rdma",
1501 		.compatible = "mediatek,mt8195-mdp3-split",
1504 		.compatible = "mediatek,mt8195-mdp3-stitch",
1507 		.compatible = "mediatek,mt8195-mdp3-fg",
1510 		.compatible = "mediatek,mt8195-mdp3-hdr",
1513 		.compatible = "mediatek,mt8195-mdp3-aal",
1516 		.compatible = "mediatek,mt8195-mdp3-merge",
1519 		.compatible = "mediatek,mt8195-mdp3-tdshp",
1522 		.compatible = "mediatek,mt8195-mdp3-color",
1525 		.compatible = "mediatek,mt8195-mdp3-ovl",
1528 		.compatible = "mediatek,mt8195-mdp3-padding",
1531 		.compatible = "mediatek,mt8195-mdp3-tcc",
1977 	else if (CFG_CHECK(MT8195, p_id))  in mdp_comp_ctx_config()
1978 		arg = CFG_COMP(MT8195, param, type);  in mdp_comp_ctx_config()
1996 	else if (CFG_CHECK(MT8195, p_id))  in mdp_comp_ctx_config()
1997 		arg = CFG_COMP(MT8195, param, input);  in mdp_comp_ctx_config()
2003 	else if (CFG_CHECK(MT8195, p_id))  in mdp_comp_ctx_config()
2004 		idx = CFG_COMP(MT8195, param, num_outputs);  in mdp_comp_ctx_config()
2010 		else if (CFG_CHECK(MT8195, p_id))  in mdp_comp_ctx_config()
2011 			arg = CFG_COMP(MT8195, param, outputs[i]);  in mdp_comp_ctx_config()