Lines Matching +full:gce +full:- +full:events
1 // SPDX-License-Identifier: GPL-2.0-only
4 * Author: Ping-Hsun Wu <ping-[email protected]>
11 #include "mtk-mdp3-cfg.h"
12 #include "mtk-mdp3-comp.h"
13 #include "mtk-mdp3-core.h"
14 #include "mtk-mdp3-regs.h"
39 return ctx->comp->mdp_dev->mdp_data->mdp_cfg; in __get_plat_cfg()
47 rdma0 = mdp_cfg_get_id_inner(ctx->comp->mdp_dev, MDP_COMP_RDMA0); in get_comp_flag()
48 rsz1 = mdp_cfg_get_id_inner(ctx->comp->mdp_dev, MDP_COMP_RSZ1); in get_comp_flag()
52 if (mdp_cfg && mdp_cfg->rdma_rsz1_sram_sharing) in get_comp_flag()
53 if (ctx->comp->inner_id == rdma0) in get_comp_flag()
56 return BIT(ctx->comp->inner_id); in get_comp_flag()
62 phys_addr_t base = ctx->comp->reg_base; in init_rdma()
63 u8 subsys_id = ctx->comp->subsys_id; in init_rdma()
66 rdma0 = mdp_cfg_get_id_inner(ctx->comp->mdp_dev, MDP_COMP_RDMA0); in init_rdma()
68 return -EINVAL; in init_rdma()
70 if (mdp_cfg && mdp_cfg->rdma_support_10bit) { in init_rdma()
71 struct mdp_comp *prz1 = ctx->comp->mdp_dev->comp[MDP_COMP_RSZ1]; in init_rdma()
74 if (ctx->comp->inner_id == rdma0 && prz1) in init_rdma()
75 MM_REG_WRITE_MASK(cmd, subsys_id, prz1->reg_base, in init_rdma()
91 u32 colorformat = ctx->input->buffer.format.colorformat; in config_rdma_frame()
94 phys_addr_t base = ctx->comp->reg_base; in config_rdma_frame()
95 u8 subsys_id = ctx->comp->subsys_id; in config_rdma_frame()
99 if (mdp_cfg && mdp_cfg->rdma_support_10bit) { in config_rdma_frame()
111 (1 << 16), //enable pre-ultra in config_rdma_frame()
116 reg = CFG_COMP(MT8183, ctx->param, rdma.src_ctrl); in config_rdma_frame()
118 reg = CFG_COMP(MT8195, ctx->param, rdma.src_ctrl); in config_rdma_frame()
122 if (mdp_cfg->rdma_support_10bit && en_ufo) { in config_rdma_frame()
125 reg = CFG_COMP(MT8183, ctx->param, rdma.ufo_dec_y); in config_rdma_frame()
127 reg = CFG_COMP(MT8195, ctx->param, rdma.ufo_dec_y); in config_rdma_frame()
132 reg = CFG_COMP(MT8183, ctx->param, rdma.ufo_dec_c); in config_rdma_frame()
134 reg = CFG_COMP(MT8195, ctx->param, rdma.ufo_dec_c); in config_rdma_frame()
141 reg = CFG_COMP(MT8183, ctx->param, rdma.mf_bkgd_in_pxl); in config_rdma_frame()
143 reg = CFG_COMP(MT8195, ctx->param, rdma.mf_bkgd_in_pxl); in config_rdma_frame()
151 reg = CFG_COMP(MT8183, ctx->param, rdma.control); in config_rdma_frame()
154 reg = CFG_COMP(MT8195, ctx->param, rdma.control); in config_rdma_frame()
161 reg = CFG_COMP(MT8183, ctx->param, rdma.iova[0]); in config_rdma_frame()
163 reg = CFG_COMP(MT8195, ctx->param, rdma.iova[0]); in config_rdma_frame()
167 reg = CFG_COMP(MT8183, ctx->param, rdma.iova[1]); in config_rdma_frame()
169 reg = CFG_COMP(MT8195, ctx->param, rdma.iova[1]); in config_rdma_frame()
173 reg = CFG_COMP(MT8183, ctx->param, rdma.iova[2]); in config_rdma_frame()
175 reg = CFG_COMP(MT8195, ctx->param, rdma.iova[2]); in config_rdma_frame()
180 reg = CFG_COMP(MT8183, ctx->param, rdma.iova_end[0]); in config_rdma_frame()
182 reg = CFG_COMP(MT8195, ctx->param, rdma.iova_end[0]); in config_rdma_frame()
186 reg = CFG_COMP(MT8183, ctx->param, rdma.iova_end[1]); in config_rdma_frame()
188 reg = CFG_COMP(MT8195, ctx->param, rdma.iova_end[1]); in config_rdma_frame()
192 reg = CFG_COMP(MT8183, ctx->param, rdma.iova_end[2]); in config_rdma_frame()
194 reg = CFG_COMP(MT8195, ctx->param, rdma.iova_end[2]); in config_rdma_frame()
199 reg = CFG_COMP(MT8183, ctx->param, rdma.mf_bkgd); in config_rdma_frame()
201 reg = CFG_COMP(MT8195, ctx->param, rdma.mf_bkgd); in config_rdma_frame()
206 reg = CFG_COMP(MT8183, ctx->param, rdma.sf_bkgd); in config_rdma_frame()
208 reg = CFG_COMP(MT8195, ctx->param, rdma.sf_bkgd); in config_rdma_frame()
214 reg = CFG_COMP(MT8183, ctx->param, rdma.transform); in config_rdma_frame()
216 reg = CFG_COMP(MT8195, ctx->param, rdma.transform); in config_rdma_frame()
220 if (!mdp_cfg || !mdp_cfg->rdma_esl_setting) in config_rdma_frame()
224 reg = CFG_COMP(MT8195, ctx->param, rdma.dmabuf_con0); in config_rdma_frame()
229 reg = CFG_COMP(MT8195, ctx->param, rdma.ultra_th_high_con0); in config_rdma_frame()
234 reg = CFG_COMP(MT8195, ctx->param, rdma.ultra_th_low_con0); in config_rdma_frame()
239 reg = CFG_COMP(MT8195, ctx->param, rdma.dmabuf_con1); in config_rdma_frame()
244 reg = CFG_COMP(MT8195, ctx->param, rdma.ultra_th_high_con1); in config_rdma_frame()
249 reg = CFG_COMP(MT8195, ctx->param, rdma.ultra_th_low_con1); in config_rdma_frame()
254 reg = CFG_COMP(MT8195, ctx->param, rdma.dmabuf_con2); in config_rdma_frame()
259 reg = CFG_COMP(MT8195, ctx->param, rdma.ultra_th_high_con2); in config_rdma_frame()
264 reg = CFG_COMP(MT8195, ctx->param, rdma.ultra_th_low_con2); in config_rdma_frame()
269 reg = CFG_COMP(MT8195, ctx->param, rdma.dmabuf_con3); in config_rdma_frame()
281 u32 colorformat = ctx->input->buffer.format.colorformat; in config_rdma_subfrm()
284 phys_addr_t base = ctx->comp->reg_base; in config_rdma_subfrm()
285 u8 subsys_id = ctx->comp->subsys_id; in config_rdma_subfrm()
294 reg = CFG_COMP(MT8183, ctx->param, rdma.subfrms[index].offset[0]); in config_rdma_subfrm()
296 reg = CFG_COMP(MT8195, ctx->param, rdma.subfrms[index].offset[0]); in config_rdma_subfrm()
301 if (mdp_cfg->rdma_support_10bit && block10bit && en_ufo) { in config_rdma_subfrm()
303 reg = CFG_COMP(MT8183, ctx->param, rdma.subfrms[index].offset_0_p); in config_rdma_subfrm()
305 reg = CFG_COMP(MT8195, ctx->param, rdma.subfrms[index].offset_0_p); in config_rdma_subfrm()
313 reg = CFG_COMP(MT8183, ctx->param, rdma.subfrms[index].offset[1]); in config_rdma_subfrm()
315 reg = CFG_COMP(MT8195, ctx->param, rdma.subfrms[index].offset[1]); in config_rdma_subfrm()
320 reg = CFG_COMP(MT8183, ctx->param, rdma.subfrms[index].offset[2]); in config_rdma_subfrm()
322 reg = CFG_COMP(MT8195, ctx->param, rdma.subfrms[index].offset[2]); in config_rdma_subfrm()
327 reg = CFG_COMP(MT8183, ctx->param, rdma.subfrms[index].src); in config_rdma_subfrm()
329 reg = CFG_COMP(MT8195, ctx->param, rdma.subfrms[index].src); in config_rdma_subfrm()
335 reg = CFG_COMP(MT8183, ctx->param, rdma.subfrms[index].clip); in config_rdma_subfrm()
337 reg = CFG_COMP(MT8195, ctx->param, rdma.subfrms[index].clip); in config_rdma_subfrm()
343 reg = CFG_COMP(MT8183, ctx->param, rdma.subfrms[index].clip_ofst); in config_rdma_subfrm()
345 reg = CFG_COMP(MT8195, ctx->param, rdma.subfrms[index].clip_ofst); in config_rdma_subfrm()
350 csf_l = CFG_COMP(MT8183, ctx->param, subfrms[index].in.left); in config_rdma_subfrm()
351 csf_r = CFG_COMP(MT8183, ctx->param, subfrms[index].in.right); in config_rdma_subfrm()
353 csf_l = CFG_COMP(MT8195, ctx->param, subfrms[index].in.left); in config_rdma_subfrm()
354 csf_r = CFG_COMP(MT8195, ctx->param, subfrms[index].in.right); in config_rdma_subfrm()
356 if (mdp_cfg && mdp_cfg->rdma_upsample_repeat_only) in config_rdma_subfrm()
357 if ((csf_r - csf_l + 1) > 320) in config_rdma_subfrm()
367 struct device *dev = &ctx->comp->mdp_dev->pdev->dev; in wait_rdma_event()
368 phys_addr_t base = ctx->comp->reg_base; in wait_rdma_event()
369 u8 subsys_id = ctx->comp->subsys_id; in wait_rdma_event()
372 return -EINVAL; in wait_rdma_event()
374 if (ctx->comp->alias_id >= mdp_cfg->rdma_event_num) { in wait_rdma_event()
375 dev_err(dev, "Invalid RDMA event %d\n", ctx->comp->alias_id); in wait_rdma_event()
376 return -EINVAL; in wait_rdma_event()
379 MM_REG_WAIT(cmd, ctx->comp->gce_event[MDP_GCE_EVENT_EOF]); in wait_rdma_event()
396 phys_addr_t base = ctx->comp->reg_base; in init_rsz()
397 u8 subsys_id = ctx->comp->subsys_id; in init_rsz()
408 dev = ctx->comp->mdp_dev->mm_subsys[MDP_MM_SUBSYS_1].mmsys; in init_rsz()
420 phys_addr_t base = ctx->comp->reg_base; in config_rsz_frame()
421 u8 subsys_id = ctx->comp->subsys_id; in config_rsz_frame()
425 if (mdp_cfg && mdp_cfg->rsz_etc_control) in config_rsz_frame()
429 bypass = CFG_COMP(MT8183, ctx->param, frame.bypass); in config_rsz_frame()
431 bypass = CFG_COMP(MT8195, ctx->param, frame.bypass); in config_rsz_frame()
440 reg = CFG_COMP(MT8183, ctx->param, rsz.control1); in config_rsz_frame()
442 reg = CFG_COMP(MT8195, ctx->param, rsz.control1); in config_rsz_frame()
446 reg = CFG_COMP(MT8183, ctx->param, rsz.control2); in config_rsz_frame()
448 reg = CFG_COMP(MT8195, ctx->param, rsz.control2); in config_rsz_frame()
452 reg = CFG_COMP(MT8183, ctx->param, rsz.coeff_step_x); in config_rsz_frame()
454 reg = CFG_COMP(MT8195, ctx->param, rsz.coeff_step_x); in config_rsz_frame()
459 reg = CFG_COMP(MT8183, ctx->param, rsz.coeff_step_y); in config_rsz_frame()
461 reg = CFG_COMP(MT8195, ctx->param, rsz.coeff_step_y); in config_rsz_frame()
472 phys_addr_t base = ctx->comp->reg_base; in config_rsz_subfrm()
473 u8 subsys_id = ctx->comp->subsys_id; in config_rsz_subfrm()
479 reg = CFG_COMP(MT8183, ctx->param, rsz.subfrms[index].control2); in config_rsz_subfrm()
481 reg = CFG_COMP(MT8195, ctx->param, rsz.subfrms[index].control2); in config_rsz_subfrm()
485 reg = CFG_COMP(MT8183, ctx->param, rsz.subfrms[index].src); in config_rsz_subfrm()
487 reg = CFG_COMP(MT8195, ctx->param, rsz.subfrms[index].src); in config_rsz_subfrm()
491 csf_l = CFG_COMP(MT8183, ctx->param, subfrms[index].in.left); in config_rsz_subfrm()
492 csf_r = CFG_COMP(MT8183, ctx->param, subfrms[index].in.right); in config_rsz_subfrm()
494 csf_l = CFG_COMP(MT8195, ctx->param, subfrms[index].in.left); in config_rsz_subfrm()
495 csf_r = CFG_COMP(MT8195, ctx->param, subfrms[index].in.right); in config_rsz_subfrm()
497 if (mdp_cfg && mdp_cfg->rsz_disable_dcm_small_sample) in config_rsz_subfrm()
498 if ((csf_r - csf_l + 1) <= 16) in config_rsz_subfrm()
503 reg = CFG_COMP(MT8183, ctx->param, subfrms[index].luma.left); in config_rsz_subfrm()
505 reg = CFG_COMP(MT8195, ctx->param, subfrms[index].luma.left); in config_rsz_subfrm()
510 reg = CFG_COMP(MT8183, ctx->param, subfrms[index].luma.left_subpix); in config_rsz_subfrm()
512 reg = CFG_COMP(MT8195, ctx->param, subfrms[index].luma.left_subpix); in config_rsz_subfrm()
517 reg = CFG_COMP(MT8183, ctx->param, subfrms[index].luma.top); in config_rsz_subfrm()
519 reg = CFG_COMP(MT8195, ctx->param, subfrms[index].luma.top); in config_rsz_subfrm()
524 reg = CFG_COMP(MT8183, ctx->param, subfrms[index].luma.top_subpix); in config_rsz_subfrm()
526 reg = CFG_COMP(MT8195, ctx->param, subfrms[index].luma.top_subpix); in config_rsz_subfrm()
531 reg = CFG_COMP(MT8183, ctx->param, subfrms[index].chroma.left); in config_rsz_subfrm()
533 reg = CFG_COMP(MT8195, ctx->param, subfrms[index].chroma.left); in config_rsz_subfrm()
538 reg = CFG_COMP(MT8183, ctx->param, subfrms[index].chroma.left_subpix); in config_rsz_subfrm()
540 reg = CFG_COMP(MT8195, ctx->param, subfrms[index].chroma.left_subpix); in config_rsz_subfrm()
545 reg = CFG_COMP(MT8183, ctx->param, rsz.subfrms[index].clip); in config_rsz_subfrm()
547 reg = CFG_COMP(MT8195, ctx->param, rsz.subfrms[index].clip); in config_rsz_subfrm()
553 const struct mtk_mdp_driver_data *data = ctx->comp->mdp_dev->mdp_data; in config_rsz_subfrm()
554 enum mtk_mdp_comp_id public_id = ctx->comp->public_id; in config_rsz_subfrm()
558 merge = ctx->comp->mdp_dev->comp[MDP_COMP_MERGE2]; in config_rsz_subfrm()
561 merge = ctx->comp->mdp_dev->comp[MDP_COMP_MERGE3]; in config_rsz_subfrm()
568 reg = CFG_COMP(MT8195, ctx->param, rsz.subfrms[index].rsz_switch); in config_rsz_subfrm()
570 id = data->comp_data[public_id].match.alias_id; in config_rsz_subfrm()
571 dev = ctx->comp->mdp_dev->mm_subsys[MDP_MM_SUBSYS_1].mmsys; in config_rsz_subfrm()
575 reg = CFG_COMP(MT8195, ctx->param, rsz.subfrms[index].merge_cfg); in config_rsz_subfrm()
576 MM_REG_WRITE(cmd, merge->subsys_id, merge->reg_base, in config_rsz_subfrm()
578 MM_REG_WRITE(cmd, merge->subsys_id, merge->reg_base, in config_rsz_subfrm()
580 MM_REG_WRITE(cmd, merge->subsys_id, merge->reg_base, in config_rsz_subfrm()
582 MM_REG_WRITE(cmd, merge->subsys_id, merge->reg_base, in config_rsz_subfrm()
586 MM_REG_WRITE(cmd, merge->subsys_id, merge->reg_base, in config_rsz_subfrm()
588 MM_REG_WRITE(cmd, merge->subsys_id, merge->reg_base, in config_rsz_subfrm()
601 if (mdp_cfg && mdp_cfg->rsz_disable_dcm_small_sample) { in advance_rsz_subfrm()
602 phys_addr_t base = ctx->comp->reg_base; in advance_rsz_subfrm()
603 u8 subsys_id = ctx->comp->subsys_id; in advance_rsz_subfrm()
607 csf_l = CFG_COMP(MT8183, ctx->param, subfrms[index].in.left); in advance_rsz_subfrm()
608 csf_r = CFG_COMP(MT8183, ctx->param, subfrms[index].in.right); in advance_rsz_subfrm()
610 csf_l = CFG_COMP(MT8195, ctx->param, subfrms[index].in.left); in advance_rsz_subfrm()
611 csf_r = CFG_COMP(MT8195, ctx->param, subfrms[index].in.right); in advance_rsz_subfrm()
614 if ((csf_r - csf_l + 1) <= 16) in advance_rsz_subfrm()
632 phys_addr_t base = ctx->comp->reg_base; in init_wrot()
633 u8 subsys_id = ctx->comp->subsys_id; in init_wrot()
653 phys_addr_t base = ctx->comp->reg_base; in config_wrot_frame()
654 u8 subsys_id = ctx->comp->subsys_id; in config_wrot_frame()
659 reg = CFG_COMP(MT8183, ctx->param, wrot.iova[0]); in config_wrot_frame()
661 reg = CFG_COMP(MT8195, ctx->param, wrot.iova[0]); in config_wrot_frame()
665 reg = CFG_COMP(MT8183, ctx->param, wrot.iova[1]); in config_wrot_frame()
667 reg = CFG_COMP(MT8195, ctx->param, wrot.iova[1]); in config_wrot_frame()
671 reg = CFG_COMP(MT8183, ctx->param, wrot.iova[2]); in config_wrot_frame()
673 reg = CFG_COMP(MT8195, ctx->param, wrot.iova[2]); in config_wrot_frame()
676 if (mdp_cfg && mdp_cfg->wrot_support_10bit) { in config_wrot_frame()
678 reg = CFG_COMP(MT8195, ctx->param, wrot.scan_10bit); in config_wrot_frame()
683 reg = CFG_COMP(MT8195, ctx->param, wrot.pending_zero); in config_wrot_frame()
689 reg = CFG_COMP(MT8195, ctx->param, wrot.bit_number); in config_wrot_frame()
696 reg = CFG_COMP(MT8183, ctx->param, wrot.control); in config_wrot_frame()
698 reg = CFG_COMP(MT8195, ctx->param, wrot.control); in config_wrot_frame()
701 /* Write pre-ultra threshold */ in config_wrot_frame()
703 reg = CFG_COMP(MT8195, ctx->param, wrot.pre_ultra); in config_wrot_frame()
710 reg = CFG_COMP(MT8183, ctx->param, wrot.stride[0]); in config_wrot_frame()
712 reg = CFG_COMP(MT8195, ctx->param, wrot.stride[0]); in config_wrot_frame()
717 reg = CFG_COMP(MT8183, ctx->param, wrot.stride[1]); in config_wrot_frame()
719 reg = CFG_COMP(MT8195, ctx->param, wrot.stride[1]); in config_wrot_frame()
723 reg = CFG_COMP(MT8183, ctx->param, wrot.stride[2]); in config_wrot_frame()
725 reg = CFG_COMP(MT8195, ctx->param, wrot.stride[2]); in config_wrot_frame()
730 reg = CFG_COMP(MT8183, ctx->param, wrot.mat_ctrl); in config_wrot_frame()
732 reg = CFG_COMP(MT8195, ctx->param, wrot.mat_ctrl); in config_wrot_frame()
744 reg = CFG_COMP(MT8183, ctx->param, wrot.fifo_test); in config_wrot_frame()
746 reg = CFG_COMP(MT8195, ctx->param, wrot.fifo_test); in config_wrot_frame()
753 if (mdp_cfg && mdp_cfg->wrot_filter_constraint) { in config_wrot_frame()
755 reg = CFG_COMP(MT8183, ctx->param, wrot.filter); in config_wrot_frame()
757 reg = CFG_COMP(MT8195, ctx->param, wrot.filter); in config_wrot_frame()
773 phys_addr_t base = ctx->comp->reg_base; in config_wrot_subfrm()
774 u8 subsys_id = ctx->comp->subsys_id; in config_wrot_subfrm()
779 reg = CFG_COMP(MT8183, ctx->param, wrot.subfrms[index].offset[0]); in config_wrot_subfrm()
781 reg = CFG_COMP(MT8195, ctx->param, wrot.subfrms[index].offset[0]); in config_wrot_subfrm()
786 reg = CFG_COMP(MT8183, ctx->param, wrot.subfrms[index].offset[1]); in config_wrot_subfrm()
788 reg = CFG_COMP(MT8195, ctx->param, wrot.subfrms[index].offset[1]); in config_wrot_subfrm()
793 reg = CFG_COMP(MT8183, ctx->param, wrot.subfrms[index].offset[2]); in config_wrot_subfrm()
795 reg = CFG_COMP(MT8195, ctx->param, wrot.subfrms[index].offset[2]); in config_wrot_subfrm()
801 reg = CFG_COMP(MT8183, ctx->param, wrot.subfrms[index].src); in config_wrot_subfrm()
803 reg = CFG_COMP(MT8195, ctx->param, wrot.subfrms[index].src); in config_wrot_subfrm()
808 reg = CFG_COMP(MT8183, ctx->param, wrot.subfrms[index].clip); in config_wrot_subfrm()
810 reg = CFG_COMP(MT8195, ctx->param, wrot.subfrms[index].clip); in config_wrot_subfrm()
814 reg = CFG_COMP(MT8183, ctx->param, wrot.subfrms[index].clip_ofst); in config_wrot_subfrm()
816 reg = CFG_COMP(MT8195, ctx->param, wrot.subfrms[index].clip_ofst); in config_wrot_subfrm()
820 reg = CFG_COMP(MT8183, ctx->param, wrot.subfrms[index].main_buf); in config_wrot_subfrm()
822 reg = CFG_COMP(MT8195, ctx->param, wrot.subfrms[index].main_buf); in config_wrot_subfrm()
835 struct device *dev = &ctx->comp->mdp_dev->pdev->dev; in wait_wrot_event()
836 phys_addr_t base = ctx->comp->reg_base; in wait_wrot_event()
837 u8 subsys_id = ctx->comp->subsys_id; in wait_wrot_event()
840 return -EINVAL; in wait_wrot_event()
842 if (ctx->comp->alias_id >= mdp_cfg->wrot_event_num) { in wait_wrot_event()
843 dev_err(dev, "Invalid WROT event %d!\n", ctx->comp->alias_id); in wait_wrot_event()
844 return -EINVAL; in wait_wrot_event()
847 MM_REG_WAIT(cmd, ctx->comp->gce_event[MDP_GCE_EVENT_EOF]); in wait_wrot_event()
849 if (mdp_cfg && mdp_cfg->wrot_filter_constraint) in wait_wrot_event()
869 phys_addr_t base = ctx->comp->reg_base; in init_wdma()
870 u8 subsys_id = ctx->comp->subsys_id; in init_wdma()
883 phys_addr_t base = ctx->comp->reg_base; in config_wdma_frame()
884 u8 subsys_id = ctx->comp->subsys_id; in config_wdma_frame()
891 reg = CFG_COMP(MT8183, ctx->param, wdma.wdma_cfg); in config_wdma_frame()
895 reg = CFG_COMP(MT8183, ctx->param, wdma.iova[0]); in config_wdma_frame()
898 reg = CFG_COMP(MT8183, ctx->param, wdma.iova[1]); in config_wdma_frame()
901 reg = CFG_COMP(MT8183, ctx->param, wdma.iova[2]); in config_wdma_frame()
905 reg = CFG_COMP(MT8183, ctx->param, wdma.w_in_byte); in config_wdma_frame()
910 reg = CFG_COMP(MT8183, ctx->param, wdma.uv_stride); in config_wdma_frame()
923 phys_addr_t base = ctx->comp->reg_base; in config_wdma_subfrm()
924 u8 subsys_id = ctx->comp->subsys_id; in config_wdma_subfrm()
929 reg = CFG_COMP(MT8183, ctx->param, wdma.subfrms[index].offset[0]); in config_wdma_subfrm()
934 reg = CFG_COMP(MT8183, ctx->param, wdma.subfrms[index].offset[1]); in config_wdma_subfrm()
939 reg = CFG_COMP(MT8183, ctx->param, wdma.subfrms[index].offset[2]); in config_wdma_subfrm()
944 reg = CFG_COMP(MT8183, ctx->param, wdma.subfrms[index].src); in config_wdma_subfrm()
948 reg = CFG_COMP(MT8183, ctx->param, wdma.subfrms[index].clip); in config_wdma_subfrm()
952 reg = CFG_COMP(MT8183, ctx->param, wdma.subfrms[index].clip_ofst); in config_wdma_subfrm()
963 phys_addr_t base = ctx->comp->reg_base; in wait_wdma_event()
964 u8 subsys_id = ctx->comp->subsys_id; in wait_wdma_event()
966 MM_REG_WAIT(cmd, ctx->comp->gce_event[MDP_GCE_EVENT_EOF]); in wait_wdma_event()
983 phys_addr_t base = ctx->comp->reg_base; in reset_luma_hist()
984 u16 subsys_id = ctx->comp->subsys_id; in reset_luma_hist()
988 return -EINVAL; in reset_luma_hist()
990 hist_num = mdp_cfg->tdshp_hist_num; in reset_luma_hist()
997 if (mdp_cfg->tdshp_constrain) in reset_luma_hist()
1001 if (mdp_cfg->tdshp_contour) in reset_luma_hist()
1011 phys_addr_t base = ctx->comp->reg_base; in init_tdshp()
1012 u16 subsys_id = ctx->comp->subsys_id; in init_tdshp()
1025 phys_addr_t base = ctx->comp->reg_base; in config_tdshp_frame()
1026 u16 subsys_id = ctx->comp->subsys_id; in config_tdshp_frame()
1030 reg = CFG_COMP(MT8195, ctx->param, tdshp.cfg); in config_tdshp_frame()
1039 phys_addr_t base = ctx->comp->reg_base; in config_tdshp_subfrm()
1040 u16 subsys_id = ctx->comp->subsys_id; in config_tdshp_subfrm()
1044 reg = CFG_COMP(MT8195, ctx->param, tdshp.subfrms[index].src); in config_tdshp_subfrm()
1048 reg = CFG_COMP(MT8195, ctx->param, tdshp.subfrms[index].clip_ofst); in config_tdshp_subfrm()
1053 reg = CFG_COMP(MT8195, ctx->param, tdshp.subfrms[index].clip); in config_tdshp_subfrm()
1057 reg = CFG_COMP(MT8195, ctx->param, tdshp.subfrms[index].hist_cfg_0); in config_tdshp_subfrm()
1061 reg = CFG_COMP(MT8195, ctx->param, tdshp.subfrms[index].hist_cfg_1); in config_tdshp_subfrm()
1076 phys_addr_t base = ctx->comp->reg_base; in init_color()
1077 u16 subsys_id = ctx->comp->subsys_id; in init_color()
1100 phys_addr_t base = ctx->comp->reg_base; in config_color_frame()
1101 u16 subsys_id = ctx->comp->subsys_id; in config_color_frame()
1105 reg = CFG_COMP(MT8195, ctx->param, color.start); in config_color_frame()
1114 phys_addr_t base = ctx->comp->reg_base; in config_color_subfrm()
1115 u16 subsys_id = ctx->comp->subsys_id; in config_color_subfrm()
1119 reg = CFG_COMP(MT8195, ctx->param, color.subfrms[index].in_hsize); in config_color_subfrm()
1124 reg = CFG_COMP(MT8195, ctx->param, color.subfrms[index].in_vsize); in config_color_subfrm()
1140 phys_addr_t base = ctx->comp->reg_base; in init_ccorr()
1141 u8 subsys_id = ctx->comp->subsys_id; in init_ccorr()
1153 phys_addr_t base = ctx->comp->reg_base; in config_ccorr_subfrm()
1154 u8 subsys_id = ctx->comp->subsys_id; in config_ccorr_subfrm()
1160 csf_l = CFG_COMP(MT8183, ctx->param, subfrms[index].in.left); in config_ccorr_subfrm()
1161 csf_r = CFG_COMP(MT8183, ctx->param, subfrms[index].in.right); in config_ccorr_subfrm()
1162 csf_t = CFG_COMP(MT8183, ctx->param, subfrms[index].in.top); in config_ccorr_subfrm()
1163 csf_b = CFG_COMP(MT8183, ctx->param, subfrms[index].in.bottom); in config_ccorr_subfrm()
1166 hsize = csf_r - csf_l + 1; in config_ccorr_subfrm()
1167 vsize = csf_b - csf_t + 1; in config_ccorr_subfrm()
1181 phys_addr_t base = ctx->comp->reg_base; in init_aal()
1182 u16 subsys_id = ctx->comp->subsys_id; in init_aal()
1194 phys_addr_t base = ctx->comp->reg_base; in config_aal_frame()
1195 u16 subsys_id = ctx->comp->subsys_id; in config_aal_frame()
1199 reg = CFG_COMP(MT8195, ctx->param, aal.cfg_main); in config_aal_frame()
1203 reg = CFG_COMP(MT8195, ctx->param, aal.cfg); in config_aal_frame()
1212 phys_addr_t base = ctx->comp->reg_base; in config_aal_subfrm()
1213 u16 subsys_id = ctx->comp->subsys_id; in config_aal_subfrm()
1217 reg = CFG_COMP(MT8195, ctx->param, aal.subfrms[index].src); in config_aal_subfrm()
1221 reg = CFG_COMP(MT8195, ctx->param, aal.subfrms[index].clip_ofst); in config_aal_subfrm()
1226 reg = CFG_COMP(MT8195, ctx->param, aal.subfrms[index].clip); in config_aal_subfrm()
1241 phys_addr_t base = ctx->comp->reg_base; in init_hdr()
1242 u16 subsys_id = ctx->comp->subsys_id; in init_hdr()
1254 phys_addr_t base = ctx->comp->reg_base; in config_hdr_frame()
1255 u16 subsys_id = ctx->comp->subsys_id; in config_hdr_frame()
1259 reg = CFG_COMP(MT8195, ctx->param, hdr.top); in config_hdr_frame()
1263 reg = CFG_COMP(MT8195, ctx->param, hdr.relay); in config_hdr_frame()
1272 phys_addr_t base = ctx->comp->reg_base; in config_hdr_subfrm()
1273 u16 subsys_id = ctx->comp->subsys_id; in config_hdr_subfrm()
1277 reg = CFG_COMP(MT8195, ctx->param, hdr.subfrms[index].win_size); in config_hdr_subfrm()
1281 reg = CFG_COMP(MT8195, ctx->param, hdr.subfrms[index].src); in config_hdr_subfrm()
1285 reg = CFG_COMP(MT8195, ctx->param, hdr.subfrms[index].clip_ofst0); in config_hdr_subfrm()
1289 reg = CFG_COMP(MT8195, ctx->param, hdr.subfrms[index].clip_ofst1); in config_hdr_subfrm()
1293 reg = CFG_COMP(MT8195, ctx->param, hdr.subfrms[index].hist_ctrl_0); in config_hdr_subfrm()
1297 reg = CFG_COMP(MT8195, ctx->param, hdr.subfrms[index].hist_ctrl_1); in config_hdr_subfrm()
1301 reg = CFG_COMP(MT8195, ctx->param, hdr.subfrms[index].hdr_top); in config_hdr_subfrm()
1306 reg = CFG_COMP(MT8195, ctx->param, hdr.subfrms[index].hist_addr); in config_hdr_subfrm()
1321 phys_addr_t base = ctx->comp->reg_base; in init_fg()
1322 u16 subsys_id = ctx->comp->subsys_id; in init_fg()
1334 phys_addr_t base = ctx->comp->reg_base; in config_fg_frame()
1335 u16 subsys_id = ctx->comp->subsys_id; in config_fg_frame()
1339 reg = CFG_COMP(MT8195, ctx->param, fg.ctrl_0); in config_fg_frame()
1343 reg = CFG_COMP(MT8195, ctx->param, fg.ck_en); in config_fg_frame()
1352 phys_addr_t base = ctx->comp->reg_base; in config_fg_subfrm()
1353 u16 subsys_id = ctx->comp->subsys_id; in config_fg_subfrm()
1357 reg = CFG_COMP(MT8195, ctx->param, fg.subfrms[index].info_0); in config_fg_subfrm()
1361 reg = CFG_COMP(MT8195, ctx->param, fg.subfrms[index].info_1); in config_fg_subfrm()
1376 phys_addr_t base = ctx->comp->reg_base; in init_ovl()
1377 u16 subsys_id = ctx->comp->subsys_id; in init_ovl()
1392 phys_addr_t base = ctx->comp->reg_base; in config_ovl_frame()
1393 u16 subsys_id = ctx->comp->subsys_id; in config_ovl_frame()
1397 reg = CFG_COMP(MT8195, ctx->param, ovl.L0_con); in config_ovl_frame()
1401 reg = CFG_COMP(MT8195, ctx->param, ovl.src_con); in config_ovl_frame()
1410 phys_addr_t base = ctx->comp->reg_base; in config_ovl_subfrm()
1411 u16 subsys_id = ctx->comp->subsys_id; in config_ovl_subfrm()
1415 reg = CFG_COMP(MT8195, ctx->param, ovl.subfrms[index].L0_src_size); in config_ovl_subfrm()
1420 reg = CFG_COMP(MT8195, ctx->param, ovl.subfrms[index].roi_size); in config_ovl_subfrm()
1435 phys_addr_t base = ctx->comp->reg_base; in init_pad()
1436 u16 subsys_id = ctx->comp->subsys_id; in init_pad()
1449 phys_addr_t base = ctx->comp->reg_base; in config_pad_subfrm()
1450 u16 subsys_id = ctx->comp->subsys_id; in config_pad_subfrm()
1454 reg = CFG_COMP(MT8195, ctx->param, pad.subfrms[index].pic_size); in config_pad_subfrm()
1483 .compatible = "mediatek,mt8183-mdp3-rdma",
1486 .compatible = "mediatek,mt8183-mdp3-ccorr",
1489 .compatible = "mediatek,mt8183-mdp3-rsz",
1492 .compatible = "mediatek,mt8183-mdp3-wrot",
1495 .compatible = "mediatek,mt8183-mdp3-wdma",
1498 .compatible = "mediatek,mt8195-mdp3-rdma",
1501 .compatible = "mediatek,mt8195-mdp3-split",
1504 .compatible = "mediatek,mt8195-mdp3-stitch",
1507 .compatible = "mediatek,mt8195-mdp3-fg",
1510 .compatible = "mediatek,mt8195-mdp3-hdr",
1513 .compatible = "mediatek,mt8195-mdp3-aal",
1516 .compatible = "mediatek,mt8195-mdp3-merge",
1519 .compatible = "mediatek,mt8195-mdp3-tdshp",
1522 .compatible = "mediatek,mt8195-mdp3-color",
1525 .compatible = "mediatek,mt8195-mdp3-ovl",
1528 .compatible = "mediatek,mt8195-mdp3-padding",
1531 .compatible = "mediatek,mt8195-mdp3-tcc",
1548 * dose not need to wait for GCE event. in is_bypass_gce_event()
1557 for (i = 0; i < mdp->mdp_data->comp_data_len; i++) in mdp_comp_get_id()
1558 if (mdp->mdp_data->comp_data[i].match.type == type && in mdp_comp_get_id()
1559 mdp->mdp_data->comp_data[i].match.alias_id == alias_id) in mdp_comp_get_id()
1561 return -ENODEV; in mdp_comp_get_id()
1569 if (comp->comp_dev && is_dma_capable(comp->type)) { in mdp_comp_clock_on()
1570 ret = pm_runtime_resume_and_get(comp->comp_dev); in mdp_comp_clock_on()
1574 ret, comp->type, comp->inner_id); in mdp_comp_clock_on()
1579 for (i = 0; i < comp->clk_num; i++) { in mdp_comp_clock_on()
1580 if (IS_ERR_OR_NULL(comp->clks[i])) in mdp_comp_clock_on()
1582 ret = clk_prepare_enable(comp->clks[i]); in mdp_comp_clock_on()
1586 i, comp->type, comp->inner_id); in mdp_comp_clock_on()
1594 while (--i >= 0) { in mdp_comp_clock_on()
1595 if (IS_ERR_OR_NULL(comp->clks[i])) in mdp_comp_clock_on()
1597 clk_disable_unprepare(comp->clks[i]); in mdp_comp_clock_on()
1599 if (comp->comp_dev && is_dma_capable(comp->type)) in mdp_comp_clock_on()
1600 pm_runtime_put_sync(comp->comp_dev); in mdp_comp_clock_on()
1609 for (i = 0; i < comp->clk_num; i++) { in mdp_comp_clock_off()
1610 if (IS_ERR_OR_NULL(comp->clks[i])) in mdp_comp_clock_off()
1612 clk_disable_unprepare(comp->clks[i]); in mdp_comp_clock_off()
1615 if (comp->comp_dev && is_dma_capable(comp->type)) in mdp_comp_clock_off()
1616 pm_runtime_put(comp->comp_dev); in mdp_comp_clock_off()
1637 b = &m->mdp_data->comp_data[id].blend; in mdp_comp_clocks_on()
1639 if (b && b->aid_clk) { in mdp_comp_clocks_on()
1640 ret = mdp_comp_clock_on(dev, m->comp[b->b_id]); in mdp_comp_clocks_on()
1665 b = &m->mdp_data->comp_data[id].blend; in mdp_comp_clocks_off()
1667 if (b && b->aid_clk) in mdp_comp_clocks_off()
1668 mdp_comp_clock_off(dev, m->comp[b->b_id]); in mdp_comp_clocks_off()
1681 return -EINVAL; in mdp_get_subsys_id()
1687 comp->public_id, comp->inner_id, comp->type); in mdp_get_subsys_id()
1688 return -ENODEV; in mdp_get_subsys_id()
1691 index = mdp->mdp_data->comp_data[comp->public_id].info.dts_reg_ofst; in mdp_get_subsys_id()
1692 ret = cmdq_dev_get_client_reg(&comp_pdev->dev, &cmdq_reg, index); in mdp_get_subsys_id()
1694 dev_err(&comp_pdev->dev, "cmdq_dev_get_subsys fail!\n"); in mdp_get_subsys_id()
1695 put_device(&comp_pdev->dev); in mdp_get_subsys_id()
1696 return -EINVAL; in mdp_get_subsys_id()
1699 comp->subsys_id = cmdq_reg.subsys; in mdp_get_subsys_id()
1700 dev_dbg(&comp_pdev->dev, "subsys id=%d\n", cmdq_reg.subsys); in mdp_get_subsys_id()
1701 put_device(&comp_pdev->dev); in mdp_get_subsys_id()
1713 index = mdp->mdp_data->comp_data[comp->public_id].info.dts_reg_ofst; in __mdp_comp_init()
1719 comp->mdp_dev = mdp; in __mdp_comp_init()
1720 comp->regs = of_iomap(node, 0); in __mdp_comp_init()
1721 comp->reg_base = base; in __mdp_comp_init()
1727 struct device *dev = &mdp->pdev->dev; in mdp_comp_init()
1735 return -EINVAL; in mdp_comp_init()
1741 node->name); in mdp_comp_init()
1742 return -ENODEV; in mdp_comp_init()
1745 comp->comp_dev = &pdev_c->dev; in mdp_comp_init()
1746 comp->public_id = id; in mdp_comp_init()
1747 comp->type = mdp->mdp_data->comp_data[id].match.type; in mdp_comp_init()
1748 comp->inner_id = mdp->mdp_data->comp_data[id].match.inner_id; in mdp_comp_init()
1749 comp->alias_id = mdp->mdp_data->comp_data[id].match.alias_id; in mdp_comp_init()
1750 comp->ops = mdp_comp_ops[comp->type]; in mdp_comp_init()
1753 comp->clk_num = mdp->mdp_data->comp_data[id].info.clk_num; in mdp_comp_init()
1754 comp->clks = devm_kzalloc(dev, sizeof(struct clk *) * comp->clk_num, in mdp_comp_init()
1756 if (!comp->clks) in mdp_comp_init()
1757 return -ENOMEM; in mdp_comp_init()
1759 clk_ofst = mdp->mdp_data->comp_data[id].info.clk_ofst; in mdp_comp_init()
1761 for (i = 0; i < comp->clk_num; i++) { in mdp_comp_init()
1762 comp->clks[i] = of_clk_get(node, i + clk_ofst); in mdp_comp_init()
1763 if (IS_ERR(comp->clks[i])) in mdp_comp_init()
1769 /* Set GCE SOF event */ in mdp_comp_init()
1770 if (is_bypass_gce_event(comp->type) || in mdp_comp_init()
1771 of_property_read_u32_index(node, "mediatek,gce-events", in mdp_comp_init()
1775 comp->gce_event[MDP_GCE_EVENT_SOF] = event; in mdp_comp_init()
1777 /* Set GCE EOF event */ in mdp_comp_init()
1778 if (is_dma_capable(comp->type)) { in mdp_comp_init()
1779 if (of_property_read_u32_index(node, "mediatek,gce-events", in mdp_comp_init()
1782 return -EINVAL; in mdp_comp_init()
1788 comp->gce_event[MDP_GCE_EVENT_EOF] = event; in mdp_comp_init()
1798 if (comp->comp_dev && comp->clks) { in mdp_comp_deinit()
1799 devm_kfree(&comp->mdp_dev->pdev->dev, comp->clks); in mdp_comp_deinit()
1800 comp->clks = NULL; in mdp_comp_deinit()
1803 if (comp->regs) in mdp_comp_deinit()
1804 iounmap(comp->regs); in mdp_comp_deinit()
1811 struct device *dev = &mdp->pdev->dev; in mdp_comp_create()
1815 if (mdp->comp[id]) in mdp_comp_create()
1816 return ERR_PTR(-EEXIST); in mdp_comp_create()
1820 return ERR_PTR(-ENOMEM); in mdp_comp_create()
1827 mdp->comp[id] = comp; in mdp_comp_create()
1828 mdp->comp[id]->mdp_dev = mdp; in mdp_comp_create()
1831 dev->of_node->name, comp->type, comp->alias_id, id, comp->inner_id, in mdp_comp_create()
1832 (u32)comp->reg_base, comp->regs); in mdp_comp_create()
1838 struct device *dev = &mdp->pdev->dev; in mdp_comp_sub_create()
1842 parent = dev->of_node->parent; in mdp_comp_sub_create()
1850 of_id = of_match_node(mdp->mdp_data->mdp_sub_comp_dt_ids, node); in mdp_comp_sub_create()
1859 type = (enum mdp_comp_type)(uintptr_t)of_id->data; in mdp_comp_sub_create()
1866 ret = -EINVAL; in mdp_comp_sub_create()
1888 for (i = 0; i < ARRAY_SIZE(mdp->comp); i++) { in mdp_comp_destroy()
1889 if (mdp->comp[i]) { in mdp_comp_destroy()
1890 if (is_dma_capable(mdp->comp[i]->type)) in mdp_comp_destroy()
1891 pm_runtime_disable(mdp->comp[i]->comp_dev); in mdp_comp_destroy()
1892 mdp_comp_deinit(mdp->comp[i]); in mdp_comp_destroy()
1893 devm_kfree(mdp->comp[i]->comp_dev, mdp->comp[i]); in mdp_comp_destroy()
1894 mdp->comp[i] = NULL; in mdp_comp_destroy()
1901 struct device *dev = &mdp->pdev->dev; in mdp_comp_config()
1906 p_id = mdp->mdp_data->mdp_plat_id; in mdp_comp_config()
1908 parent = dev->of_node->parent; in mdp_comp_config()
1926 type = (enum mdp_comp_type)(uintptr_t)of_id->data; in mdp_comp_config()
1945 if (!is_dma_capable(comp->type)) in mdp_comp_config()
1947 pm_runtime_enable(comp->comp_dev); in mdp_comp_config()
1965 struct device *dev = &mdp->pdev->dev; in mdp_comp_ctx_config()
1972 return -EINVAL; in mdp_comp_ctx_config()
1980 return -EINVAL; in mdp_comp_ctx_config()
1984 return -EINVAL; in mdp_comp_ctx_config()
1987 ctx->comp = mdp->comp[public_id]; in mdp_comp_ctx_config()
1988 if (!ctx->comp) { in mdp_comp_ctx_config()
1990 return -EINVAL; in mdp_comp_ctx_config()
1993 ctx->param = param; in mdp_comp_ctx_config()
1999 return -EINVAL; in mdp_comp_ctx_config()
2000 ctx->input = &frame->inputs[arg]; in mdp_comp_ctx_config()
2006 return -EINVAL; in mdp_comp_ctx_config()
2013 return -EINVAL; in mdp_comp_ctx_config()
2014 ctx->outputs[i] = &frame->outputs[arg]; in mdp_comp_ctx_config()