34 	u32 val;  in write_reg_field_not_busy()  local
50 	u32 val;  in e5010_reset()  local
71 void e5010_hw_bypass_mmu(void __iomem *mmu_base, u32 enable)  in e5010_hw_bypass_mmu()
81 int e5010_hw_enable_output_address_error_irq(void __iomem *core_base, u32 enable)  in e5010_hw_enable_output_address_error_irq()
106 int e5010_hw_enable_picture_done_irq(void __iomem *core_base, u32 enable)  in e5010_hw_enable_picture_done_irq()
115 int e5010_hw_enable_auto_clock_gating(void __iomem *core_base, u32 enable)  in e5010_hw_enable_auto_clock_gating()
124 int e5010_hw_enable_manual_clock_gating(void __iomem *core_base, u32 enable)  in e5010_hw_enable_manual_clock_gating()
132 int e5010_hw_enable_crc_check(void __iomem *core_base, u32 enable)  in e5010_hw_enable_crc_check()
148 int e5010_hw_set_input_luma_addr(void __iomem *core_base, u32 val)  in e5010_hw_set_input_luma_addr()
155 int e5010_hw_set_input_chroma_addr(void __iomem *core_base, u32 val)  in e5010_hw_set_input_chroma_addr()
162 int e5010_hw_set_output_base_addr(void __iomem *core_base, u32 val)  in e5010_hw_set_output_base_addr()
170 int e5010_hw_set_horizontal_size(void __iomem *core_base, u32 val)  in e5010_hw_set_horizontal_size()
179 int e5010_hw_set_vertical_size(void __iomem *core_base, u32 val)  in e5010_hw_set_vertical_size()
190 	u32 val = bytesperline / 64;  in e5010_hw_set_luma_stride()  local
201 	u32 val = bytesperline / 64;  in e5010_hw_set_chroma_stride()  local
210 int e5010_hw_set_input_subsampling(void __iomem *core_base, u32 val)  in e5010_hw_set_input_subsampling()
219 int e5010_hw_set_chroma_order(void __iomem *core_base, u32 val)  in e5010_hw_set_chroma_order()
228 void e5010_hw_set_output_max_size(void __iomem *core_base, u32 val)  in e5010_hw_set_output_max_size()
236 int e5010_hw_set_qpvalue(void __iomem *core_base, u32 offset, u32 val)  in e5010_hw_set_qpvalue()