Lines Matching +full:msb +full:- +full:justified
1 // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
3 * Wave5 series multi-standard codec IP - wave5 backend logic
5 * Copyright (C) 2021-2023 CHIPS&MEDIA INC
10 #include "wave5-vpu.h"
12 #include "wave5-regdefine.h"
96 struct device *dev = vpu_dev->dev; in _wave5_print_reg_err()
144 return -ETIMEDOUT; in wave5_wait_fio_readl()
161 dev_dbg_ratelimited(vpu_dev->dev, "FIO write timeout: addr=0x%x data=%x\n", in wave5_fio_writel()
169 if (vpu_dev->product_code == WAVE515_CODE) in wave5_wait_bus_busy()
171 if (vpu_dev->product_code == WAVE521C_CODE || in wave5_wait_bus_busy()
172 vpu_dev->product_code == WAVE521_CODE || in wave5_wait_bus_busy()
173 vpu_dev->product_code == WAVE521E1_CODE) in wave5_wait_bus_busy()
212 dev_err(vpu_dev->dev, "Unsupported product id (%x)\n", val); in wave5_vpu_get_product_id()
215 dev_err(vpu_dev->dev, "Invalid product id (%x)\n", val); in wave5_vpu_get_product_id()
228 instance_index = inst->id; in wave5_bit_issue_command()
229 codec_mode = inst->std; in wave5_bit_issue_command()
239 dev_dbg(vpu_dev->dev, "%s: cmd=0x%x (%s)\n", __func__, cmd, in wave5_bit_issue_command()
240 cmd_to_str(cmd, inst->type == VPU_INST_TYPE_DEC)); in wave5_bit_issue_command()
242 dev_dbg(vpu_dev->dev, "%s: cmd=0x%x\n", __func__, cmd); in wave5_bit_issue_command()
259 * If the fail_res argument is NULL, then just return -EIO. in wave5_vpu_firmware_command_queue_error_check()
266 return -EIO; in wave5_vpu_firmware_command_queue_error_check()
269 return -EBUSY; in wave5_vpu_firmware_command_queue_error_check()
279 wave5_bit_issue_command(inst->dev, inst, cmd); in send_firmware_command()
280 ret = wave5_wait_vpu_busy(inst->dev, W5_VPU_BUSY_STATUS); in send_firmware_command()
282 dev_warn(inst->dev->dev, "%s: command: '%s', timed out\n", __func__, in send_firmware_command()
283 cmd_to_str(cmd, inst->type == VPU_INST_TYPE_DEC)); in send_firmware_command()
284 return -ETIMEDOUT; in send_firmware_command()
288 *queue_status = vpu_read_reg(inst->dev, W5_RET_QUEUE_STATUS); in send_firmware_command()
296 return wave5_vpu_firmware_command_queue_error_check(inst->dev, fail_result); in send_firmware_command()
310 dev_warn(vpu_dev->dev, "command: 'W5_QUERY', timed out opt=0x%x\n", query_opt); in wave5_send_query()
321 if (vpu_dev->attr.support_encoders) { in setup_wave5_interrupts()
328 if (vpu_dev->attr.support_decoders) { in setup_wave5_interrupts()
341 struct vpu_attr *p_attr = &vpu_dev->attr; in setup_wave5_properties()
353 p_attr->product_name[0] = str[3]; in setup_wave5_properties()
354 p_attr->product_name[1] = str[2]; in setup_wave5_properties()
355 p_attr->product_name[2] = str[1]; in setup_wave5_properties()
356 p_attr->product_name[3] = str[0]; in setup_wave5_properties()
357 p_attr->product_name[4] = 0; in setup_wave5_properties()
359 p_attr->product_id = wave5_vpu_get_product_id(vpu_dev); in setup_wave5_properties()
360 p_attr->product_version = vpu_read_reg(vpu_dev, W5_RET_PRODUCT_VERSION); in setup_wave5_properties()
361 p_attr->fw_version = vpu_read_reg(vpu_dev, W5_RET_FW_VERSION); in setup_wave5_properties()
362 p_attr->customer_id = vpu_read_reg(vpu_dev, W5_RET_CUSTOMER_ID); in setup_wave5_properties()
367 if (vpu_dev->product_code == WAVE515_CODE) { in setup_wave5_properties()
368 p_attr->support_hevc10bit_dec = FIELD_GET(W515_FEATURE_HEVC10BIT_DEC, in setup_wave5_properties()
370 p_attr->support_decoders = FIELD_GET(W515_FEATURE_HEVC_DECODER, in setup_wave5_properties()
373 p_attr->support_hevc10bit_enc = FIELD_GET(W521_FEATURE_HEVC10BIT_ENC, in setup_wave5_properties()
375 p_attr->support_avc10bit_enc = FIELD_GET(W521_FEATURE_AVC10BIT_ENC, in setup_wave5_properties()
378 p_attr->support_decoders = FIELD_GET(W521_FEATURE_AVC_DECODER, in setup_wave5_properties()
380 p_attr->support_decoders |= FIELD_GET(W521_FEATURE_HEVC_DECODER, in setup_wave5_properties()
382 p_attr->support_encoders = FIELD_GET(W521_FEATURE_AVC_ENCODER, in setup_wave5_properties()
384 p_attr->support_encoders |= FIELD_GET(W521_FEATURE_HEVC_ENCODER, in setup_wave5_properties()
387 p_attr->support_backbone = FIELD_GET(W521_FEATURE_BACKBONE, in setup_wave5_properties()
389 p_attr->support_vcpu_backbone = FIELD_GET(W521_FEATURE_VCPU_BACKBONE, in setup_wave5_properties()
391 p_attr->support_vcore_backbone = FIELD_GET(W521_FEATURE_VCORE_BACKBONE, in setup_wave5_properties()
415 return -EINVAL; in wave5_vpu_get_version()
434 common_vb = &vpu_dev->common_mem; in wave5_vpu_init()
436 code_base = common_vb->daddr; in wave5_vpu_init()
438 if (vpu_dev->product_code == WAVE515_CODE) in wave5_vpu_init()
446 return -EINVAL; in wave5_vpu_init()
453 dev_err(vpu_dev->dev, "VPU init, Writing firmware to common buffer, fail: %d\n", in wave5_vpu_init()
477 if (vpu_dev->product_code != WAVE515_CODE) { in wave5_vpu_init()
496 if (vpu_dev->product_code == WAVE515_CODE) { in wave5_vpu_init()
510 vpu_write_reg(vpu_dev, W515_CMD_ADDR_SEC_AXI, vpu_dev->sram_buf.daddr); in wave5_vpu_init()
511 vpu_write_reg(vpu_dev, W515_CMD_SEC_AXI_SIZE, vpu_dev->sram_buf.size); in wave5_vpu_init()
519 dev_err(vpu_dev->dev, "VPU init(W5_VPU_REMAP_CORE_START) timeout\n"); in wave5_vpu_init()
534 struct dec_info *p_dec_info = &inst->codec_info->dec_info; in wave5_vpu_build_up_dec_param()
535 struct vpu_device *vpu_dev = inst->dev; in wave5_vpu_build_up_dec_param()
537 p_dec_info->cycle_per_tick = 256; in wave5_vpu_build_up_dec_param()
538 if (vpu_dev->sram_buf.size) { in wave5_vpu_build_up_dec_param()
539 p_dec_info->sec_axi_info.use_bit_enable = 1; in wave5_vpu_build_up_dec_param()
540 p_dec_info->sec_axi_info.use_ip_enable = 1; in wave5_vpu_build_up_dec_param()
541 p_dec_info->sec_axi_info.use_lf_row_enable = 1; in wave5_vpu_build_up_dec_param()
543 switch (inst->std) { in wave5_vpu_build_up_dec_param()
545 p_dec_info->seq_change_mask = SEQ_CHANGE_ENABLE_ALL_HEVC; in wave5_vpu_build_up_dec_param()
548 p_dec_info->seq_change_mask = SEQ_CHANGE_ENABLE_ALL_AVC; in wave5_vpu_build_up_dec_param()
551 return -EINVAL; in wave5_vpu_build_up_dec_param()
554 if (vpu_dev->product == PRODUCT_ID_515) in wave5_vpu_build_up_dec_param()
555 p_dec_info->vb_work.size = WAVE515DEC_WORKBUF_SIZE; in wave5_vpu_build_up_dec_param()
557 p_dec_info->vb_work.size = WAVE521DEC_WORKBUF_SIZE; in wave5_vpu_build_up_dec_param()
559 ret = wave5_vdi_allocate_dma_memory(inst->dev, &p_dec_info->vb_work); in wave5_vpu_build_up_dec_param()
563 if (inst->dev->product_code != WAVE515_CODE) in wave5_vpu_build_up_dec_param()
564 vpu_write_reg(inst->dev, W5_CMD_DEC_VCORE_INFO, 1); in wave5_vpu_build_up_dec_param()
566 wave5_vdi_clear_memory(inst->dev, &p_dec_info->vb_work); in wave5_vpu_build_up_dec_param()
568 vpu_write_reg(inst->dev, W5_ADDR_WORK_BASE, p_dec_info->vb_work.daddr); in wave5_vpu_build_up_dec_param()
569 vpu_write_reg(inst->dev, W5_WORK_SIZE, p_dec_info->vb_work.size); in wave5_vpu_build_up_dec_param()
571 if (inst->dev->product_code != WAVE515_CODE) { in wave5_vpu_build_up_dec_param()
572 vpu_write_reg(inst->dev, W5_CMD_ADDR_SEC_AXI, vpu_dev->sram_buf.daddr); in wave5_vpu_build_up_dec_param()
573 vpu_write_reg(inst->dev, W5_CMD_SEC_AXI_SIZE, vpu_dev->sram_buf.size); in wave5_vpu_build_up_dec_param()
576 vpu_write_reg(inst->dev, W5_CMD_DEC_BS_START_ADDR, p_dec_info->stream_buf_start_addr); in wave5_vpu_build_up_dec_param()
577 vpu_write_reg(inst->dev, W5_CMD_DEC_BS_SIZE, p_dec_info->stream_buf_size); in wave5_vpu_build_up_dec_param()
579 /* NOTE: SDMA reads MSB first */ in wave5_vpu_build_up_dec_param()
580 vpu_write_reg(inst->dev, W5_CMD_BS_PARAM, BITSTREAM_ENDIANNESS_BIG_ENDIAN); in wave5_vpu_build_up_dec_param()
582 if (inst->dev->product_code != WAVE515_CODE) { in wave5_vpu_build_up_dec_param()
584 vpu_write_reg(inst->dev, W5_CMD_EXT_ADDR, 0); in wave5_vpu_build_up_dec_param()
585 vpu_write_reg(inst->dev, W5_CMD_NUM_CQ_DEPTH_M1, in wave5_vpu_build_up_dec_param()
586 WAVE521_COMMAND_QUEUE_DEPTH - 1); in wave5_vpu_build_up_dec_param()
588 vpu_write_reg(inst->dev, W5_CMD_ERR_CONCEAL, 0); in wave5_vpu_build_up_dec_param()
591 wave5_vdi_free_dma_memory(vpu_dev, &p_dec_info->vb_work); in wave5_vpu_build_up_dec_param()
595 p_dec_info->product_code = vpu_read_reg(inst->dev, W5_PRODUCT_NUMBER); in wave5_vpu_build_up_dec_param()
602 struct dec_info *p_dec_info = &inst->codec_info->dec_info; in wave5_vpu_hw_flush_instance()
615 dev_warn(inst->dev->dev, in wave5_vpu_hw_flush_instance()
620 p_dec_info->instance_queue_count = 0; in wave5_vpu_hw_flush_instance()
621 p_dec_info->report_queue_count = 0; in wave5_vpu_hw_flush_instance()
630 if (info->stream_endflag) in get_bitstream_options()
637 struct dec_info *p_dec_info = &inst->codec_info->dec_info; in wave5_vpu_dec_init_seq()
642 if (!inst->codec_info) in wave5_vpu_dec_init_seq()
643 return -EINVAL; in wave5_vpu_dec_init_seq()
645 vpu_write_reg(inst->dev, W5_BS_RD_PTR, p_dec_info->stream_rd_ptr); in wave5_vpu_dec_init_seq()
646 vpu_write_reg(inst->dev, W5_BS_WR_PTR, p_dec_info->stream_wr_ptr); in wave5_vpu_dec_init_seq()
651 if (inst->dev->product_code == WAVE515_CODE) in wave5_vpu_dec_init_seq()
654 vpu_write_reg(inst->dev, W5_BS_OPTION, bs_option); in wave5_vpu_dec_init_seq()
656 vpu_write_reg(inst->dev, W5_COMMAND_OPTION, cmd_option); in wave5_vpu_dec_init_seq()
657 vpu_write_reg(inst->dev, W5_CMD_DEC_USER_MASK, p_dec_info->user_data_enable); in wave5_vpu_dec_init_seq()
663 p_dec_info->instance_queue_count = (reg_val >> 16) & 0xff; in wave5_vpu_dec_init_seq()
664 p_dec_info->report_queue_count = (reg_val & QUEUE_REPORT_MASK); in wave5_vpu_dec_init_seq()
666 dev_dbg(inst->dev->dev, "%s: init seq sent (queue %u : %u)\n", __func__, in wave5_vpu_dec_init_seq()
667 p_dec_info->instance_queue_count, p_dec_info->report_queue_count); in wave5_vpu_dec_init_seq()
676 struct dec_info *p_dec_info = &inst->codec_info->dec_info; in wave5_get_dec_seq_result()
678 p_dec_info->stream_rd_ptr = wave5_dec_get_rd_ptr(inst); in wave5_get_dec_seq_result()
679 info->rd_ptr = p_dec_info->stream_rd_ptr; in wave5_get_dec_seq_result()
681 p_dec_info->frame_display_flag = vpu_read_reg(inst->dev, W5_RET_DEC_DISP_IDC); in wave5_get_dec_seq_result()
683 reg_val = vpu_read_reg(inst->dev, W5_RET_DEC_PIC_SIZE); in wave5_get_dec_seq_result()
684 info->pic_width = ((reg_val >> 16) & 0xffff); in wave5_get_dec_seq_result()
685 info->pic_height = (reg_val & 0xffff); in wave5_get_dec_seq_result()
686 info->min_frame_buffer_count = vpu_read_reg(inst->dev, W5_RET_DEC_NUM_REQUIRED_FB); in wave5_get_dec_seq_result()
688 reg_val = vpu_read_reg(inst->dev, W5_RET_DEC_CROP_LEFT_RIGHT); in wave5_get_dec_seq_result()
689 info->pic_crop_rect.left = (reg_val >> 16) & 0xffff; in wave5_get_dec_seq_result()
690 info->pic_crop_rect.right = reg_val & 0xffff; in wave5_get_dec_seq_result()
691 reg_val = vpu_read_reg(inst->dev, W5_RET_DEC_CROP_TOP_BOTTOM); in wave5_get_dec_seq_result()
692 info->pic_crop_rect.top = (reg_val >> 16) & 0xffff; in wave5_get_dec_seq_result()
693 info->pic_crop_rect.bottom = reg_val & 0xffff; in wave5_get_dec_seq_result()
695 reg_val = vpu_read_reg(inst->dev, W5_RET_DEC_COLOR_SAMPLE_INFO); in wave5_get_dec_seq_result()
696 info->luma_bitdepth = reg_val & 0xf; in wave5_get_dec_seq_result()
697 info->chroma_bitdepth = (reg_val >> 4) & 0xf; in wave5_get_dec_seq_result()
699 reg_val = vpu_read_reg(inst->dev, W5_RET_DEC_SEQ_PARAM); in wave5_get_dec_seq_result()
701 info->profile = (reg_val >> 24) & 0x1f; in wave5_get_dec_seq_result()
703 if (inst->std == W_HEVC_DEC) { in wave5_get_dec_seq_result()
705 if (!info->profile) { in wave5_get_dec_seq_result()
707 info->profile = HEVC_PROFILE_MAIN; /* main profile */ in wave5_get_dec_seq_result()
709 info->profile = HEVC_PROFILE_MAIN10; /* main10 profile */ in wave5_get_dec_seq_result()
712 info->profile = HEVC_PROFILE_STILLPICTURE; in wave5_get_dec_seq_result()
714 info->profile = HEVC_PROFILE_MAIN; /* for old version HM */ in wave5_get_dec_seq_result()
716 } else if (inst->std == W_AVC_DEC) { in wave5_get_dec_seq_result()
717 info->profile = FIELD_GET(SEQ_PARAM_PROFILE_MASK, reg_val); in wave5_get_dec_seq_result()
720 if (inst->dev->product_code != WAVE515_CODE) { in wave5_get_dec_seq_result()
721 info->vlc_buf_size = vpu_read_reg(inst->dev, W5_RET_VLC_BUF_SIZE); in wave5_get_dec_seq_result()
722 info->param_buf_size = vpu_read_reg(inst->dev, W5_RET_PARAM_BUF_SIZE); in wave5_get_dec_seq_result()
723 p_dec_info->vlc_buf_size = info->vlc_buf_size; in wave5_get_dec_seq_result()
724 p_dec_info->param_buf_size = info->param_buf_size; in wave5_get_dec_seq_result()
732 struct dec_info *p_dec_info = &inst->codec_info->dec_info; in wave5_vpu_dec_get_seq_info()
734 vpu_write_reg(inst->dev, W5_CMD_DEC_ADDR_REPORT_BASE, p_dec_info->user_data_buf_addr); in wave5_vpu_dec_get_seq_info()
735 vpu_write_reg(inst->dev, W5_CMD_DEC_REPORT_SIZE, p_dec_info->user_data_buf_size); in wave5_vpu_dec_get_seq_info()
736 vpu_write_reg(inst->dev, W5_CMD_DEC_REPORT_PARAM, REPORT_PARAM_ENDIANNESS_BIG_ENDIAN); in wave5_vpu_dec_get_seq_info()
739 ret = wave5_send_query(inst->dev, inst, GET_RESULT); in wave5_vpu_dec_get_seq_info()
743 reg_val = vpu_read_reg(inst->dev, W5_RET_QUEUE_STATUS); in wave5_vpu_dec_get_seq_info()
745 p_dec_info->instance_queue_count = (reg_val >> 16) & 0xff; in wave5_vpu_dec_get_seq_info()
746 p_dec_info->report_queue_count = (reg_val & QUEUE_REPORT_MASK); in wave5_vpu_dec_get_seq_info()
748 dev_dbg(inst->dev->dev, "%s: init seq complete (queue %u : %u)\n", __func__, in wave5_vpu_dec_get_seq_info()
749 p_dec_info->instance_queue_count, p_dec_info->report_queue_count); in wave5_vpu_dec_get_seq_info()
751 /* this is not a fatal error, set ret to -EIO but don't return immediately */ in wave5_vpu_dec_get_seq_info()
752 if (vpu_read_reg(inst->dev, W5_RET_DEC_DECODING_SUCCESS) != 1) { in wave5_vpu_dec_get_seq_info()
753 info->seq_init_err_reason = vpu_read_reg(inst->dev, W5_RET_DEC_ERR_INFO); in wave5_vpu_dec_get_seq_info()
754 ret = -EIO; in wave5_vpu_dec_get_seq_info()
766 struct dec_info *p_dec_info = &inst->codec_info->dec_info; in wave5_vpu_dec_register_framebuffer()
767 struct dec_initial_info *init_info = &p_dec_info->initial_info; in wave5_vpu_dec_register_framebuffer()
774 bool justified = WTL_RIGHT_JUSTIFIED; in wave5_vpu_dec_register_framebuffer() local
780 cbcr_interleave = inst->cbcr_interleave; in wave5_vpu_dec_register_framebuffer()
781 nv21 = inst->nv21; in wave5_vpu_dec_register_framebuffer()
790 switch (inst->std) { in wave5_vpu_dec_register_framebuffer()
792 mv_col_size = WAVE5_DEC_HEVC_BUF_SIZE(init_info->pic_width, in wave5_vpu_dec_register_framebuffer()
793 init_info->pic_height); in wave5_vpu_dec_register_framebuffer()
796 mv_col_size = WAVE5_DEC_AVC_BUF_SIZE(init_info->pic_width, in wave5_vpu_dec_register_framebuffer()
797 init_info->pic_height); in wave5_vpu_dec_register_framebuffer()
800 return -EINVAL; in wave5_vpu_dec_register_framebuffer()
803 if (inst->std == W_HEVC_DEC || inst->std == W_AVC_DEC) { in wave5_vpu_dec_register_framebuffer()
805 ret = wave5_vdi_allocate_array(inst->dev, p_dec_info->vb_mv, count, size); in wave5_vpu_dec_register_framebuffer()
810 frame_width = init_info->pic_width; in wave5_vpu_dec_register_framebuffer()
811 frame_height = init_info->pic_height; in wave5_vpu_dec_register_framebuffer()
816 ret = wave5_vdi_allocate_array(inst->dev, p_dec_info->vb_fbc_y_tbl, count, size); in wave5_vpu_dec_register_framebuffer()
821 ret = wave5_vdi_allocate_array(inst->dev, p_dec_info->vb_fbc_c_tbl, count, size); in wave5_vpu_dec_register_framebuffer()
825 pic_size = (init_info->pic_width << 16) | (init_info->pic_height); in wave5_vpu_dec_register_framebuffer()
827 if (inst->dev->product_code != WAVE515_CODE) { in wave5_vpu_dec_register_framebuffer()
828 vb_buf.size = (p_dec_info->vlc_buf_size * VLC_BUF_NUM) + in wave5_vpu_dec_register_framebuffer()
829 (p_dec_info->param_buf_size * WAVE521_COMMAND_QUEUE_DEPTH); in wave5_vpu_dec_register_framebuffer()
832 if (vb_buf.size != p_dec_info->vb_task.size) { in wave5_vpu_dec_register_framebuffer()
833 wave5_vdi_free_dma_memory(inst->dev, in wave5_vpu_dec_register_framebuffer()
834 &p_dec_info->vb_task); in wave5_vpu_dec_register_framebuffer()
835 ret = wave5_vdi_allocate_dma_memory(inst->dev, in wave5_vpu_dec_register_framebuffer()
840 p_dec_info->vb_task = vb_buf; in wave5_vpu_dec_register_framebuffer()
843 vpu_write_reg(inst->dev, W5_CMD_SET_FB_ADDR_TASK_BUF, in wave5_vpu_dec_register_framebuffer()
844 p_dec_info->vb_task.daddr); in wave5_vpu_dec_register_framebuffer()
845 vpu_write_reg(inst->dev, W5_CMD_SET_FB_TASK_BUF_SIZE, in wave5_vpu_dec_register_framebuffer()
849 pic_size = (init_info->pic_width << 16) | (init_info->pic_height); in wave5_vpu_dec_register_framebuffer()
851 if (inst->output_format == FORMAT_422) in wave5_vpu_dec_register_framebuffer()
854 vpu_write_reg(inst->dev, W5_PIC_SIZE, pic_size); in wave5_vpu_dec_register_framebuffer()
858 (justified << 22) | in wave5_vpu_dec_register_framebuffer()
864 vpu_write_reg(inst->dev, W5_COMMON_PIC_INFO, reg_val); in wave5_vpu_dec_register_framebuffer()
870 reg_val = (j == cnt_8_chunk - 1) << 4 | ((j == 0) << 3); in wave5_vpu_dec_register_framebuffer()
871 vpu_write_reg(inst->dev, W5_SFB_OPTION, reg_val); in wave5_vpu_dec_register_framebuffer()
873 end_no = start_no + ((remain >= 8) ? 8 : remain) - 1; in wave5_vpu_dec_register_framebuffer()
875 vpu_write_reg(inst->dev, W5_SET_FB_NUM, (start_no << 8) | end_no); in wave5_vpu_dec_register_framebuffer()
881 vpu_write_reg(inst->dev, W5_ADDR_LUMA_BASE0 + (i << 4), addr_y); in wave5_vpu_dec_register_framebuffer()
882 vpu_write_reg(inst->dev, W5_ADDR_CB_BASE0 + (i << 4), addr_cb); in wave5_vpu_dec_register_framebuffer()
885 vpu_write_reg(inst->dev, W5_ADDR_FBC_Y_OFFSET0 + (i << 4), in wave5_vpu_dec_register_framebuffer()
886 p_dec_info->vb_fbc_y_tbl[idx].daddr); in wave5_vpu_dec_register_framebuffer()
888 vpu_write_reg(inst->dev, W5_ADDR_FBC_C_OFFSET0 + (i << 4), in wave5_vpu_dec_register_framebuffer()
889 p_dec_info->vb_fbc_c_tbl[idx].daddr); in wave5_vpu_dec_register_framebuffer()
890 vpu_write_reg(inst->dev, W5_ADDR_MV_COL0 + (i << 2), in wave5_vpu_dec_register_framebuffer()
891 p_dec_info->vb_mv[idx].daddr); in wave5_vpu_dec_register_framebuffer()
893 vpu_write_reg(inst->dev, W5_ADDR_CR_BASE0 + (i << 4), addr_cr); in wave5_vpu_dec_register_framebuffer()
894 vpu_write_reg(inst->dev, W5_ADDR_FBC_C_OFFSET0 + (i << 4), 0); in wave5_vpu_dec_register_framebuffer()
895 vpu_write_reg(inst->dev, W5_ADDR_MV_COL0 + (i << 2), 0); in wave5_vpu_dec_register_framebuffer()
899 remain -= i; in wave5_vpu_dec_register_framebuffer()
906 reg_val = vpu_read_reg(inst->dev, W5_RET_SUCCESS); in wave5_vpu_dec_register_framebuffer()
908 ret = -EIO; in wave5_vpu_dec_register_framebuffer()
915 wave5_vdi_free_dma_memory(inst->dev, &p_dec_info->vb_task); in wave5_vpu_dec_register_framebuffer()
918 wave5_vdi_free_dma_memory(inst->dev, &p_dec_info->vb_fbc_c_tbl[i]); in wave5_vpu_dec_register_framebuffer()
921 wave5_vdi_free_dma_memory(inst->dev, &p_dec_info->vb_fbc_y_tbl[i]); in wave5_vpu_dec_register_framebuffer()
924 wave5_vdi_free_dma_memory(inst->dev, &p_dec_info->vb_mv[i]); in wave5_vpu_dec_register_framebuffer()
930 u32 bitdepth = inst->codec_info->dec_info.initial_info.luma_bitdepth; in wave5_vpu_dec_validate_sec_axi()
931 struct dec_info *p_dec_info = &inst->codec_info->dec_info; in wave5_vpu_dec_validate_sec_axi()
933 u32 sram_size = inst->dev->sram_size; in wave5_vpu_dec_validate_sec_axi()
934 u32 width = inst->src_fmt.width; in wave5_vpu_dec_validate_sec_axi()
943 if (inst->dev->product_code == WAVE515_CODE) { in wave5_vpu_dec_validate_sec_axi()
949 if (p_dec_info->sec_axi_info.use_bit_enable && sram_size >= bit_size) { in wave5_vpu_dec_validate_sec_axi()
951 sram_size -= bit_size; in wave5_vpu_dec_validate_sec_axi()
954 if (p_dec_info->sec_axi_info.use_ip_enable && sram_size >= ip_size) { in wave5_vpu_dec_validate_sec_axi()
956 sram_size -= ip_size; in wave5_vpu_dec_validate_sec_axi()
959 if (p_dec_info->sec_axi_info.use_lf_row_enable && sram_size >= lf_size) in wave5_vpu_dec_validate_sec_axi()
968 struct dec_info *p_dec_info = &inst->codec_info->dec_info; in wave5_vpu_decode()
971 vpu_write_reg(inst->dev, W5_BS_RD_PTR, p_dec_info->stream_rd_ptr); in wave5_vpu_decode()
972 vpu_write_reg(inst->dev, W5_BS_WR_PTR, p_dec_info->stream_wr_ptr); in wave5_vpu_decode()
974 vpu_write_reg(inst->dev, W5_BS_OPTION, get_bitstream_options(p_dec_info)); in wave5_vpu_decode()
978 vpu_write_reg(inst->dev, W5_USE_SEC_AXI, reg_val); in wave5_vpu_decode()
981 vpu_write_reg(inst->dev, W5_CMD_DEC_USER_MASK, p_dec_info->user_data_enable); in wave5_vpu_decode()
983 vpu_write_reg(inst->dev, W5_COMMAND_OPTION, DEC_PIC_NORMAL); in wave5_vpu_decode()
984 vpu_write_reg(inst->dev, W5_CMD_DEC_TEMPORAL_ID_PLUS1, in wave5_vpu_decode()
985 (p_dec_info->target_spatial_id << 9) | in wave5_vpu_decode()
986 (p_dec_info->temp_id_select_mode << 8) | p_dec_info->target_temp_id); in wave5_vpu_decode()
987 vpu_write_reg(inst->dev, W5_CMD_SEQ_CHANGE_ENABLE_FLAG, p_dec_info->seq_change_mask); in wave5_vpu_decode()
989 vpu_write_reg(inst->dev, W5_CMD_DEC_FORCE_FB_LATENCY_PLUS1, !p_dec_info->reorder_enable); in wave5_vpu_decode()
992 if (ret == -ETIMEDOUT) in wave5_vpu_decode()
995 p_dec_info->instance_queue_count = (reg_val >> 16) & 0xff; in wave5_vpu_decode()
996 p_dec_info->report_queue_count = (reg_val & QUEUE_REPORT_MASK); in wave5_vpu_decode()
998 dev_dbg(inst->dev->dev, "%s: dec pic sent (queue %u : %u)\n", __func__, in wave5_vpu_decode()
999 p_dec_info->instance_queue_count, p_dec_info->report_queue_count); in wave5_vpu_decode()
1011 struct dec_info *p_dec_info = &inst->codec_info->dec_info; in wave5_vpu_dec_get_result()
1012 struct vpu_device *vpu_dev = inst->dev; in wave5_vpu_dec_get_result()
1014 vpu_write_reg(inst->dev, W5_CMD_DEC_ADDR_REPORT_BASE, p_dec_info->user_data_buf_addr); in wave5_vpu_dec_get_result()
1015 vpu_write_reg(inst->dev, W5_CMD_DEC_REPORT_SIZE, p_dec_info->user_data_buf_size); in wave5_vpu_dec_get_result()
1016 vpu_write_reg(inst->dev, W5_CMD_DEC_REPORT_PARAM, REPORT_PARAM_ENDIANNESS_BIG_ENDIAN); in wave5_vpu_dec_get_result()
1023 reg_val = vpu_read_reg(inst->dev, W5_RET_QUEUE_STATUS); in wave5_vpu_dec_get_result()
1025 p_dec_info->instance_queue_count = (reg_val >> 16) & 0xff; in wave5_vpu_dec_get_result()
1026 p_dec_info->report_queue_count = (reg_val & QUEUE_REPORT_MASK); in wave5_vpu_dec_get_result()
1028 dev_dbg(inst->dev->dev, "%s: dec pic complete (queue %u : %u)\n", __func__, in wave5_vpu_dec_get_result()
1029 p_dec_info->instance_queue_count, p_dec_info->report_queue_count); in wave5_vpu_dec_get_result()
1031 reg_val = vpu_read_reg(inst->dev, W5_RET_DEC_PIC_TYPE); in wave5_vpu_dec_get_result()
1035 if (inst->std == W_HEVC_DEC) { in wave5_vpu_dec_get_result()
1037 result->pic_type = PIC_TYPE_B; in wave5_vpu_dec_get_result()
1039 result->pic_type = PIC_TYPE_P; in wave5_vpu_dec_get_result()
1041 result->pic_type = PIC_TYPE_I; in wave5_vpu_dec_get_result()
1043 result->pic_type = PIC_TYPE_MAX; in wave5_vpu_dec_get_result()
1044 if ((nal_unit_type == 19 || nal_unit_type == 20) && result->pic_type == PIC_TYPE_I) in wave5_vpu_dec_get_result()
1046 result->pic_type = PIC_TYPE_IDR; in wave5_vpu_dec_get_result()
1047 } else if (inst->std == W_AVC_DEC) { in wave5_vpu_dec_get_result()
1049 result->pic_type = PIC_TYPE_B; in wave5_vpu_dec_get_result()
1051 result->pic_type = PIC_TYPE_P; in wave5_vpu_dec_get_result()
1053 result->pic_type = PIC_TYPE_I; in wave5_vpu_dec_get_result()
1055 result->pic_type = PIC_TYPE_MAX; in wave5_vpu_dec_get_result()
1056 if (nal_unit_type == 5 && result->pic_type == PIC_TYPE_I) in wave5_vpu_dec_get_result()
1057 result->pic_type = PIC_TYPE_IDR; in wave5_vpu_dec_get_result()
1059 index = vpu_read_reg(inst->dev, W5_RET_DEC_DISPLAY_INDEX); in wave5_vpu_dec_get_result()
1060 result->index_frame_display = index; in wave5_vpu_dec_get_result()
1061 index = vpu_read_reg(inst->dev, W5_RET_DEC_DECODED_INDEX); in wave5_vpu_dec_get_result()
1062 result->index_frame_decoded = index; in wave5_vpu_dec_get_result()
1063 result->index_frame_decoded_for_tiled = index; in wave5_vpu_dec_get_result()
1065 sub_layer_info = vpu_read_reg(inst->dev, W5_RET_DEC_SUB_LAYER_INFO); in wave5_vpu_dec_get_result()
1066 result->temporal_id = sub_layer_info & 0x7; in wave5_vpu_dec_get_result()
1068 if (inst->std == W_HEVC_DEC || inst->std == W_AVC_DEC) { in wave5_vpu_dec_get_result()
1069 result->decoded_poc = -1; in wave5_vpu_dec_get_result()
1070 if (result->index_frame_decoded >= 0 || in wave5_vpu_dec_get_result()
1071 result->index_frame_decoded == DECODED_IDX_FLAG_SKIP) in wave5_vpu_dec_get_result()
1072 result->decoded_poc = vpu_read_reg(inst->dev, W5_RET_DEC_PIC_POC); in wave5_vpu_dec_get_result()
1075 result->sequence_changed = vpu_read_reg(inst->dev, W5_RET_DEC_NOTIFICATION); in wave5_vpu_dec_get_result()
1076 reg_val = vpu_read_reg(inst->dev, W5_RET_DEC_PIC_SIZE); in wave5_vpu_dec_get_result()
1077 result->dec_pic_width = reg_val >> 16; in wave5_vpu_dec_get_result()
1078 result->dec_pic_height = reg_val & 0xffff; in wave5_vpu_dec_get_result()
1080 if (result->sequence_changed) { in wave5_vpu_dec_get_result()
1081 memcpy((void *)&p_dec_info->new_seq_info, (void *)&p_dec_info->initial_info, in wave5_vpu_dec_get_result()
1083 wave5_get_dec_seq_result(inst, &p_dec_info->new_seq_info); in wave5_vpu_dec_get_result()
1086 result->dec_host_cmd_tick = vpu_read_reg(inst->dev, W5_RET_DEC_HOST_CMD_TICK); in wave5_vpu_dec_get_result()
1087 result->dec_decode_end_tick = vpu_read_reg(inst->dev, W5_RET_DEC_DECODING_ENC_TICK); in wave5_vpu_dec_get_result()
1089 if (!p_dec_info->first_cycle_check) { in wave5_vpu_dec_get_result()
1090 result->frame_cycle = in wave5_vpu_dec_get_result()
1091 (result->dec_decode_end_tick - result->dec_host_cmd_tick) * in wave5_vpu_dec_get_result()
1092 p_dec_info->cycle_per_tick; in wave5_vpu_dec_get_result()
1093 vpu_dev->last_performance_cycles = result->dec_decode_end_tick; in wave5_vpu_dec_get_result()
1094 p_dec_info->first_cycle_check = true; in wave5_vpu_dec_get_result()
1095 } else if (result->index_frame_decoded_for_tiled != -1) { in wave5_vpu_dec_get_result()
1096 result->frame_cycle = in wave5_vpu_dec_get_result()
1097 (result->dec_decode_end_tick - vpu_dev->last_performance_cycles) * in wave5_vpu_dec_get_result()
1098 p_dec_info->cycle_per_tick; in wave5_vpu_dec_get_result()
1099 vpu_dev->last_performance_cycles = result->dec_decode_end_tick; in wave5_vpu_dec_get_result()
1100 if (vpu_dev->last_performance_cycles < result->dec_host_cmd_tick) in wave5_vpu_dec_get_result()
1101 result->frame_cycle = in wave5_vpu_dec_get_result()
1102 (result->dec_decode_end_tick - result->dec_host_cmd_tick) * in wave5_vpu_dec_get_result()
1103 p_dec_info->cycle_per_tick; in wave5_vpu_dec_get_result()
1107 if (p_dec_info->instance_queue_count == 0 && p_dec_info->report_queue_count == 0) in wave5_vpu_dec_get_result()
1108 p_dec_info->first_cycle_check = false; in wave5_vpu_dec_get_result()
1122 common_vb = &vpu_dev->common_mem; in wave5_vpu_re_init()
1124 code_base = common_vb->daddr; in wave5_vpu_re_init()
1126 if (vpu_dev->product_code == WAVE515_CODE) in wave5_vpu_re_init()
1134 return -EINVAL; in wave5_vpu_re_init()
1146 dev_err(vpu_dev->dev, in wave5_vpu_re_init()
1155 dev_err(vpu_dev->dev, "VPU init, Resetting the VPU, fail: %d\n", ret); in wave5_vpu_re_init()
1171 if (vpu_dev->product_code != WAVE515_CODE) { in wave5_vpu_re_init()
1190 if (vpu_dev->product_code == WAVE515_CODE) { in wave5_vpu_re_init()
1208 vpu_dev->sram_buf.daddr); in wave5_vpu_re_init()
1210 vpu_dev->sram_buf.size); in wave5_vpu_re_init()
1219 dev_err(vpu_dev->dev, "VPU reinit(W5_VPU_REMAP_CORE_START) timeout\n"); in wave5_vpu_re_init()
1264 common_vb = &vpu_dev->common_mem; in wave5_vpu_sleep_wake()
1266 code_base = common_vb->daddr; in wave5_vpu_sleep_wake()
1268 if (vpu_dev->product_code == WAVE515_CODE) in wave5_vpu_sleep_wake()
1277 return -EINVAL; in wave5_vpu_sleep_wake()
1296 if (vpu_dev->product_code != WAVE515_CODE) { in wave5_vpu_sleep_wake()
1317 if (vpu_dev->product_code == WAVE515_CODE) { in wave5_vpu_sleep_wake()
1335 vpu_dev->sram_buf.daddr); in wave5_vpu_sleep_wake()
1337 vpu_dev->sram_buf.size); in wave5_vpu_sleep_wake()
1347 dev_err(vpu_dev->dev, "VPU wakeup(W5_VPU_REMAP_CORE_START) timeout\n"); in wave5_vpu_sleep_wake()
1362 struct vpu_attr *p_attr = &vpu_dev->attr; in wave5_vpu_reset()
1374 p_attr->support_backbone = true; in wave5_vpu_reset()
1376 p_attr->support_vcore_backbone = true; in wave5_vpu_reset()
1378 p_attr->support_vcpu_backbone = true; in wave5_vpu_reset()
1381 if (p_attr->support_backbone) { in wave5_vpu_reset()
1384 if (p_attr->support_vcore_backbone) { in wave5_vpu_reset()
1385 if (p_attr->support_vcpu_backbone) { in wave5_vpu_reset()
1403 return -EBUSY; in wave5_vpu_reset()
1412 return -EBUSY; in wave5_vpu_reset()
1435 return -EINVAL; in wave5_vpu_reset()
1449 if (p_attr->support_backbone) { in wave5_vpu_reset()
1450 if (p_attr->support_vcore_backbone) { in wave5_vpu_reset()
1451 if (p_attr->support_vcpu_backbone) in wave5_vpu_reset()
1473 struct dec_info *p_dec_info = &inst->codec_info->dec_info; in wave5_vpu_dec_set_bitstream_flag()
1475 p_dec_info->stream_endflag = eos ? 1 : 0; in wave5_vpu_dec_set_bitstream_flag()
1476 vpu_write_reg(inst->dev, W5_BS_OPTION, get_bitstream_options(p_dec_info)); in wave5_vpu_dec_set_bitstream_flag()
1477 vpu_write_reg(inst->dev, W5_BS_WR_PTR, p_dec_info->stream_wr_ptr); in wave5_vpu_dec_set_bitstream_flag()
1484 struct dec_info *p_dec_info = &inst->codec_info->dec_info; in wave5_dec_clr_disp_flag()
1487 vpu_write_reg(inst->dev, W5_CMD_DEC_CLR_DISP_IDC, BIT(index)); in wave5_dec_clr_disp_flag()
1488 vpu_write_reg(inst->dev, W5_CMD_DEC_SET_DISP_IDC, 0); in wave5_dec_clr_disp_flag()
1490 ret = wave5_send_query(inst->dev, inst, UPDATE_DISP_FLAG); in wave5_dec_clr_disp_flag()
1494 p_dec_info->frame_display_flag = vpu_read_reg(inst->dev, W5_RET_DEC_DISP_IDC); in wave5_dec_clr_disp_flag()
1503 vpu_write_reg(inst->dev, W5_CMD_DEC_CLR_DISP_IDC, 0); in wave5_dec_set_disp_flag()
1504 vpu_write_reg(inst->dev, W5_CMD_DEC_SET_DISP_IDC, BIT(index)); in wave5_dec_set_disp_flag()
1506 ret = wave5_send_query(inst->dev, inst, UPDATE_DISP_FLAG); in wave5_dec_set_disp_flag()
1517 interrupt_reason = vpu_read_reg(inst->dev, W5_VPU_VINT_REASON_USR); in wave5_vpu_clear_interrupt()
1519 vpu_write_reg(inst->dev, W5_VPU_VINT_REASON_USR, interrupt_reason); in wave5_vpu_clear_interrupt()
1528 ret = wave5_send_query(inst->dev, inst, GET_BS_RD_PTR); in wave5_dec_get_rd_ptr()
1530 return inst->codec_info->dec_info.stream_rd_ptr; in wave5_dec_get_rd_ptr()
1532 return vpu_read_reg(inst->dev, W5_RET_QUERY_DEC_BS_RD_PTR); in wave5_dec_get_rd_ptr()
1539 vpu_write_reg(inst->dev, W5_RET_QUERY_DEC_SET_BS_RD_PTR, addr); in wave5_dec_set_rd_ptr()
1541 ret = wave5_send_query(inst->dev, inst, SET_BS_RD_PTR); in wave5_dec_set_rd_ptr()
1554 struct enc_info *p_enc_info = &inst->codec_info->enc_info; in wave5_vpu_build_up_enc_param()
1560 p_enc_info->cycle_per_tick = 256; in wave5_vpu_build_up_enc_param()
1561 if (vpu_dev->sram_buf.size) { in wave5_vpu_build_up_enc_param()
1562 p_enc_info->sec_axi_info.use_enc_rdo_enable = 1; in wave5_vpu_build_up_enc_param()
1563 p_enc_info->sec_axi_info.use_enc_lf_enable = 1; in wave5_vpu_build_up_enc_param()
1566 p_enc_info->vb_work.size = WAVE521ENC_WORKBUF_SIZE; in wave5_vpu_build_up_enc_param()
1567 ret = wave5_vdi_allocate_dma_memory(vpu_dev, &p_enc_info->vb_work); in wave5_vpu_build_up_enc_param()
1569 memset(&p_enc_info->vb_work, 0, sizeof(p_enc_info->vb_work)); in wave5_vpu_build_up_enc_param()
1573 wave5_vdi_clear_memory(vpu_dev, &p_enc_info->vb_work); in wave5_vpu_build_up_enc_param()
1575 vpu_write_reg(inst->dev, W5_ADDR_WORK_BASE, p_enc_info->vb_work.daddr); in wave5_vpu_build_up_enc_param()
1576 vpu_write_reg(inst->dev, W5_WORK_SIZE, p_enc_info->vb_work.size); in wave5_vpu_build_up_enc_param()
1578 vpu_write_reg(inst->dev, W5_CMD_ADDR_SEC_AXI, vpu_dev->sram_buf.daddr); in wave5_vpu_build_up_enc_param()
1579 vpu_write_reg(inst->dev, W5_CMD_SEC_AXI_SIZE, vpu_dev->sram_buf.size); in wave5_vpu_build_up_enc_param()
1581 reg_val = (open_param->line_buf_int_en << 6) | BITSTREAM_ENDIANNESS_BIG_ENDIAN; in wave5_vpu_build_up_enc_param()
1582 vpu_write_reg(inst->dev, W5_CMD_BS_PARAM, reg_val); in wave5_vpu_build_up_enc_param()
1583 vpu_write_reg(inst->dev, W5_CMD_EXT_ADDR, 0); in wave5_vpu_build_up_enc_param()
1584 vpu_write_reg(inst->dev, W5_CMD_NUM_CQ_DEPTH_M1, WAVE521_COMMAND_QUEUE_DEPTH - 1); in wave5_vpu_build_up_enc_param()
1587 vpu_write_reg(inst->dev, W5_CMD_ENC_SRC_OPTIONS, 0); in wave5_vpu_build_up_enc_param()
1588 vpu_write_reg(inst->dev, W5_CMD_ENC_VCORE_INFO, 1); in wave5_vpu_build_up_enc_param()
1594 buffer_addr = open_param->bitstream_buffer; in wave5_vpu_build_up_enc_param()
1595 buffer_size = open_param->bitstream_buffer_size; in wave5_vpu_build_up_enc_param()
1596 p_enc_info->stream_rd_ptr = buffer_addr; in wave5_vpu_build_up_enc_param()
1597 p_enc_info->stream_wr_ptr = buffer_addr; in wave5_vpu_build_up_enc_param()
1598 p_enc_info->line_buf_int_en = open_param->line_buf_int_en; in wave5_vpu_build_up_enc_param()
1599 p_enc_info->stream_buf_start_addr = buffer_addr; in wave5_vpu_build_up_enc_param()
1600 p_enc_info->stream_buf_size = buffer_size; in wave5_vpu_build_up_enc_param()
1601 p_enc_info->stream_buf_end_addr = buffer_addr + buffer_size; in wave5_vpu_build_up_enc_param()
1602 p_enc_info->stride = 0; in wave5_vpu_build_up_enc_param()
1603 p_enc_info->initial_info_obtained = false; in wave5_vpu_build_up_enc_param()
1604 p_enc_info->product_code = vpu_read_reg(inst->dev, W5_PRODUCT_NUMBER); in wave5_vpu_build_up_enc_param()
1608 if (wave5_vdi_free_dma_memory(vpu_dev, &p_enc_info->vb_work)) in wave5_vpu_build_up_enc_param()
1609 memset(&p_enc_info->vb_work, 0, sizeof(p_enc_info->vb_work)); in wave5_vpu_build_up_enc_param()
1626 pad_right = aligned_width - src_width; in wave5_set_enc_crop_info()
1627 pad_bot = aligned_height - src_height; in wave5_set_enc_crop_info()
1629 if (param->conf_win_right > 0) in wave5_set_enc_crop_info()
1630 crop_right = param->conf_win_right + pad_right; in wave5_set_enc_crop_info()
1634 if (param->conf_win_bot > 0) in wave5_set_enc_crop_info()
1635 crop_bot = param->conf_win_bot + pad_bot; in wave5_set_enc_crop_info()
1639 crop_top = param->conf_win_top; in wave5_set_enc_crop_info()
1640 crop_left = param->conf_win_left; in wave5_set_enc_crop_info()
1642 param->conf_win_top = crop_top; in wave5_set_enc_crop_info()
1643 param->conf_win_left = crop_left; in wave5_set_enc_crop_info()
1644 param->conf_win_bot = crop_bot; in wave5_set_enc_crop_info()
1645 param->conf_win_right = crop_right; in wave5_set_enc_crop_info()
1652 param->conf_win_top = crop_right; in wave5_set_enc_crop_info()
1653 param->conf_win_left = crop_top; in wave5_set_enc_crop_info()
1654 param->conf_win_bot = crop_left; in wave5_set_enc_crop_info()
1655 param->conf_win_right = crop_bot; in wave5_set_enc_crop_info()
1659 param->conf_win_top = crop_bot; in wave5_set_enc_crop_info()
1660 param->conf_win_left = crop_right; in wave5_set_enc_crop_info()
1661 param->conf_win_bot = crop_top; in wave5_set_enc_crop_info()
1662 param->conf_win_right = crop_left; in wave5_set_enc_crop_info()
1666 param->conf_win_top = crop_left; in wave5_set_enc_crop_info()
1667 param->conf_win_left = crop_bot; in wave5_set_enc_crop_info()
1668 param->conf_win_bot = crop_right; in wave5_set_enc_crop_info()
1669 param->conf_win_right = crop_top; in wave5_set_enc_crop_info()
1673 param->conf_win_top = crop_bot; in wave5_set_enc_crop_info()
1674 param->conf_win_bot = crop_top; in wave5_set_enc_crop_info()
1678 param->conf_win_left = crop_right; in wave5_set_enc_crop_info()
1679 param->conf_win_right = crop_left; in wave5_set_enc_crop_info()
1683 param->conf_win_top = crop_left; in wave5_set_enc_crop_info()
1684 param->conf_win_left = crop_top; in wave5_set_enc_crop_info()
1685 param->conf_win_bot = crop_right; in wave5_set_enc_crop_info()
1686 param->conf_win_right = crop_bot; in wave5_set_enc_crop_info()
1690 param->conf_win_top = crop_right; in wave5_set_enc_crop_info()
1691 param->conf_win_left = crop_bot; in wave5_set_enc_crop_info()
1692 param->conf_win_bot = crop_left; in wave5_set_enc_crop_info()
1693 param->conf_win_right = crop_top; in wave5_set_enc_crop_info()
1696 WARN(1, "Invalid prp_mode: %d, must be in range of 1 - 15\n", prp_mode); in wave5_set_enc_crop_info()
1703 struct enc_info *p_enc_info = &inst->codec_info->enc_info; in wave5_vpu_enc_init_seq()
1704 struct enc_open_param *p_open_param = &p_enc_info->open_param; in wave5_vpu_enc_init_seq()
1705 struct enc_wave_param *p_param = &p_open_param->wave_param; in wave5_vpu_enc_init_seq()
1712 if (p_enc_info->rotation_enable) { in wave5_vpu_enc_init_seq()
1713 switch (p_enc_info->rotation_angle) { in wave5_vpu_enc_init_seq()
1729 if (p_enc_info->mirror_enable) { in wave5_vpu_enc_init_seq()
1730 switch (p_enc_info->mirror_direction) { in wave5_vpu_enc_init_seq()
1746 wave5_set_enc_crop_info(inst->std, p_param, rot_mir_mode, p_open_param->pic_width, in wave5_vpu_enc_init_seq()
1747 p_open_param->pic_height); in wave5_vpu_enc_init_seq()
1750 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_SET_PARAM_OPTION, OPT_COMMON); in wave5_vpu_enc_init_seq()
1751 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_SRC_SIZE, p_open_param->pic_height << 16 in wave5_vpu_enc_init_seq()
1752 | p_open_param->pic_width); in wave5_vpu_enc_init_seq()
1753 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_CUSTOM_MAP_ENDIAN, VDI_LITTLE_ENDIAN); in wave5_vpu_enc_init_seq()
1755 reg_val = p_param->profile | in wave5_vpu_enc_init_seq()
1756 (p_param->level << 3) | in wave5_vpu_enc_init_seq()
1757 (p_param->internal_bit_depth << 14); in wave5_vpu_enc_init_seq()
1758 if (inst->std == W_HEVC_ENC) in wave5_vpu_enc_init_seq()
1759 reg_val |= (p_param->tier << 12) | in wave5_vpu_enc_init_seq()
1760 (p_param->tmvp_enable << 23) | in wave5_vpu_enc_init_seq()
1761 (p_param->sao_enable << 24) | in wave5_vpu_enc_init_seq()
1762 (p_param->skip_intra_trans << 25) | in wave5_vpu_enc_init_seq()
1763 (p_param->strong_intra_smooth_enable << 27) | in wave5_vpu_enc_init_seq()
1764 (p_param->en_still_picture << 30); in wave5_vpu_enc_init_seq()
1765 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_SPS_PARAM, reg_val); in wave5_vpu_enc_init_seq()
1767 reg_val = (p_param->lossless_enable) | in wave5_vpu_enc_init_seq()
1768 (p_param->const_intra_pred_flag << 1) | in wave5_vpu_enc_init_seq()
1769 (p_param->lf_cross_slice_boundary_enable << 2) | in wave5_vpu_enc_init_seq()
1770 (p_param->wpp_enable << 4) | in wave5_vpu_enc_init_seq()
1771 (p_param->disable_deblk << 5) | in wave5_vpu_enc_init_seq()
1772 ((p_param->beta_offset_div2 & 0xF) << 6) | in wave5_vpu_enc_init_seq()
1773 ((p_param->tc_offset_div2 & 0xF) << 10) | in wave5_vpu_enc_init_seq()
1774 ((p_param->chroma_cb_qp_offset & 0x1F) << 14) | in wave5_vpu_enc_init_seq()
1775 ((p_param->chroma_cr_qp_offset & 0x1F) << 19) | in wave5_vpu_enc_init_seq()
1776 (p_param->transform8x8_enable << 29) | in wave5_vpu_enc_init_seq()
1777 (p_param->entropy_coding_mode << 30); in wave5_vpu_enc_init_seq()
1778 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_PPS_PARAM, reg_val); in wave5_vpu_enc_init_seq()
1780 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_GOP_PARAM, p_param->gop_preset_idx); in wave5_vpu_enc_init_seq()
1782 if (inst->std == W_AVC_ENC) in wave5_vpu_enc_init_seq()
1783 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_INTRA_PARAM, p_param->intra_qp | in wave5_vpu_enc_init_seq()
1784 ((p_param->intra_period & ENC_AVC_INTRA_IDR_PARAM_MASK) in wave5_vpu_enc_init_seq()
1786 ((p_param->avc_idr_period & ENC_AVC_INTRA_IDR_PARAM_MASK) in wave5_vpu_enc_init_seq()
1788 (p_param->forced_idr_header_enable in wave5_vpu_enc_init_seq()
1790 else if (inst->std == W_HEVC_ENC) in wave5_vpu_enc_init_seq()
1791 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_INTRA_PARAM, in wave5_vpu_enc_init_seq()
1792 p_param->decoding_refresh_type | in wave5_vpu_enc_init_seq()
1793 (p_param->intra_qp << ENC_HEVC_INTRA_QP_SHIFT) | in wave5_vpu_enc_init_seq()
1794 (p_param->forced_idr_header_enable in wave5_vpu_enc_init_seq()
1796 (p_param->intra_period << ENC_HEVC_INTRA_PERIOD_SHIFT)); in wave5_vpu_enc_init_seq()
1798 reg_val = (p_param->rdo_skip << 2) | in wave5_vpu_enc_init_seq()
1799 (p_param->lambda_scaling_enable << 3) | in wave5_vpu_enc_init_seq()
1801 (p_param->intra_nx_n_enable << 8) | in wave5_vpu_enc_init_seq()
1802 (p_param->max_num_merge << 18); in wave5_vpu_enc_init_seq()
1804 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_RDO_PARAM, reg_val); in wave5_vpu_enc_init_seq()
1806 if (inst->std == W_AVC_ENC) in wave5_vpu_enc_init_seq()
1807 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_INTRA_REFRESH, in wave5_vpu_enc_init_seq()
1808 p_param->intra_mb_refresh_arg << 16 | p_param->intra_mb_refresh_mode); in wave5_vpu_enc_init_seq()
1809 else if (inst->std == W_HEVC_ENC) in wave5_vpu_enc_init_seq()
1810 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_INTRA_REFRESH, in wave5_vpu_enc_init_seq()
1811 p_param->intra_refresh_arg << 16 | p_param->intra_refresh_mode); in wave5_vpu_enc_init_seq()
1813 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_RC_FRAME_RATE, p_open_param->frame_rate_info); in wave5_vpu_enc_init_seq()
1814 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_RC_TARGET_RATE, p_open_param->bit_rate); in wave5_vpu_enc_init_seq()
1816 reg_val = p_open_param->rc_enable | in wave5_vpu_enc_init_seq()
1817 (p_param->hvs_qp_enable << 2) | in wave5_vpu_enc_init_seq()
1818 (p_param->hvs_qp_scale << 4) | in wave5_vpu_enc_init_seq()
1819 ((p_param->initial_rc_qp & 0x3F) << 14) | in wave5_vpu_enc_init_seq()
1820 (p_open_param->vbv_buffer_size << 20); in wave5_vpu_enc_init_seq()
1821 if (inst->std == W_AVC_ENC) in wave5_vpu_enc_init_seq()
1822 reg_val |= (p_param->mb_level_rc_enable << 1); in wave5_vpu_enc_init_seq()
1823 else if (inst->std == W_HEVC_ENC) in wave5_vpu_enc_init_seq()
1824 reg_val |= (p_param->cu_level_rc_enable << 1); in wave5_vpu_enc_init_seq()
1825 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_RC_PARAM, reg_val); in wave5_vpu_enc_init_seq()
1827 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_RC_WEIGHT_PARAM, in wave5_vpu_enc_init_seq()
1828 p_param->rc_weight_buf << 8 | p_param->rc_weight_param); in wave5_vpu_enc_init_seq()
1830 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_RC_MIN_MAX_QP, p_param->min_qp_i | in wave5_vpu_enc_init_seq()
1831 (p_param->max_qp_i << 6) | (p_param->hvs_max_delta_qp << 12)); in wave5_vpu_enc_init_seq()
1833 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_RC_INTER_MIN_MAX_QP, p_param->min_qp_p | in wave5_vpu_enc_init_seq()
1834 (p_param->max_qp_p << 6) | (p_param->min_qp_b << 12) | in wave5_vpu_enc_init_seq()
1835 (p_param->max_qp_b << 18)); in wave5_vpu_enc_init_seq()
1837 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_RC_BIT_RATIO_LAYER_0_3, 0); in wave5_vpu_enc_init_seq()
1838 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_RC_BIT_RATIO_LAYER_4_7, 0); in wave5_vpu_enc_init_seq()
1839 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_ROT_PARAM, rot_mir_mode); in wave5_vpu_enc_init_seq()
1841 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_BG_PARAM, 0); in wave5_vpu_enc_init_seq()
1842 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_CUSTOM_LAMBDA_ADDR, 0); in wave5_vpu_enc_init_seq()
1843 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_CONF_WIN_TOP_BOT, in wave5_vpu_enc_init_seq()
1844 p_param->conf_win_bot << 16 | p_param->conf_win_top); in wave5_vpu_enc_init_seq()
1845 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_CONF_WIN_LEFT_RIGHT, in wave5_vpu_enc_init_seq()
1846 p_param->conf_win_right << 16 | p_param->conf_win_left); in wave5_vpu_enc_init_seq()
1848 if (inst->std == W_AVC_ENC) in wave5_vpu_enc_init_seq()
1849 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_INDEPENDENT_SLICE, in wave5_vpu_enc_init_seq()
1850 p_param->avc_slice_arg << 16 | p_param->avc_slice_mode); in wave5_vpu_enc_init_seq()
1851 else if (inst->std == W_HEVC_ENC) in wave5_vpu_enc_init_seq()
1852 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_INDEPENDENT_SLICE, in wave5_vpu_enc_init_seq()
1853 p_param->independ_slice_mode_arg << 16 | in wave5_vpu_enc_init_seq()
1854 p_param->independ_slice_mode); in wave5_vpu_enc_init_seq()
1856 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_USER_SCALING_LIST_ADDR, 0); in wave5_vpu_enc_init_seq()
1857 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_NUM_UNITS_IN_TICK, 0); in wave5_vpu_enc_init_seq()
1858 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_TIME_SCALE, 0); in wave5_vpu_enc_init_seq()
1859 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_NUM_TICKS_POC_DIFF_ONE, 0); in wave5_vpu_enc_init_seq()
1861 if (inst->std == W_HEVC_ENC) { in wave5_vpu_enc_init_seq()
1862 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_CUSTOM_MD_PU04, 0); in wave5_vpu_enc_init_seq()
1863 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_CUSTOM_MD_PU08, 0); in wave5_vpu_enc_init_seq()
1864 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_CUSTOM_MD_PU16, 0); in wave5_vpu_enc_init_seq()
1865 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_CUSTOM_MD_PU32, 0); in wave5_vpu_enc_init_seq()
1866 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_CUSTOM_MD_CU08, 0); in wave5_vpu_enc_init_seq()
1867 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_CUSTOM_MD_CU16, 0); in wave5_vpu_enc_init_seq()
1868 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_CUSTOM_MD_CU32, 0); in wave5_vpu_enc_init_seq()
1869 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_DEPENDENT_SLICE, in wave5_vpu_enc_init_seq()
1870 p_param->depend_slice_mode_arg << 16 | p_param->depend_slice_mode); in wave5_vpu_enc_init_seq()
1872 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_NR_PARAM, 0); in wave5_vpu_enc_init_seq()
1874 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_NR_WEIGHT, in wave5_vpu_enc_init_seq()
1875 p_param->nr_intra_weight_y | in wave5_vpu_enc_init_seq()
1876 (p_param->nr_intra_weight_cb << 5) | in wave5_vpu_enc_init_seq()
1877 (p_param->nr_intra_weight_cr << 10) | in wave5_vpu_enc_init_seq()
1878 (p_param->nr_inter_weight_y << 15) | in wave5_vpu_enc_init_seq()
1879 (p_param->nr_inter_weight_cb << 20) | in wave5_vpu_enc_init_seq()
1880 (p_param->nr_inter_weight_cr << 25)); in wave5_vpu_enc_init_seq()
1882 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_VUI_HRD_PARAM, 0); in wave5_vpu_enc_init_seq()
1891 struct enc_info *p_enc_info = &inst->codec_info->enc_info; in wave5_vpu_enc_get_seq_info()
1894 ret = wave5_send_query(inst->dev, inst, GET_RESULT); in wave5_vpu_enc_get_seq_info()
1898 dev_dbg(inst->dev->dev, "%s: init seq\n", __func__); in wave5_vpu_enc_get_seq_info()
1900 reg_val = vpu_read_reg(inst->dev, W5_RET_QUEUE_STATUS); in wave5_vpu_enc_get_seq_info()
1902 p_enc_info->instance_queue_count = (reg_val >> 16) & 0xff; in wave5_vpu_enc_get_seq_info()
1903 p_enc_info->report_queue_count = (reg_val & QUEUE_REPORT_MASK); in wave5_vpu_enc_get_seq_info()
1905 if (vpu_read_reg(inst->dev, W5_RET_ENC_ENCODING_SUCCESS) != 1) { in wave5_vpu_enc_get_seq_info()
1906 info->seq_init_err_reason = vpu_read_reg(inst->dev, W5_RET_ENC_ERR_INFO); in wave5_vpu_enc_get_seq_info()
1907 ret = -EIO; in wave5_vpu_enc_get_seq_info()
1909 info->warn_info = vpu_read_reg(inst->dev, W5_RET_ENC_WARN_INFO); in wave5_vpu_enc_get_seq_info()
1912 info->min_frame_buffer_count = vpu_read_reg(inst->dev, W5_RET_ENC_NUM_REQUIRED_FB); in wave5_vpu_enc_get_seq_info()
1913 info->min_src_frame_count = vpu_read_reg(inst->dev, W5_RET_ENC_MIN_SRC_BUF_NUM); in wave5_vpu_enc_get_seq_info()
1914 info->vlc_buf_size = vpu_read_reg(inst->dev, W5_RET_VLC_BUF_SIZE); in wave5_vpu_enc_get_seq_info()
1915 info->param_buf_size = vpu_read_reg(inst->dev, W5_RET_PARAM_BUF_SIZE); in wave5_vpu_enc_get_seq_info()
1916 p_enc_info->vlc_buf_size = info->vlc_buf_size; in wave5_vpu_enc_get_seq_info()
1917 p_enc_info->param_buf_size = info->param_buf_size; in wave5_vpu_enc_get_seq_info()
1946 bool avc_encoding = (inst->std == W_AVC_ENC); in wave5_vpu_enc_register_framebuffer()
1953 struct enc_info *p_enc_info = &inst->codec_info->enc_info; in wave5_vpu_enc_register_framebuffer()
1955 p_open_param = &p_enc_info->open_param; in wave5_vpu_enc_register_framebuffer()
1959 stride = p_enc_info->stride; in wave5_vpu_enc_register_framebuffer()
1960 bit_depth = p_open_param->wave_param.internal_bit_depth; in wave5_vpu_enc_register_framebuffer()
1963 buf_width = ALIGN(p_open_param->pic_width, 16); in wave5_vpu_enc_register_framebuffer()
1964 buf_height = ALIGN(p_open_param->pic_height, 16); in wave5_vpu_enc_register_framebuffer()
1966 if ((p_enc_info->rotation_angle || p_enc_info->mirror_direction) && in wave5_vpu_enc_register_framebuffer()
1967 !(p_enc_info->rotation_angle == 180 && in wave5_vpu_enc_register_framebuffer()
1968 p_enc_info->mirror_direction == MIRDIR_HOR_VER)) { in wave5_vpu_enc_register_framebuffer()
1969 buf_width = ALIGN(p_open_param->pic_width, 16); in wave5_vpu_enc_register_framebuffer()
1970 buf_height = ALIGN(p_open_param->pic_height, 16); in wave5_vpu_enc_register_framebuffer()
1973 if (p_enc_info->rotation_angle == 90 || p_enc_info->rotation_angle == 270) { in wave5_vpu_enc_register_framebuffer()
1974 buf_width = ALIGN(p_open_param->pic_height, 16); in wave5_vpu_enc_register_framebuffer()
1975 buf_height = ALIGN(p_open_param->pic_width, 16); in wave5_vpu_enc_register_framebuffer()
1978 buf_width = ALIGN(p_open_param->pic_width, 8); in wave5_vpu_enc_register_framebuffer()
1979 buf_height = ALIGN(p_open_param->pic_height, 8); in wave5_vpu_enc_register_framebuffer()
1981 if ((p_enc_info->rotation_angle || p_enc_info->mirror_direction) && in wave5_vpu_enc_register_framebuffer()
1982 !(p_enc_info->rotation_angle == 180 && in wave5_vpu_enc_register_framebuffer()
1983 p_enc_info->mirror_direction == MIRDIR_HOR_VER)) { in wave5_vpu_enc_register_framebuffer()
1984 buf_width = ALIGN(p_open_param->pic_width, 32); in wave5_vpu_enc_register_framebuffer()
1985 buf_height = ALIGN(p_open_param->pic_height, 32); in wave5_vpu_enc_register_framebuffer()
1988 if (p_enc_info->rotation_angle == 90 || p_enc_info->rotation_angle == 270) { in wave5_vpu_enc_register_framebuffer()
1989 buf_width = ALIGN(p_open_param->pic_height, 32); in wave5_vpu_enc_register_framebuffer()
1990 buf_height = ALIGN(p_open_param->pic_width, 32); in wave5_vpu_enc_register_framebuffer()
2011 p_enc_info->vb_mv = vb_mv; in wave5_vpu_enc_register_framebuffer()
2022 p_enc_info->vb_fbc_y_tbl = vb_fbc_y_tbl; in wave5_vpu_enc_register_framebuffer()
2030 p_enc_info->vb_fbc_c_tbl = vb_fbc_c_tbl; in wave5_vpu_enc_register_framebuffer()
2042 p_enc_info->vb_sub_sam_buf = vb_sub_sam_buf; in wave5_vpu_enc_register_framebuffer()
2044 vb_task.size = (p_enc_info->vlc_buf_size * VLC_BUF_NUM) + in wave5_vpu_enc_register_framebuffer()
2045 (p_enc_info->param_buf_size * WAVE521_COMMAND_QUEUE_DEPTH); in wave5_vpu_enc_register_framebuffer()
2047 if (p_enc_info->vb_task.size == 0) { in wave5_vpu_enc_register_framebuffer()
2052 p_enc_info->vb_task = vb_task; in wave5_vpu_enc_register_framebuffer()
2054 vpu_write_reg(inst->dev, W5_CMD_SET_FB_ADDR_TASK_BUF, in wave5_vpu_enc_register_framebuffer()
2055 p_enc_info->vb_task.daddr); in wave5_vpu_enc_register_framebuffer()
2056 vpu_write_reg(inst->dev, W5_CMD_SET_FB_TASK_BUF_SIZE, vb_task.size); in wave5_vpu_enc_register_framebuffer()
2059 /* set sub-sampled buffer base addr */ in wave5_vpu_enc_register_framebuffer()
2060 vpu_write_reg(inst->dev, W5_ADDR_SUB_SAMPLED_FB_BASE, vb_sub_sam_buf.daddr); in wave5_vpu_enc_register_framebuffer()
2061 /* set sub-sampled buffer size for one frame */ in wave5_vpu_enc_register_framebuffer()
2062 vpu_write_reg(inst->dev, W5_SUB_SAMPLED_ONE_FB_SIZE, sub_sampled_size); in wave5_vpu_enc_register_framebuffer()
2064 vpu_write_reg(inst->dev, W5_PIC_SIZE, pic_size); in wave5_vpu_enc_register_framebuffer()
2067 if ((p_enc_info->rotation_angle || p_enc_info->mirror_direction) && in wave5_vpu_enc_register_framebuffer()
2068 !(p_enc_info->rotation_angle == 180 && in wave5_vpu_enc_register_framebuffer()
2069 p_enc_info->mirror_direction == MIRDIR_HOR_VER)) { in wave5_vpu_enc_register_framebuffer()
2073 luma_stride = calculate_luma_stride(p_open_param->pic_width, bit_depth); in wave5_vpu_enc_register_framebuffer()
2074 chroma_stride = calculate_chroma_stride(p_open_param->pic_width / 2, bit_depth); in wave5_vpu_enc_register_framebuffer()
2077 vpu_write_reg(inst->dev, W5_FBC_STRIDE, luma_stride << 16 | chroma_stride); in wave5_vpu_enc_register_framebuffer()
2078 vpu_write_reg(inst->dev, W5_COMMON_PIC_INFO, stride); in wave5_vpu_enc_register_framebuffer()
2084 reg_val = (j == cnt_8_chunk - 1) << 4 | ((j == 0) << 3); in wave5_vpu_enc_register_framebuffer()
2085 vpu_write_reg(inst->dev, W5_SFB_OPTION, reg_val); in wave5_vpu_enc_register_framebuffer()
2087 end_no = start_no + ((remain >= 8) ? 8 : remain) - 1; in wave5_vpu_enc_register_framebuffer()
2089 vpu_write_reg(inst->dev, W5_SET_FB_NUM, (start_no << 8) | end_no); in wave5_vpu_enc_register_framebuffer()
2092 vpu_write_reg(inst->dev, W5_ADDR_LUMA_BASE0 + (i << 4), fb_arr[i + in wave5_vpu_enc_register_framebuffer()
2094 vpu_write_reg(inst->dev, W5_ADDR_CB_BASE0 + (i << 4), in wave5_vpu_enc_register_framebuffer()
2097 vpu_write_reg(inst->dev, W5_ADDR_FBC_Y_OFFSET0 + (i << 4), in wave5_vpu_enc_register_framebuffer()
2100 vpu_write_reg(inst->dev, W5_ADDR_FBC_C_OFFSET0 + (i << 4), in wave5_vpu_enc_register_framebuffer()
2103 vpu_write_reg(inst->dev, W5_ADDR_MV_COL0 + (i << 2), in wave5_vpu_enc_register_framebuffer()
2107 remain -= i; in wave5_vpu_enc_register_framebuffer()
2135 struct enc_info *p_enc_info = &inst->codec_info->enc_info; in wave5_vpu_enc_validate_sec_axi()
2137 u32 sram_size = inst->dev->sram_size; in wave5_vpu_enc_validate_sec_axi()
2143 * TODO: calculate rdo_size and lf_size from inst->src_fmt.width and in wave5_vpu_enc_validate_sec_axi()
2144 * inst->codec_info->enc_info.open_param.wave_param.internal_bit_depth in wave5_vpu_enc_validate_sec_axi()
2147 if (p_enc_info->sec_axi_info.use_enc_rdo_enable && sram_size >= rdo_size) { in wave5_vpu_enc_validate_sec_axi()
2149 sram_size -= rdo_size; in wave5_vpu_enc_validate_sec_axi()
2152 if (p_enc_info->sec_axi_info.use_enc_lf_enable && sram_size >= lf_size) in wave5_vpu_enc_validate_sec_axi()
2163 struct enc_info *p_enc_info = &inst->codec_info->enc_info; in wave5_vpu_encode()
2164 struct frame_buffer *p_src_frame = option->source_frame; in wave5_vpu_encode()
2165 struct enc_open_param *p_open_param = &p_enc_info->open_param; in wave5_vpu_encode()
2166 bool justified = WTL_RIGHT_JUSTIFIED; in wave5_vpu_encode() local
2170 vpu_write_reg(inst->dev, W5_CMD_ENC_BS_START_ADDR, option->pic_stream_buffer_addr); in wave5_vpu_encode()
2171 vpu_write_reg(inst->dev, W5_CMD_ENC_BS_SIZE, option->pic_stream_buffer_size); in wave5_vpu_encode()
2172 p_enc_info->stream_buf_start_addr = option->pic_stream_buffer_addr; in wave5_vpu_encode()
2173 p_enc_info->stream_buf_size = option->pic_stream_buffer_size; in wave5_vpu_encode()
2174 p_enc_info->stream_buf_end_addr = in wave5_vpu_encode()
2175 option->pic_stream_buffer_addr + option->pic_stream_buffer_size; in wave5_vpu_encode()
2177 vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_SRC_AXI_SEL, DEFAULT_SRC_AXI); in wave5_vpu_encode()
2180 vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_USE_SEC_AXI, reg_val); in wave5_vpu_encode()
2182 vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_REPORT_PARAM, 0); in wave5_vpu_encode()
2188 if (option->code_option.implicit_header_encode) in wave5_vpu_encode()
2189 vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_CODE_OPTION, in wave5_vpu_encode()
2191 (option->code_option.encode_aud << 5) | in wave5_vpu_encode()
2192 (option->code_option.encode_eos << 6) | in wave5_vpu_encode()
2193 (option->code_option.encode_eob << 7)); in wave5_vpu_encode()
2195 vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_CODE_OPTION, in wave5_vpu_encode()
2196 option->code_option.implicit_header_encode | in wave5_vpu_encode()
2197 (option->code_option.encode_vcl << 1) | in wave5_vpu_encode()
2198 (option->code_option.encode_vps << 2) | in wave5_vpu_encode()
2199 (option->code_option.encode_sps << 3) | in wave5_vpu_encode()
2200 (option->code_option.encode_pps << 4) | in wave5_vpu_encode()
2201 (option->code_option.encode_aud << 5) | in wave5_vpu_encode()
2202 (option->code_option.encode_eos << 6) | in wave5_vpu_encode()
2203 (option->code_option.encode_eob << 7)); in wave5_vpu_encode()
2205 vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_PIC_PARAM, 0); in wave5_vpu_encode()
2207 if (option->src_end_flag) in wave5_vpu_encode()
2209 vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_SRC_PIC_IDX, 0xFFFFFFFF); in wave5_vpu_encode()
2211 vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_SRC_PIC_IDX, option->src_idx); in wave5_vpu_encode()
2213 vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_SRC_ADDR_Y, p_src_frame->buf_y); in wave5_vpu_encode()
2214 vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_SRC_ADDR_U, p_src_frame->buf_cb); in wave5_vpu_encode()
2215 vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_SRC_ADDR_V, p_src_frame->buf_cr); in wave5_vpu_encode()
2217 switch (p_open_param->src_format) { in wave5_vpu_encode()
2224 justified = WTL_LEFT_JUSTIFIED; in wave5_vpu_encode()
2226 src_stride_c = inst->cbcr_interleave ? p_src_frame->stride : in wave5_vpu_encode()
2227 (p_src_frame->stride / 2); in wave5_vpu_encode()
2228 src_stride_c = (p_open_param->src_format == FORMAT_422) ? src_stride_c * 2 : in wave5_vpu_encode()
2237 justified = WTL_RIGHT_JUSTIFIED; in wave5_vpu_encode()
2239 src_stride_c = inst->cbcr_interleave ? p_src_frame->stride : in wave5_vpu_encode()
2240 (p_src_frame->stride / 2); in wave5_vpu_encode()
2241 src_stride_c = (p_open_param->src_format == in wave5_vpu_encode()
2250 justified = WTL_LEFT_JUSTIFIED; in wave5_vpu_encode()
2252 src_stride_c = inst->cbcr_interleave ? p_src_frame->stride : in wave5_vpu_encode()
2253 (p_src_frame->stride / 2); in wave5_vpu_encode()
2254 src_stride_c = (p_open_param->src_format == in wave5_vpu_encode()
2263 justified = WTL_RIGHT_JUSTIFIED; in wave5_vpu_encode()
2265 src_stride_c = inst->cbcr_interleave ? p_src_frame->stride : in wave5_vpu_encode()
2266 ALIGN(p_src_frame->stride / 2, 16) * BIT(inst->cbcr_interleave); in wave5_vpu_encode()
2267 src_stride_c = (p_open_param->src_format == in wave5_vpu_encode()
2276 justified = WTL_LEFT_JUSTIFIED; in wave5_vpu_encode()
2278 src_stride_c = inst->cbcr_interleave ? p_src_frame->stride : in wave5_vpu_encode()
2279 ALIGN(p_src_frame->stride / 2, 16) * BIT(inst->cbcr_interleave); in wave5_vpu_encode()
2280 src_stride_c = (p_open_param->src_format == in wave5_vpu_encode()
2284 return -EINVAL; in wave5_vpu_encode()
2287 src_frame_format = (inst->cbcr_interleave << 1) | (inst->nv21); in wave5_vpu_encode()
2288 switch (p_open_param->packed_format) { in wave5_vpu_encode()
2305 vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_SRC_STRIDE, in wave5_vpu_encode()
2306 (p_src_frame->stride << 16) | src_stride_c); in wave5_vpu_encode()
2307 vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_SRC_FORMAT, src_frame_format | in wave5_vpu_encode()
2308 (format_no << 3) | (justified << 5) | (PIC_SRC_ENDIANNESS_BIG_ENDIAN << 6)); in wave5_vpu_encode()
2310 vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_CUSTOM_MAP_OPTION_ADDR, 0); in wave5_vpu_encode()
2311 vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_CUSTOM_MAP_OPTION_PARAM, 0); in wave5_vpu_encode()
2312 vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_LONGTERM_PIC, 0); in wave5_vpu_encode()
2313 vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_WP_PIXEL_SIGMA_Y, 0); in wave5_vpu_encode()
2314 vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_WP_PIXEL_SIGMA_C, 0); in wave5_vpu_encode()
2315 vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_WP_PIXEL_MEAN_Y, 0); in wave5_vpu_encode()
2316 vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_WP_PIXEL_MEAN_C, 0); in wave5_vpu_encode()
2317 vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_PREFIX_SEI_INFO, 0); in wave5_vpu_encode()
2318 vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_PREFIX_SEI_NAL_ADDR, 0); in wave5_vpu_encode()
2319 vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_SUFFIX_SEI_INFO, 0); in wave5_vpu_encode()
2320 vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_SUFFIX_SEI_NAL_ADDR, 0); in wave5_vpu_encode()
2323 if (ret == -ETIMEDOUT) in wave5_vpu_encode()
2326 p_enc_info->instance_queue_count = (reg_val >> 16) & 0xff; in wave5_vpu_encode()
2327 p_enc_info->report_queue_count = (reg_val & QUEUE_REPORT_MASK); in wave5_vpu_encode()
2340 struct enc_info *p_enc_info = &inst->codec_info->enc_info; in wave5_vpu_enc_get_result()
2341 struct vpu_device *vpu_dev = inst->dev; in wave5_vpu_enc_get_result()
2343 ret = wave5_send_query(inst->dev, inst, GET_RESULT); in wave5_vpu_enc_get_result()
2347 dev_dbg(inst->dev->dev, "%s: enc pic complete\n", __func__); in wave5_vpu_enc_get_result()
2349 reg_val = vpu_read_reg(inst->dev, W5_RET_QUEUE_STATUS); in wave5_vpu_enc_get_result()
2351 p_enc_info->instance_queue_count = (reg_val >> 16) & 0xff; in wave5_vpu_enc_get_result()
2352 p_enc_info->report_queue_count = (reg_val & QUEUE_REPORT_MASK); in wave5_vpu_enc_get_result()
2354 encoding_success = vpu_read_reg(inst->dev, W5_RET_ENC_ENCODING_SUCCESS); in wave5_vpu_enc_get_result()
2356 result->error_reason = vpu_read_reg(inst->dev, W5_RET_ENC_ERR_INFO); in wave5_vpu_enc_get_result()
2357 return -EIO; in wave5_vpu_enc_get_result()
2360 result->warn_info = vpu_read_reg(inst->dev, W5_RET_ENC_WARN_INFO); in wave5_vpu_enc_get_result()
2362 reg_val = vpu_read_reg(inst->dev, W5_RET_ENC_PIC_TYPE); in wave5_vpu_enc_get_result()
2363 result->pic_type = reg_val & 0xFFFF; in wave5_vpu_enc_get_result()
2365 result->enc_vcl_nut = vpu_read_reg(inst->dev, W5_RET_ENC_VCL_NUT); in wave5_vpu_enc_get_result()
2368 * inst->frame_buf in wave5_vpu_enc_get_result()
2370 result->recon_frame_index = vpu_read_reg(inst->dev, W5_RET_ENC_PIC_IDX); in wave5_vpu_enc_get_result()
2371 result->enc_pic_byte = vpu_read_reg(inst->dev, W5_RET_ENC_PIC_BYTE); in wave5_vpu_enc_get_result()
2372 result->enc_src_idx = vpu_read_reg(inst->dev, W5_RET_ENC_USED_SRC_IDX); in wave5_vpu_enc_get_result()
2373 p_enc_info->stream_wr_ptr = vpu_read_reg(inst->dev, W5_RET_ENC_WR_PTR); in wave5_vpu_enc_get_result()
2374 p_enc_info->stream_rd_ptr = vpu_read_reg(inst->dev, W5_RET_ENC_RD_PTR); in wave5_vpu_enc_get_result()
2376 result->bitstream_buffer = vpu_read_reg(inst->dev, W5_RET_ENC_RD_PTR); in wave5_vpu_enc_get_result()
2377 result->rd_ptr = p_enc_info->stream_rd_ptr; in wave5_vpu_enc_get_result()
2378 result->wr_ptr = p_enc_info->stream_wr_ptr; in wave5_vpu_enc_get_result()
2381 if (result->recon_frame_index == RECON_IDX_FLAG_HEADER_ONLY) in wave5_vpu_enc_get_result()
2382 result->bitstream_size = result->enc_pic_byte; in wave5_vpu_enc_get_result()
2383 else if (result->recon_frame_index < 0) in wave5_vpu_enc_get_result()
2384 result->bitstream_size = 0; in wave5_vpu_enc_get_result()
2386 result->bitstream_size = result->enc_pic_byte; in wave5_vpu_enc_get_result()
2388 result->enc_host_cmd_tick = vpu_read_reg(inst->dev, W5_RET_ENC_HOST_CMD_TICK); in wave5_vpu_enc_get_result()
2389 result->enc_encode_end_tick = vpu_read_reg(inst->dev, W5_RET_ENC_ENCODING_END_TICK); in wave5_vpu_enc_get_result()
2391 if (!p_enc_info->first_cycle_check) { in wave5_vpu_enc_get_result()
2392 result->frame_cycle = (result->enc_encode_end_tick - result->enc_host_cmd_tick) * in wave5_vpu_enc_get_result()
2393 p_enc_info->cycle_per_tick; in wave5_vpu_enc_get_result()
2394 p_enc_info->first_cycle_check = true; in wave5_vpu_enc_get_result()
2396 result->frame_cycle = in wave5_vpu_enc_get_result()
2397 (result->enc_encode_end_tick - vpu_dev->last_performance_cycles) * in wave5_vpu_enc_get_result()
2398 p_enc_info->cycle_per_tick; in wave5_vpu_enc_get_result()
2399 if (vpu_dev->last_performance_cycles < result->enc_host_cmd_tick) in wave5_vpu_enc_get_result()
2400 result->frame_cycle = (result->enc_encode_end_tick - in wave5_vpu_enc_get_result()
2401 result->enc_host_cmd_tick) * p_enc_info->cycle_per_tick; in wave5_vpu_enc_get_result()
2403 vpu_dev->last_performance_cycles = result->enc_encode_end_tick; in wave5_vpu_enc_get_result()
2417 struct enc_wave_param *param = &open_param->wave_param; in wave5_vpu_enc_check_common_param_valid()
2418 struct vpu_device *vpu_dev = inst->dev; in wave5_vpu_enc_check_common_param_valid()
2419 struct device *dev = vpu_dev->dev; in wave5_vpu_enc_check_common_param_valid()
2420 u32 num_ctu_row = (open_param->pic_height + 64 - 1) / 64; in wave5_vpu_enc_check_common_param_valid()
2421 u32 num_ctu_col = (open_param->pic_width + 64 - 1) / 64; in wave5_vpu_enc_check_common_param_valid()
2424 if (inst->std == W_HEVC_ENC && low_delay && in wave5_vpu_enc_check_common_param_valid()
2425 param->decoding_refresh_type == DEC_REFRESH_TYPE_CRA) { in wave5_vpu_enc_check_common_param_valid()
2429 param->decoding_refresh_type = 2; in wave5_vpu_enc_check_common_param_valid()
2432 if (param->wpp_enable && param->independ_slice_mode) { in wave5_vpu_enc_check_common_param_valid()
2433 unsigned int num_ctb_in_width = ALIGN(open_param->pic_width, 64) >> 6; in wave5_vpu_enc_check_common_param_valid()
2435 if (param->independ_slice_mode_arg % num_ctb_in_width) { in wave5_vpu_enc_check_common_param_valid()
2437 param->independ_slice_mode_arg, num_ctb_in_width); in wave5_vpu_enc_check_common_param_valid()
2442 /* multi-slice & wpp */ in wave5_vpu_enc_check_common_param_valid()
2443 if (param->wpp_enable && param->depend_slice_mode) { in wave5_vpu_enc_check_common_param_valid()
2448 if (!param->independ_slice_mode && param->depend_slice_mode) { in wave5_vpu_enc_check_common_param_valid()
2451 } else if (param->independ_slice_mode && in wave5_vpu_enc_check_common_param_valid()
2452 param->depend_slice_mode == DEPEND_SLICE_MODE_RECOMMENDED && in wave5_vpu_enc_check_common_param_valid()
2453 param->independ_slice_mode_arg < param->depend_slice_mode_arg) { in wave5_vpu_enc_check_common_param_valid()
2455 param->independ_slice_mode_arg, param->depend_slice_mode_arg); in wave5_vpu_enc_check_common_param_valid()
2459 if (param->independ_slice_mode && param->independ_slice_mode_arg > 65535) { in wave5_vpu_enc_check_common_param_valid()
2461 param->independ_slice_mode_arg); in wave5_vpu_enc_check_common_param_valid()
2465 if (param->depend_slice_mode && param->depend_slice_mode_arg > 65535) { in wave5_vpu_enc_check_common_param_valid()
2467 param->depend_slice_mode_arg); in wave5_vpu_enc_check_common_param_valid()
2471 if (param->conf_win_top % 2) { in wave5_vpu_enc_check_common_param_valid()
2472 dev_err(dev, "conf_win_top: %u, must be a multiple of 2\n", param->conf_win_top); in wave5_vpu_enc_check_common_param_valid()
2476 if (param->conf_win_bot % 2) { in wave5_vpu_enc_check_common_param_valid()
2477 dev_err(dev, "conf_win_bot: %u, must be a multiple of 2\n", param->conf_win_bot); in wave5_vpu_enc_check_common_param_valid()
2481 if (param->conf_win_left % 2) { in wave5_vpu_enc_check_common_param_valid()
2482 dev_err(dev, "conf_win_left: %u, must be a multiple of 2\n", param->conf_win_left); in wave5_vpu_enc_check_common_param_valid()
2486 if (param->conf_win_right % 2) { in wave5_vpu_enc_check_common_param_valid()
2488 param->conf_win_right); in wave5_vpu_enc_check_common_param_valid()
2492 if (param->lossless_enable && open_param->rc_enable) { in wave5_vpu_enc_check_common_param_valid()
2497 if (param->lossless_enable && !param->skip_intra_trans) { in wave5_vpu_enc_check_common_param_valid()
2503 if (param->intra_refresh_mode && param->intra_refresh_arg == 0) { in wave5_vpu_enc_check_common_param_valid()
2505 param->intra_refresh_mode, param->intra_refresh_arg); in wave5_vpu_enc_check_common_param_valid()
2508 switch (param->intra_refresh_mode) { in wave5_vpu_enc_check_common_param_valid()
2510 if (param->intra_mb_refresh_arg > num_ctu_row) in wave5_vpu_enc_check_common_param_valid()
2514 if (param->intra_refresh_arg > num_ctu_col) in wave5_vpu_enc_check_common_param_valid()
2518 if (param->intra_refresh_arg > ctu_sz) in wave5_vpu_enc_check_common_param_valid()
2522 if (param->intra_refresh_arg > ctu_sz) in wave5_vpu_enc_check_common_param_valid()
2524 if (param->lossless_enable) { in wave5_vpu_enc_check_common_param_valid()
2526 param->intra_refresh_mode); in wave5_vpu_enc_check_common_param_valid()
2534 param->intra_refresh_mode, param->intra_refresh_arg, in wave5_vpu_enc_check_common_param_valid()
2542 struct enc_wave_param *param = &open_param->wave_param; in wave5_vpu_enc_check_param_valid()
2544 if (open_param->rc_enable) { in wave5_vpu_enc_check_param_valid()
2545 if (param->min_qp_i > param->max_qp_i || param->min_qp_p > param->max_qp_p || in wave5_vpu_enc_check_param_valid()
2546 param->min_qp_b > param->max_qp_b) { in wave5_vpu_enc_check_param_valid()
2547 dev_err(vpu_dev->dev, "Configuration failed because min_qp is greater than max_qp\n"); in wave5_vpu_enc_check_param_valid()
2548 dev_err(vpu_dev->dev, "Suggested configuration parameters: min_qp = max_qp\n"); in wave5_vpu_enc_check_param_valid()
2552 if (open_param->bit_rate <= (int)open_param->frame_rate_info) { in wave5_vpu_enc_check_param_valid()
2553 dev_err(vpu_dev->dev, in wave5_vpu_enc_check_param_valid()
2555 open_param->bit_rate, (int)open_param->frame_rate_info); in wave5_vpu_enc_check_param_valid()
2567 s32 product_id = inst->dev->product; in wave5_vpu_enc_check_open_param()
2568 struct vpu_attr *p_attr = &inst->dev->attr; in wave5_vpu_enc_check_open_param()
2572 return -EINVAL; in wave5_vpu_enc_check_open_param()
2574 param = &open_param->wave_param; in wave5_vpu_enc_check_open_param()
2575 pic_width = open_param->pic_width; in wave5_vpu_enc_check_open_param()
2576 pic_height = open_param->pic_height; in wave5_vpu_enc_check_open_param()
2578 if (inst->id >= MAX_NUM_INSTANCE) { in wave5_vpu_enc_check_open_param()
2579 dev_err(inst->dev->dev, "Too many simultaneous instances: %d (max: %u)\n", in wave5_vpu_enc_check_open_param()
2580 inst->id, MAX_NUM_INSTANCE); in wave5_vpu_enc_check_open_param()
2581 return -EOPNOTSUPP; in wave5_vpu_enc_check_open_param()
2584 if (inst->std != W_HEVC_ENC && in wave5_vpu_enc_check_open_param()
2585 !(inst->std == W_AVC_ENC && product_id == PRODUCT_ID_521)) { in wave5_vpu_enc_check_open_param()
2586 dev_err(inst->dev->dev, "Unsupported encoder-codec & product combination\n"); in wave5_vpu_enc_check_open_param()
2587 return -EOPNOTSUPP; in wave5_vpu_enc_check_open_param()
2590 if (param->internal_bit_depth == 10) { in wave5_vpu_enc_check_open_param()
2591 if (inst->std == W_HEVC_ENC && !p_attr->support_hevc10bit_enc) { in wave5_vpu_enc_check_open_param()
2592 dev_err(inst->dev->dev, in wave5_vpu_enc_check_open_param()
2594 return -EOPNOTSUPP; in wave5_vpu_enc_check_open_param()
2595 } else if (inst->std == W_AVC_ENC && !p_attr->support_avc10bit_enc) { in wave5_vpu_enc_check_open_param()
2596 dev_err(inst->dev->dev, in wave5_vpu_enc_check_open_param()
2598 return -EOPNOTSUPP; in wave5_vpu_enc_check_open_param()
2602 if (!open_param->frame_rate_info) { in wave5_vpu_enc_check_open_param()
2603 dev_err(inst->dev->dev, "No frame rate information.\n"); in wave5_vpu_enc_check_open_param()
2604 return -EINVAL; in wave5_vpu_enc_check_open_param()
2607 if (open_param->bit_rate > MAX_BIT_RATE) { in wave5_vpu_enc_check_open_param()
2608 dev_err(inst->dev->dev, "Invalid encoding bit-rate: %u (valid: 0-%u)\n", in wave5_vpu_enc_check_open_param()
2609 open_param->bit_rate, MAX_BIT_RATE); in wave5_vpu_enc_check_open_param()
2610 return -EINVAL; in wave5_vpu_enc_check_open_param()
2615 dev_err(inst->dev->dev, "Invalid encoding dimension: %ux%u\n", in wave5_vpu_enc_check_open_param()
2617 return -EINVAL; in wave5_vpu_enc_check_open_param()
2620 if (param->profile) { in wave5_vpu_enc_check_open_param()
2621 if (inst->std == W_HEVC_ENC) { in wave5_vpu_enc_check_open_param()
2622 if ((param->profile != HEVC_PROFILE_MAIN || in wave5_vpu_enc_check_open_param()
2623 (param->profile == HEVC_PROFILE_MAIN && in wave5_vpu_enc_check_open_param()
2624 param->internal_bit_depth > 8)) && in wave5_vpu_enc_check_open_param()
2625 (param->profile != HEVC_PROFILE_MAIN10 || in wave5_vpu_enc_check_open_param()
2626 (param->profile == HEVC_PROFILE_MAIN10 && in wave5_vpu_enc_check_open_param()
2627 param->internal_bit_depth < 10)) && in wave5_vpu_enc_check_open_param()
2628 param->profile != HEVC_PROFILE_STILLPICTURE) { in wave5_vpu_enc_check_open_param()
2629 dev_err(inst->dev->dev, in wave5_vpu_enc_check_open_param()
2630 "Invalid HEVC encoding profile: %u (bit-depth: %u)\n", in wave5_vpu_enc_check_open_param()
2631 param->profile, param->internal_bit_depth); in wave5_vpu_enc_check_open_param()
2632 return -EINVAL; in wave5_vpu_enc_check_open_param()
2634 } else if (inst->std == W_AVC_ENC) { in wave5_vpu_enc_check_open_param()
2635 if ((param->internal_bit_depth > 8 && in wave5_vpu_enc_check_open_param()
2636 param->profile != H264_PROFILE_HIGH10)) { in wave5_vpu_enc_check_open_param()
2637 dev_err(inst->dev->dev, in wave5_vpu_enc_check_open_param()
2638 "Invalid AVC encoding profile: %u (bit-depth: %u)\n", in wave5_vpu_enc_check_open_param()
2639 param->profile, param->internal_bit_depth); in wave5_vpu_enc_check_open_param()
2640 return -EINVAL; in wave5_vpu_enc_check_open_param()
2645 if (param->decoding_refresh_type > DEC_REFRESH_TYPE_IDR) { in wave5_vpu_enc_check_open_param()
2646 dev_err(inst->dev->dev, "Invalid decoding refresh type: %u (valid: 0-2)\n", in wave5_vpu_enc_check_open_param()
2647 param->decoding_refresh_type); in wave5_vpu_enc_check_open_param()
2648 return -EINVAL; in wave5_vpu_enc_check_open_param()
2651 if (param->intra_refresh_mode > REFRESH_MODE_CTUS) { in wave5_vpu_enc_check_open_param()
2652 dev_err(inst->dev->dev, "Invalid intra refresh mode: %d (valid: 0-4)\n", in wave5_vpu_enc_check_open_param()
2653 param->intra_refresh_mode); in wave5_vpu_enc_check_open_param()
2654 return -EINVAL; in wave5_vpu_enc_check_open_param()
2657 if (inst->std == W_HEVC_ENC && param->independ_slice_mode && in wave5_vpu_enc_check_open_param()
2658 param->depend_slice_mode > DEPEND_SLICE_MODE_BOOST) { in wave5_vpu_enc_check_open_param()
2659 dev_err(inst->dev->dev, in wave5_vpu_enc_check_open_param()
2661 return -EINVAL; in wave5_vpu_enc_check_open_param()
2664 if (!param->disable_deblk) { in wave5_vpu_enc_check_open_param()
2665 if (param->beta_offset_div2 < -6 || param->beta_offset_div2 > 6) { in wave5_vpu_enc_check_open_param()
2666 dev_err(inst->dev->dev, "Invalid beta offset: %d (valid: -6-6)\n", in wave5_vpu_enc_check_open_param()
2667 param->beta_offset_div2); in wave5_vpu_enc_check_open_param()
2668 return -EINVAL; in wave5_vpu_enc_check_open_param()
2671 if (param->tc_offset_div2 < -6 || param->tc_offset_div2 > 6) { in wave5_vpu_enc_check_open_param()
2672 dev_err(inst->dev->dev, "Invalid tc offset: %d (valid: -6-6)\n", in wave5_vpu_enc_check_open_param()
2673 param->tc_offset_div2); in wave5_vpu_enc_check_open_param()
2674 return -EINVAL; in wave5_vpu_enc_check_open_param()
2678 if (param->intra_qp > MAX_INTRA_QP) { in wave5_vpu_enc_check_open_param()
2679 dev_err(inst->dev->dev, in wave5_vpu_enc_check_open_param()
2680 "Invalid intra quantization parameter: %u (valid: 0-%u)\n", in wave5_vpu_enc_check_open_param()
2681 param->intra_qp, MAX_INTRA_QP); in wave5_vpu_enc_check_open_param()
2682 return -EINVAL; in wave5_vpu_enc_check_open_param()
2685 if (open_param->rc_enable) { in wave5_vpu_enc_check_open_param()
2686 if (param->min_qp_i > MAX_INTRA_QP || param->max_qp_i > MAX_INTRA_QP || in wave5_vpu_enc_check_open_param()
2687 param->min_qp_p > MAX_INTRA_QP || param->max_qp_p > MAX_INTRA_QP || in wave5_vpu_enc_check_open_param()
2688 param->min_qp_b > MAX_INTRA_QP || param->max_qp_b > MAX_INTRA_QP) { in wave5_vpu_enc_check_open_param()
2689 dev_err(inst->dev->dev, in wave5_vpu_enc_check_open_param()
2691 "I: %u-%u, P: %u-%u, B: %u-%u (valid for each: 0-%u)\n", in wave5_vpu_enc_check_open_param()
2692 param->min_qp_i, param->max_qp_i, param->min_qp_p, param->max_qp_p, in wave5_vpu_enc_check_open_param()
2693 param->min_qp_b, param->max_qp_b, MAX_INTRA_QP); in wave5_vpu_enc_check_open_param()
2694 return -EINVAL; in wave5_vpu_enc_check_open_param()
2697 if (param->hvs_qp_enable && param->hvs_max_delta_qp > MAX_HVS_MAX_DELTA_QP) { in wave5_vpu_enc_check_open_param()
2698 dev_err(inst->dev->dev, in wave5_vpu_enc_check_open_param()
2699 "Invalid HVS max delta quantization parameter: %u (valid: 0-%u)\n", in wave5_vpu_enc_check_open_param()
2700 param->hvs_max_delta_qp, MAX_HVS_MAX_DELTA_QP); in wave5_vpu_enc_check_open_param()
2701 return -EINVAL; in wave5_vpu_enc_check_open_param()
2704 if (open_param->vbv_buffer_size < MIN_VBV_BUFFER_SIZE || in wave5_vpu_enc_check_open_param()
2705 open_param->vbv_buffer_size > MAX_VBV_BUFFER_SIZE) { in wave5_vpu_enc_check_open_param()
2706 dev_err(inst->dev->dev, "VBV buffer size: %u (valid: %u-%u)\n", in wave5_vpu_enc_check_open_param()
2707 open_param->vbv_buffer_size, MIN_VBV_BUFFER_SIZE, in wave5_vpu_enc_check_open_param()
2709 return -EINVAL; in wave5_vpu_enc_check_open_param()
2714 return -EINVAL; in wave5_vpu_enc_check_open_param()
2716 if (!wave5_vpu_enc_check_param_valid(inst->dev, open_param)) in wave5_vpu_enc_check_open_param()
2717 return -EINVAL; in wave5_vpu_enc_check_open_param()
2719 if (param->chroma_cb_qp_offset < -12 || param->chroma_cb_qp_offset > 12) { in wave5_vpu_enc_check_open_param()
2720 dev_err(inst->dev->dev, in wave5_vpu_enc_check_open_param()
2721 "Invalid chroma Cb quantization parameter offset: %d (valid: -12-12)\n", in wave5_vpu_enc_check_open_param()
2722 param->chroma_cb_qp_offset); in wave5_vpu_enc_check_open_param()
2723 return -EINVAL; in wave5_vpu_enc_check_open_param()
2726 if (param->chroma_cr_qp_offset < -12 || param->chroma_cr_qp_offset > 12) { in wave5_vpu_enc_check_open_param()
2727 dev_err(inst->dev->dev, in wave5_vpu_enc_check_open_param()
2728 "Invalid chroma Cr quantization parameter offset: %d (valid: -12-12)\n", in wave5_vpu_enc_check_open_param()
2729 param->chroma_cr_qp_offset); in wave5_vpu_enc_check_open_param()
2730 return -EINVAL; in wave5_vpu_enc_check_open_param()
2733 if (param->intra_refresh_mode == REFRESH_MODE_CTU_STEP_SIZE && !param->intra_refresh_arg) { in wave5_vpu_enc_check_open_param()
2734 dev_err(inst->dev->dev, in wave5_vpu_enc_check_open_param()
2735 "Intra refresh mode CTU step-size requires an argument\n"); in wave5_vpu_enc_check_open_param()
2736 return -EINVAL; in wave5_vpu_enc_check_open_param()
2739 if (inst->std == W_HEVC_ENC) { in wave5_vpu_enc_check_open_param()
2740 if (param->nr_intra_weight_y > MAX_INTRA_WEIGHT || in wave5_vpu_enc_check_open_param()
2741 param->nr_intra_weight_cb > MAX_INTRA_WEIGHT || in wave5_vpu_enc_check_open_param()
2742 param->nr_intra_weight_cr > MAX_INTRA_WEIGHT) { in wave5_vpu_enc_check_open_param()
2743 dev_err(inst->dev->dev, in wave5_vpu_enc_check_open_param()
2745 param->nr_intra_weight_y, param->nr_intra_weight_cb, in wave5_vpu_enc_check_open_param()
2746 param->nr_intra_weight_cr, MAX_INTRA_WEIGHT); in wave5_vpu_enc_check_open_param()
2747 return -EINVAL; in wave5_vpu_enc_check_open_param()
2750 if (param->nr_inter_weight_y > MAX_INTER_WEIGHT || in wave5_vpu_enc_check_open_param()
2751 param->nr_inter_weight_cb > MAX_INTER_WEIGHT || in wave5_vpu_enc_check_open_param()
2752 param->nr_inter_weight_cr > MAX_INTER_WEIGHT) { in wave5_vpu_enc_check_open_param()
2753 dev_err(inst->dev->dev, in wave5_vpu_enc_check_open_param()
2755 param->nr_inter_weight_y, param->nr_inter_weight_cb, in wave5_vpu_enc_check_open_param()
2756 param->nr_inter_weight_cr, MAX_INTER_WEIGHT); in wave5_vpu_enc_check_open_param()
2757 return -EINVAL; in wave5_vpu_enc_check_open_param()