Lines Matching +full:per +full:- +full:lane
1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /* Copyright (C) 2023--2024 Intel Corporation */
19 * IRQ0 - CSI_FE event
20 * IRQ1 - CSI_SYNC
21 * IRQ2 - S2M_SIDS0TO7
22 * IRQ3 - S2M_SIDS8TO15
141 * ipu6se support 2 front ends, 2 port per front end, 4 ports 0..3
142 * sip0 - 0, 1
143 * sip1 - 2, 3
169 #define CSI2_SIP_TOP_CSI_RX_DLY_CNT_TERMEN_DLANE(lane) (0xc + (lane) * 8) argument
170 #define CSI2_SIP_TOP_CSI_RX_DLY_CNT_SETTLE_DLANE(lane) (0x10 + (lane) * 8) argument