Lines Matching full:rw
93 #define MO_DMA7_PTR1 0x300018 // {24}RW* DMA Current Ptr : Ch#7
94 #define MO_DMA8_PTR1 0x30001C // {24}RW* DMA Current Ptr : Ch#8
110 #define MO_DMA21_PTR2 0x3000C0 // {24}RW* DMA Tab Ptr : Ch#21
111 #define MO_DMA22_PTR2 0x3000C4 // {24}RW* DMA Tab Ptr : Ch#22
112 #define MO_DMA23_PTR2 0x3000C8 // {24}RW* DMA Tab Ptr : Ch#23
113 #define MO_DMA24_PTR2 0x3000CC // {24}RW* DMA Tab Ptr : Ch#24
114 #define MO_DMA25_PTR2 0x3000D0 // {24}RW* DMA Tab Ptr : Ch#25
115 #define MO_DMA26_PTR2 0x3000D4 // {24}RW* DMA Tab Ptr : Ch#26
116 #define MO_DMA27_PTR2 0x3000D8 // {24}RW* DMA Tab Ptr : Ch#27
117 #define MO_DMA28_PTR2 0x3000DC // {24}RW* DMA Tab Ptr : Ch#28
118 #define MO_DMA29_PTR2 0x3000E0 // {24}RW* DMA Tab Ptr : Ch#29
119 #define MO_DMA30_PTR2 0x3000E4 // {24}RW* DMA Tab Ptr : Ch#30
120 #define MO_DMA31_PTR2 0x3000E8 // {24}RW* DMA Tab Ptr : Ch#31
121 #define MO_DMA32_PTR2 0x3000EC // {24}RW* DMA Tab Ptr : Ch#32
123 #define MO_DMA21_CNT1 0x300100 // {11}RW* DMA Buffer Size : Ch#21
124 #define MO_DMA22_CNT1 0x300104 // {11}RW* DMA Buffer Size : Ch#22
125 #define MO_DMA23_CNT1 0x300108 // {11}RW* DMA Buffer Size : Ch#23
126 #define MO_DMA24_CNT1 0x30010C // {11}RW* DMA Buffer Size : Ch#24
127 #define MO_DMA25_CNT1 0x300110 // {11}RW* DMA Buffer Size : Ch#25
128 #define MO_DMA26_CNT1 0x300114 // {11}RW* DMA Buffer Size : Ch#26
129 #define MO_DMA27_CNT1 0x300118 // {11}RW* DMA Buffer Size : Ch#27
130 #define MO_DMA28_CNT1 0x30011C // {11}RW* DMA Buffer Size : Ch#28
131 #define MO_DMA29_CNT1 0x300120 // {11}RW* DMA Buffer Size : Ch#29
132 #define MO_DMA30_CNT1 0x300124 // {11}RW* DMA Buffer Size : Ch#30
133 #define MO_DMA31_CNT1 0x300128 // {11}RW* DMA Buffer Size : Ch#31
134 #define MO_DMA32_CNT1 0x30012C // {11}RW* DMA Buffer Size : Ch#32
136 #define MO_DMA21_CNT2 0x300140 // {11}RW* DMA Table Size : Ch#21
137 #define MO_DMA22_CNT2 0x300144 // {11}RW* DMA Table Size : Ch#22
138 #define MO_DMA23_CNT2 0x300148 // {11}RW* DMA Table Size : Ch#23
139 #define MO_DMA24_CNT2 0x30014C // {11}RW* DMA Table Size : Ch#24
140 #define MO_DMA25_CNT2 0x300150 // {11}RW* DMA Table Size : Ch#25
141 #define MO_DMA26_CNT2 0x300154 // {11}RW* DMA Table Size : Ch#26
142 #define MO_DMA27_CNT2 0x300158 // {11}RW* DMA Table Size : Ch#27
143 #define MO_DMA28_CNT2 0x30015C // {11}RW* DMA Table Size : Ch#28
144 #define MO_DMA29_CNT2 0x300160 // {11}RW* DMA Table Size : Ch#29
145 #define MO_DMA30_CNT2 0x300164 // {11}RW* DMA Table Size : Ch#30
146 #define MO_DMA31_CNT2 0x300168 // {11}RW* DMA Table Size : Ch#31
147 #define MO_DMA32_CNT2 0x30016C // {11}RW* DMA Table Size : Ch#32
206 #define MO_VID_DMACNTRL 0x31C040 // {8}RW Video DMA control
222 #define MO_AUD_DMACNTRL 0x32C040 // {6}RW Audio DMA control
224 #define MO_AUDD_LNGTH 0x32C048 // {12}RW Audio down line length
225 #define MO_AUDR_LNGTH 0x32C04C // {12}RW Audio RDS line length
436 #define MO_TS_DMACNTRL 0x33C040 // {6}RW TS DMA control
438 #define MO_TS_LNGTH 0x33C048 // {12}RW TS line length
457 #define MO_VIP_DMACNTRL 0x34C040 // {6}RW VIP DMA control
472 #define MO_GP0_IO 0x350010 // {32}RW* GPIOoutput enablesdata I/O
473 #define MO_GP1_IO 0x350014 // {32}RW* GPIOoutput enablesdata I/O
474 #define MO_GP2_IO 0x350018 // {32}RW* GPIOoutput enablesdata I/O
475 #define MO_GP3_IO 0x35001C // {32}RW* GPIO Mode/Ctrloutput enables
476 #define MO_GPIO 0x350020 // {32}RW* GPIO I2C Ctrldata I/O
477 #define MO_GPOE 0x350024 // {32}RW GPIO I2C Ctrloutput enables
480 #define MO_PLL_B 0x35C008 // {32}RW* PLL Control for ASB bus clks
481 #define MO_M2M_CNT 0x35C024 // {32}RW Mem2Mem DMA Cnt
483 #define MO_CRC 0x35C02C // {16}RW CRC16 init/result
487 #define MO_TM_LMT_LDW 0x35C03C // {32}RW Timer : Limit low dword
488 #define MO_TM_LMT_UW 0x35C040 // {32}RW Timer : Limit high word
489 #define MO_PINMUX_IO 0x35C044 // {8}RW Pin Mux Control
490 #define MO_TSTSEL_IO 0x35C048 // {2}RW Pin Mux Control