Lines Matching full:sw1
23 static void epu_cmd(struct cx18 *cx, u32 sw1) in epu_cmd() argument
25 if (sw1 & IRQ_CPU_TO_EPU) in epu_cmd()
27 if (sw1 & IRQ_APU_TO_EPU) in epu_cmd()
34 u32 sw1, sw2, hw2; in cx18_irq_handler() local
36 sw1 = cx18_read_reg(cx, SW1_INT_STATUS) & cx->sw1_irq_mask; in cx18_irq_handler()
40 if (sw1) in cx18_irq_handler()
41 cx18_write_reg_expect(cx, sw1, SW1_INT_STATUS, ~sw1, sw1); in cx18_irq_handler()
47 if (sw1 || sw2 || hw2) in cx18_irq_handler()
48 CX18_DEBUG_HI_IRQ("received interrupts SW1: %x SW2: %x HW2: %x\n", in cx18_irq_handler()
49 sw1, sw2, hw2); in cx18_irq_handler()
52 * SW1 responses have to happen first. The sending XPU times out the in cx18_irq_handler()
55 if (sw1) in cx18_irq_handler()
56 epu_cmd(cx, sw1); in cx18_irq_handler()
66 return (sw1 || sw2 || hw2) ? IRQ_HANDLED : IRQ_NONE; in cx18_irq_handler()