26 #define OV2740_REG_CHIP_ID		0x300a
27 #define OV2740_CHIP_ID			0x2740
29 #define OV2740_REG_MODE_SELECT		0x0100
30 #define OV2740_MODE_STANDBY		0x00
31 #define OV2740_MODE_STREAMING		0x01
34 #define OV2740_REG_VTS			0x380e
37 #define OV2740_REG_HTS			0x380c
40 #define OV2740_REG_EXPOSURE		0x3500
46 #define OV2740_REG_ANALOG_GAIN		0x3508
52 #define OV2740_REG_MWB_R_GAIN		0x500a
53 #define OV2740_REG_MWB_G_GAIN		0x500c
54 #define OV2740_REG_MWB_B_GAIN		0x500e
61 #define OV2740_REG_TEST_PATTERN		0x5040
66 #define OV2740_REG_GROUP_ACCESS		0x3208
67 #define OV2740_GROUP_HOLD_START		0x0
68 #define OV2740_GROUP_HOLD_END		0x10
69 #define OV2740_GROUP_HOLD_LAUNCH	0xa0
72 #define OV2740_REG_ISP_CTRL00		0x5000
74 #define OV2740_REG_ISP_CTRL01		0x5001
75 /* Customer Addresses: 0x7010 - 0x710F */
76 #define CUSTOMER_USE_OTP_SIZE		0x100
78 #define OV2740_REG_OTP_CUSTOMER		0x7010
140 	{0x0302, 0x4b},
141 	{0x030d, 0x4b},
142 	{0x030e, 0x02},
143 	{0x030a, 0x01},
144 	{0x0312, 0x11},
148 	{0x0302, 0x4b},
149 	{0x0303, 0x01},
150 	{0x030d, 0x4b},
151 	{0x030e, 0x02},
152 	{0x030a, 0x01},
153 	{0x0312, 0x11},
154 	{0x4837, 0x2c},
158 	{0x3000, 0x00},
159 	{0x3018, 0x32},
160 	{0x3031, 0x0a},
161 	{0x3080, 0x08},
162 	{0x3083, 0xB4},
163 	{0x3103, 0x00},
164 	{0x3104, 0x01},
165 	{0x3106, 0x01},
166 	{0x3500, 0x00},
167 	{0x3501, 0x44},
168 	{0x3502, 0x40},
169 	{0x3503, 0x88},
170 	{0x3507, 0x00},
171 	{0x3508, 0x00},
172 	{0x3509, 0x80},
173 	{0x350c, 0x00},
174 	{0x350d, 0x80},
175 	{0x3510, 0x00},
176 	{0x3511, 0x00},
177 	{0x3512, 0x20},
178 	{0x3632, 0x00},
179 	{0x3633, 0x10},
180 	{0x3634, 0x10},
181 	{0x3635, 0x10},
182 	{0x3645, 0x13},
183 	{0x3646, 0x81},
184 	{0x3636, 0x10},
185 	{0x3651, 0x0a},
186 	{0x3656, 0x02},
187 	{0x3659, 0x04},
188 	{0x365a, 0xda},
189 	{0x365b, 0xa2},
190 	{0x365c, 0x04},
191 	{0x365d, 0x1d},
192 	{0x365e, 0x1a},
193 	{0x3662, 0xd7},
194 	{0x3667, 0x78},
195 	{0x3669, 0x0a},
196 	{0x366a, 0x92},
197 	{0x3700, 0x54},
198 	{0x3702, 0x10},
199 	{0x3706, 0x42},
200 	{0x3709, 0x30},
201 	{0x370b, 0xc2},
202 	{0x3714, 0x63},
203 	{0x3715, 0x01},
204 	{0x3716, 0x00},
205 	{0x371a, 0x3e},
206 	{0x3732, 0x0e},
207 	{0x3733, 0x10},
208 	{0x375f, 0x0e},
209 	{0x3768, 0x30},
210 	{0x3769, 0x44},
211 	{0x376a, 0x22},
212 	{0x377b, 0x20},
213 	{0x377c, 0x00},
214 	{0x377d, 0x0c},
215 	{0x3798, 0x00},
216 	{0x37a1, 0x55},
217 	{0x37a8, 0x6d},
218 	{0x37c2, 0x04},
219 	{0x37c5, 0x00},
220 	{0x37c8, 0x00},
221 	{0x3800, 0x00},
222 	{0x3801, 0x00},
223 	{0x3802, 0x00},
224 	{0x3803, 0x00},
225 	{0x3804, 0x07},
226 	{0x3805, 0x8f},
227 	{0x3806, 0x04},
228 	{0x3807, 0x47},
229 	{0x3808, 0x07},
230 	{0x3809, 0x88},
231 	{0x380a, 0x04},
232 	{0x380b, 0x40},
233 	{0x380c, 0x04},
234 	{0x380d, 0x38},
235 	{0x380e, 0x04},
236 	{0x380f, 0x60},
237 	{0x3810, 0x00},
238 	{0x3811, 0x04},
239 	{0x3812, 0x00},
240 	{0x3813, 0x04},
241 	{0x3814, 0x01},
242 	{0x3815, 0x01},
243 	{0x3820, 0x80},
244 	{0x3821, 0x46},
245 	{0x3822, 0x84},
246 	{0x3829, 0x00},
247 	{0x382a, 0x01},
248 	{0x382b, 0x01},
249 	{0x3830, 0x04},
250 	{0x3836, 0x01},
251 	{0x3837, 0x08},
252 	{0x3839, 0x01},
253 	{0x383a, 0x00},
254 	{0x383b, 0x08},
255 	{0x383c, 0x00},
256 	{0x3f0b, 0x00},
257 	{0x4001, 0x20},
258 	{0x4009, 0x07},
259 	{0x4003, 0x10},
260 	{0x4010, 0xe0},
261 	{0x4016, 0x00},
262 	{0x4017, 0x10},
263 	{0x4044, 0x02},
264 	{0x4304, 0x08},
265 	{0x4307, 0x30},
266 	{0x4320, 0x80},
267 	{0x4322, 0x00},
268 	{0x4323, 0x00},
269 	{0x4324, 0x00},
270 	{0x4325, 0x00},
271 	{0x4326, 0x00},
272 	{0x4327, 0x00},
273 	{0x4328, 0x00},
274 	{0x4329, 0x00},
275 	{0x432c, 0x03},
276 	{0x432d, 0x81},
277 	{0x4501, 0x84},
278 	{0x4502, 0x40},
279 	{0x4503, 0x18},
280 	{0x4504, 0x04},
281 	{0x4508, 0x02},
282 	{0x4601, 0x10},
283 	{0x4800, 0x00},
284 	{0x4816, 0x52},
285 	{0x4837, 0x16},
286 	{0x5000, 0x7f},
287 	{0x5001, 0x00},
288 	{0x5005, 0x38},
289 	{0x501e, 0x0d},
290 	{0x5040, 0x00},
291 	{0x5901, 0x00},
292 	{0x3800, 0x00},
293 	{0x3801, 0x00},
294 	{0x3802, 0x00},
295 	{0x3803, 0x00},
296 	{0x3804, 0x07},
297 	{0x3805, 0x8f},
298 	{0x3806, 0x04},
299 	{0x3807, 0x47},
300 	{0x3808, 0x07},
301 	{0x3809, 0x8c},
302 	{0x380a, 0x04},
303 	{0x380b, 0x44},
304 	{0x3810, 0x00},
305 	{0x3811, 0x00},
306 	{0x3812, 0x00},
307 	{0x3813, 0x01},
311 	{0x3000, 0x00},
312 	{0x3018, 0x32},	/* 0x32 for 2 lanes, 0x12 for 1 lane */
313 	{0x3031, 0x0a},
314 	{0x3080, 0x08},
315 	{0x3083, 0xB4},
316 	{0x3103, 0x00},
317 	{0x3104, 0x01},
318 	{0x3106, 0x01},
319 	{0x3500, 0x00},
320 	{0x3501, 0x44},
321 	{0x3502, 0x40},
322 	{0x3503, 0x88},
323 	{0x3507, 0x00},
324 	{0x3508, 0x00},
325 	{0x3509, 0x80},
326 	{0x350c, 0x00},
327 	{0x350d, 0x80},
328 	{0x3510, 0x00},
329 	{0x3511, 0x00},
330 	{0x3512, 0x20},
331 	{0x3632, 0x00},
332 	{0x3633, 0x10},
333 	{0x3634, 0x10},
334 	{0x3635, 0x10},
335 	{0x3645, 0x13},
336 	{0x3646, 0x81},
337 	{0x3636, 0x10},
338 	{0x3651, 0x0a},
339 	{0x3656, 0x02},
340 	{0x3659, 0x04},
341 	{0x365a, 0xda},
342 	{0x365b, 0xa2},
343 	{0x365c, 0x04},
344 	{0x365d, 0x1d},
345 	{0x365e, 0x1a},
346 	{0x3662, 0xd7},
347 	{0x3667, 0x78},
348 	{0x3669, 0x0a},
349 	{0x366a, 0x92},
350 	{0x3700, 0x54},
351 	{0x3702, 0x10},
352 	{0x3706, 0x42},
353 	{0x3709, 0x30},
354 	{0x370b, 0xc2},
355 	{0x3714, 0x63},
356 	{0x3715, 0x01},
357 	{0x3716, 0x00},
358 	{0x371a, 0x3e},
359 	{0x3732, 0x0e},
360 	{0x3733, 0x10},
361 	{0x375f, 0x0e},
362 	{0x3768, 0x30},
363 	{0x3769, 0x44},
364 	{0x376a, 0x22},
365 	{0x377b, 0x20},
366 	{0x377c, 0x00},
367 	{0x377d, 0x0c},
368 	{0x3798, 0x00},
369 	{0x37a1, 0x55},
370 	{0x37a8, 0x6d},
371 	{0x37c2, 0x04},
372 	{0x37c5, 0x00},
373 	{0x37c8, 0x00},
374 	{0x3800, 0x00},
375 	{0x3801, 0x00},
376 	{0x3802, 0x00},
377 	{0x3803, 0x00},
378 	{0x3804, 0x07},
379 	{0x3805, 0x8f},
380 	{0x3806, 0x04},
381 	{0x3807, 0x47},
382 	{0x3808, 0x07},
383 	{0x3809, 0x88},
384 	{0x380a, 0x04},
385 	{0x380b, 0x40},
386 	{0x380c, 0x08},
387 	{0x380d, 0x70},
388 	{0x380e, 0x04},
389 	{0x380f, 0x56},
390 	{0x3810, 0x00},
391 	{0x3811, 0x04},
392 	{0x3812, 0x00},
393 	{0x3813, 0x04},
394 	{0x3814, 0x01},
395 	{0x3815, 0x01},
396 	{0x3820, 0x80},
397 	{0x3821, 0x46},
398 	{0x3822, 0x84},
399 	{0x3829, 0x00},
400 	{0x382a, 0x01},
401 	{0x382b, 0x01},
402 	{0x3830, 0x04},
403 	{0x3836, 0x01},
404 	{0x3837, 0x08},
405 	{0x3839, 0x01},
406 	{0x383a, 0x00},
407 	{0x383b, 0x08},
408 	{0x383c, 0x00},
409 	{0x3f0b, 0x00},
410 	{0x4001, 0x20},
411 	{0x4009, 0x07},
412 	{0x4003, 0x10},
413 	{0x4010, 0xe0},
414 	{0x4016, 0x00},
415 	{0x4017, 0x10},
416 	{0x4044, 0x02},
417 	{0x4304, 0x08},
418 	{0x4307, 0x30},
419 	{0x4320, 0x80},
420 	{0x4322, 0x00},
421 	{0x4323, 0x00},
422 	{0x4324, 0x00},
423 	{0x4325, 0x00},
424 	{0x4326, 0x00},
425 	{0x4327, 0x00},
426 	{0x4328, 0x00},
427 	{0x4329, 0x00},
428 	{0x432c, 0x03},
429 	{0x432d, 0x81},
430 	{0x4501, 0x84},
431 	{0x4502, 0x40},
432 	{0x4503, 0x18},
433 	{0x4504, 0x04},
434 	{0x4508, 0x02},
435 	{0x4601, 0x10},
436 	{0x4800, 0x00},
437 	{0x4816, 0x52},
438 	{0x5000, 0x73},	/* 0x7f enable DPC */
439 	{0x5001, 0x00},
440 	{0x5005, 0x38},
441 	{0x501e, 0x0d},
442 	{0x5040, 0x00},
443 	{0x5901, 0x00},
444 	{0x3800, 0x00},
445 	{0x3801, 0x00},
446 	{0x3802, 0x00},
447 	{0x3803, 0x00},
448 	{0x3804, 0x07},
449 	{0x3805, 0x8f},
450 	{0x3806, 0x04},
451 	{0x3807, 0x47},
452 	{0x3808, 0x07},
453 	{0x3809, 0x8c},
454 	{0x380a, 0x04},
455 	{0x380b, 0x44},
456 	{0x3810, 0x00},
457 	{0x3811, 0x00},
458 	{0x3812, 0x00},
459 	{0x3813, 0x01},
460 	{0x4003, 0x40},	/* set Black level to 0x40 */
574 	u8 data_buf[4] = {0};  in ov2740_read_reg()
581 	msgs[0].addr = client->addr;  in ov2740_read_reg()
582 	msgs[0].flags = 0;  in ov2740_read_reg()
583 	msgs[0].len = sizeof(addr_buf);  in ov2740_read_reg()
584 	msgs[0].buf = addr_buf;  in ov2740_read_reg()
592 		return ret < 0 ? ret : -EIO;  in ov2740_read_reg()
596 	return 0;  in ov2740_read_reg()
613 		return ret < 0 ? ret : -EIO;  in ov2740_write_reg()
615 	return 0;  in ov2740_write_reg()
625 	for (i = 0; i < r_list->num_of_regs; i++) {  in ov2740_write_reg_list()
630 					    "write reg 0x%4.4x return err = %d\n",  in ov2740_write_reg_list()
636 	return 0;  in ov2740_write_reg_list()
646 		return 0;  in ov2740_identify_module()
662 	return 0;  in ov2740_identify_module()
726 		return 0;  in ov2740_set_ctrl()
796 					       V4L2_CID_PIXEL_RATE, 0,  in ov2740_init_controls()
828 				     0, 0, ov2740_test_pattern_menu);  in ov2740_init_controls()
843 	return 0;  in ov2740_init_controls()
859 	u32 isp_ctrl00 = 0;  in ov2740_load_otp_data()
860 	u32 isp_ctrl01 = 0;  in ov2740_load_otp_data()
864 		return 0;  in ov2740_load_otp_data()
907 	 * during the 20 ms period after streaming starts (0x100 = 0x01).  in ov2740_load_otp_data()
937 	return 0;  in ov2740_load_otp_data()
960 	ret = ov2740_write_reg(ov2740, 0x0103, 1, 0x01);  in ov2740_start_streaming()
1009 	int ret = 0;  in ov2740_set_stream()
1015 		if (ret < 0)  in ov2740_set_stream()
1020 			enable = 0;  in ov2740_set_stream()
1052 		return 0;  in ov2740_set_format()
1068 	return 0;  in ov2740_set_format()
1075 	if (code->index > 0)  in ov2740_enum_mbus_code()
1080 	return 0;  in ov2740_enum_mbus_code()
1101 	return 0;  in ov2740_enum_frame_size()
1109 	ov2740_update_pad_format(&ov2740->supported_modes[0],  in ov2740_init_state()
1110 				 v4l2_subdev_state_get_format(sd_state, 0));  in ov2740_init_state()
1111 	return 0;  in ov2740_init_state()
1191 	for (i = 0; i < ARRAY_SIZE(link_freq_menu_items); i++) {  in ov2740_check_hwcfg()
1192 		for (j = 0; j < bus_cfg.nr_of_link_frequencies; j++) {  in ov2740_check_hwcfg()
1245 	int ret = 0;  in ov2740_nvmem_read()
1256 	if (ret < 0) {  in ov2740_nvmem_read()
1311 	return 0;  in ov2740_register_nvmem()
1323 	return 0;  in ov2740_suspend()
1342 	gpiod_set_value_cansleep(ov2740->powerdown_gpio, 0);  in ov2740_resume()
1343 	gpiod_set_value_cansleep(ov2740->reset_gpio, 0);  in ov2740_resume()
1346 	return 0;  in ov2740_resume()
1392 	for (i = 0; i < OV2740_NUM_SUPPLIES; i++)  in ov2740_probe()
1413 	ov2740->cur_mode = &ov2740->supported_modes[0];  in ov2740_probe()
1442 	if (ret < 0) {  in ov2740_probe()
1451 	return 0;  in ov2740_probe()