22 #define IMX335_REG_MODE_SELECT		CCI_REG8(0x3000)
23 #define IMX335_MODE_STANDBY		0x01
24 #define IMX335_MODE_STREAMING		0x00
27 #define IMX335_REG_HOLD			CCI_REG8(0x3001)
29 #define IMX335_REG_MASTER_MODE		CCI_REG8(0x3002)
30 #define IMX335_REG_BCWAIT_TIME		CCI_REG8(0x300c)
31 #define IMX335_REG_CPWAIT_TIME		CCI_REG8(0x300d)
32 #define IMX335_REG_WINMODE		CCI_REG8(0x3018)
33 #define IMX335_REG_HTRIMMING_START	CCI_REG16_LE(0x302c)
34 #define IMX335_REG_HNUM			CCI_REG8(0x302e)
37 #define IMX335_REG_VMAX			CCI_REG24_LE(0x3030)
39 #define IMX335_REG_OPB_SIZE_V		CCI_REG8(0x304c)
40 #define IMX335_REG_ADBIT		CCI_REG8(0x3050)
41 #define IMX335_REG_Y_OUT_SIZE		CCI_REG16_LE(0x3056)
43 #define IMX335_REG_SHUTTER		CCI_REG24_LE(0x3058)
47 #define IMX335_EXPOSURE_DEFAULT		0x0648
49 #define IMX335_REG_AREA3_ST_ADR_1	CCI_REG16_LE(0x3074)
50 #define IMX335_REG_AREA3_WIDTH_1	CCI_REG16_LE(0x3076)
53 #define IMX335_REG_GAIN			CCI_REG8(0x30e8)
54 #define IMX335_AGAIN_MIN		0
57 #define IMX335_AGAIN_DEFAULT		0
59 #define IMX335_REG_TPG_TESTCLKEN	CCI_REG8(0x3148)
61 #define IMX335_REG_INCLKSEL1		CCI_REG16_LE(0x314c)
62 #define IMX335_REG_INCLKSEL2		CCI_REG8(0x315a)
63 #define IMX335_REG_INCLKSEL3		CCI_REG8(0x3168)
64 #define IMX335_REG_INCLKSEL4		CCI_REG8(0x316a)
66 #define IMX335_REG_MDBIT		CCI_REG8(0x319d)
67 #define IMX335_REG_SYSMODE		CCI_REG8(0x319e)
69 #define IMX335_REG_XVS_XHS_DRV		CCI_REG8(0x31a1)
72 #define IMX335_REG_TPG_DIG_CLP_MODE	CCI_REG8(0x3280)
73 #define IMX335_REG_TPG_EN_DUOUT		CCI_REG8(0x329c)
74 #define IMX335_REG_TPG			CCI_REG8(0x329e)
75 #define IMX335_TPG_ALL_000		0
87 #define IMX335_REG_TPG_COLORWIDTH	CCI_REG8(0x32a0)
89 #define IMX335_REG_BLKLEVEL		CCI_REG16_LE(0x3302)
91 #define IMX335_REG_WRJ_OPEN		CCI_REG8(0x336c)
93 #define IMX335_REG_ADBIT1		CCI_REG16_LE(0x341c)
96 #define IMX335_REG_ID			CCI_REG8(0x3912)
97 #define IMX335_ID			0x00
100 #define IMX335_REG_LANEMODE		CCI_REG8(0x3a01)
104 #define IMX335_REG_TCLKPOST		CCI_REG16_LE(0x3a18)
105 #define IMX335_REG_TCLKPREPARE		CCI_REG16_LE(0x3a1a)
106 #define IMX335_REG_TCLK_TRAIL		CCI_REG16_LE(0x3a1c)
107 #define IMX335_REG_TCLK_ZERO		CCI_REG16_LE(0x3a1e)
108 #define IMX335_REG_THS_PREPARE		CCI_REG16_LE(0x3a20)
109 #define IMX335_REG_THS_ZERO		CCI_REG16_LE(0x3a22)
110 #define IMX335_REG_THS_TRAIL		CCI_REG16_LE(0x3a24)
111 #define IMX335_REG_THS_EXIT		CCI_REG16_LE(0x3a26)
112 #define IMX335_REG_TPLX			CCI_REG16_LE(0x3a28)
257 	{ IMX335_REG_MASTER_MODE, 0x00 },
258 	{ IMX335_REG_WINMODE, 0x04 },
264 	{ IMX335_REG_OPB_SIZE_V, 0 },
265 	{ IMX335_REG_XVS_XHS_DRV, 0x00 },
266 	{ CCI_REG8(0x3288), 0x21 },
267 	{ CCI_REG8(0x328a), 0x02 },
268 	{ CCI_REG8(0x3414), 0x05 },
269 	{ CCI_REG8(0x3416), 0x18 },
270 	{ CCI_REG8(0x3648), 0x01 },
271 	{ CCI_REG8(0x364a), 0x04 },
272 	{ CCI_REG8(0x364c), 0x04 },
273 	{ CCI_REG8(0x3678), 0x01 },
274 	{ CCI_REG8(0x367c), 0x31 },
275 	{ CCI_REG8(0x367e), 0x31 },
276 	{ CCI_REG8(0x3706), 0x10 },
277 	{ CCI_REG8(0x3708), 0x03 },
278 	{ CCI_REG8(0x3714), 0x02 },
279 	{ CCI_REG8(0x3715), 0x02 },
280 	{ CCI_REG8(0x3716), 0x01 },
281 	{ CCI_REG8(0x3717), 0x03 },
282 	{ CCI_REG8(0x371c), 0x3d },
283 	{ CCI_REG8(0x371d), 0x3f },
284 	{ CCI_REG8(0x372c), 0x00 },
285 	{ CCI_REG8(0x372d), 0x00 },
286 	{ CCI_REG8(0x372e), 0x46 },
287 	{ CCI_REG8(0x372f), 0x00 },
288 	{ CCI_REG8(0x3730), 0x89 },
289 	{ CCI_REG8(0x3731), 0x00 },
290 	{ CCI_REG8(0x3732), 0x08 },
291 	{ CCI_REG8(0x3733), 0x01 },
292 	{ CCI_REG8(0x3734), 0xfe },
293 	{ CCI_REG8(0x3735), 0x05 },
294 	{ CCI_REG8(0x3740), 0x02 },
295 	{ CCI_REG8(0x375d), 0x00 },
296 	{ CCI_REG8(0x375e), 0x00 },
297 	{ CCI_REG8(0x375f), 0x11 },
298 	{ CCI_REG8(0x3760), 0x01 },
299 	{ CCI_REG8(0x3768), 0x1b },
300 	{ CCI_REG8(0x3769), 0x1b },
301 	{ CCI_REG8(0x376a), 0x1b },
302 	{ CCI_REG8(0x376b), 0x1b },
303 	{ CCI_REG8(0x376c), 0x1a },
304 	{ CCI_REG8(0x376d), 0x17 },
305 	{ CCI_REG8(0x376e), 0x0f },
306 	{ CCI_REG8(0x3776), 0x00 },
307 	{ CCI_REG8(0x3777), 0x00 },
308 	{ CCI_REG8(0x3778), 0x46 },
309 	{ CCI_REG8(0x3779), 0x00 },
310 	{ CCI_REG8(0x377a), 0x89 },
311 	{ CCI_REG8(0x377b), 0x00 },
312 	{ CCI_REG8(0x377c), 0x08 },
313 	{ CCI_REG8(0x377d), 0x01 },
314 	{ CCI_REG8(0x377e), 0x23 },
315 	{ CCI_REG8(0x377f), 0x02 },
316 	{ CCI_REG8(0x3780), 0xd9 },
317 	{ CCI_REG8(0x3781), 0x03 },
318 	{ CCI_REG8(0x3782), 0xf5 },
319 	{ CCI_REG8(0x3783), 0x06 },
320 	{ CCI_REG8(0x3784), 0xa5 },
321 	{ CCI_REG8(0x3788), 0x0f },
322 	{ CCI_REG8(0x378a), 0xd9 },
323 	{ CCI_REG8(0x378b), 0x03 },
324 	{ CCI_REG8(0x378c), 0xeb },
325 	{ CCI_REG8(0x378d), 0x05 },
326 	{ CCI_REG8(0x378e), 0x87 },
327 	{ CCI_REG8(0x378f), 0x06 },
328 	{ CCI_REG8(0x3790), 0xf5 },
329 	{ CCI_REG8(0x3792), 0x43 },
330 	{ CCI_REG8(0x3794), 0x7a },
331 	{ CCI_REG8(0x3796), 0xa1 },
332 	{ CCI_REG8(0x37b0), 0x36 },
333 	{ CCI_REG8(0x3a00), 0x00 },
337 	{ IMX335_REG_ADBIT, 0x00 },
338 	{ IMX335_REG_MDBIT, 0x00 },
339 	{ IMX335_REG_ADBIT1, 0x1ff },
343 	{ IMX335_REG_ADBIT, 0x01 },
344 	{ IMX335_REG_MDBIT, 0x01 },
345 	{ IMX335_REG_ADBIT1, 0x47 },
349 	{ IMX335_REG_BCWAIT_TIME, 0x3b },
350 	{ IMX335_REG_CPWAIT_TIME, 0x2a },
351 	{ IMX335_REG_INCLKSEL1, 0x00c6 },
352 	{ IMX335_REG_INCLKSEL2, 0x02 },
353 	{ IMX335_REG_INCLKSEL3, 0xa0 },
354 	{ IMX335_REG_INCLKSEL4, 0x7e },
355 	{ IMX335_REG_SYSMODE, 0x01 },
356 	{ IMX335_REG_TCLKPOST, 0x8f },
357 	{ IMX335_REG_TCLKPREPARE, 0x4f },
358 	{ IMX335_REG_TCLK_TRAIL, 0x47 },
359 	{ IMX335_REG_TCLK_ZERO, 0x0137 },
360 	{ IMX335_REG_THS_PREPARE, 0x4f },
361 	{ IMX335_REG_THS_ZERO,  0x87 },
362 	{ IMX335_REG_THS_TRAIL, 0x4f },
363 	{ IMX335_REG_THS_EXIT, 0x7f },
364 	{ IMX335_REG_TPLX, 0x3f },
368 	{ IMX335_REG_BCWAIT_TIME, 0x3b },
369 	{ IMX335_REG_CPWAIT_TIME, 0x2a },
370 	{ IMX335_REG_INCLKSEL1, 0x0129 },
371 	{ IMX335_REG_INCLKSEL2, 0x06 },
372 	{ IMX335_REG_INCLKSEL3, 0xa0 },
373 	{ IMX335_REG_INCLKSEL4, 0x7e },
374 	{ IMX335_REG_SYSMODE, 0x02 },
375 	{ IMX335_REG_TCLKPOST, 0x7f },
376 	{ IMX335_REG_TCLKPREPARE, 0x37 },
377 	{ IMX335_REG_TCLK_TRAIL, 0x37 },
378 	{ IMX335_REG_TCLK_ZERO, 0xf7 },
379 	{ IMX335_REG_THS_PREPARE, 0x3f },
380 	{ IMX335_REG_THS_ZERO, 0x6f },
381 	{ IMX335_REG_THS_TRAIL, 0x3f },
382 	{ IMX335_REG_THS_EXIT, 0x5f },
383 	{ IMX335_REG_TPLX, 0x2f },
440  * Return: 0 if successful, error code otherwise.
466  * Return: 0 if successful, error code otherwise.
472 	int ret = 0;  in imx335_update_exp_gain()
488 	ret_hold = cci_write(imx335->cci, IMX335_REG_HOLD, 0, NULL);  in imx335_update_exp_gain()
497 	int ret = 0;  in imx335_update_test_pattern()
504 			{ IMX335_REG_TPG_TESTCLKEN, 0x10 },  in imx335_update_test_pattern()
505 			{ IMX335_REG_TPG_DIG_CLP_MODE, 0x00 },  in imx335_update_test_pattern()
506 			{ IMX335_REG_TPG_EN_DUOUT, 0x01 },  in imx335_update_test_pattern()
507 			{ IMX335_REG_TPG_COLORWIDTH, 0x11 },  in imx335_update_test_pattern()
508 			{ IMX335_REG_BLKLEVEL, 0x00 },  in imx335_update_test_pattern()
509 			{ IMX335_REG_WRJ_OPEN, 0x00 },  in imx335_update_test_pattern()
519 			{ IMX335_REG_TPG_TESTCLKEN, 0x00 },  in imx335_update_test_pattern()
520 			{ IMX335_REG_TPG_DIG_CLP_MODE, 0x01 },  in imx335_update_test_pattern()
521 			{ IMX335_REG_TPG_EN_DUOUT, 0x00 },  in imx335_update_test_pattern()
522 			{ IMX335_REG_TPG_COLORWIDTH, 0x10 },  in imx335_update_test_pattern()
523 			{ IMX335_REG_BLKLEVEL, 0x32 },  in imx335_update_test_pattern()
524 			{ IMX335_REG_WRJ_OPEN, 0x01 },  in imx335_update_test_pattern()
544  * Return: 0 if successful, error code otherwise.
574 	if (pm_runtime_get_if_in_use(imx335->dev) == 0)  in imx335_set_ctrl()
575 		return 0;  in imx335_set_ctrl()
611 	for (i = 0; i < ARRAY_SIZE(imx335_mbus_codes); i++) {  in imx335_get_format_code()
616 	return imx335_mbus_codes[0];  in imx335_get_format_code()
625  * Return: 0 if successful, error code otherwise.
636 	return 0;  in imx335_enum_mbus_code()
645  * Return: 0 if successful, error code otherwise.
666 	return 0;  in imx335_enum_frame_size()
696  * Return: 0 if successful, error code otherwise.
717 	return 0;  in imx335_get_pad_format()
726  * Return: 0 if successful, error code otherwise.
734 	int i, ret = 0;  in imx335_set_pad_format()
739 	for (i = 0; i < ARRAY_SIZE(imx335_mbus_codes); i++) {  in imx335_set_pad_format()
767  * Return: 0 if successful, error code otherwise.
773 	struct v4l2_subdev_format fmt = { 0 };  in imx335_init_state()
779 	__v4l2_ctrl_modify_range(imx335->link_freq_ctrl, 0,  in imx335_init_state()
794  * Return: 0 if successful, error code otherwise.
802 		sel->r.top = 0;  in imx335_get_selection()
803 		sel->r.left = 0;  in imx335_get_selection()
807 		return 0;  in imx335_get_selection()
817 		return 0;  in imx335_get_selection()
844  * Return: 0 if successful, error code otherwise.
900 	return 0;  in imx335_start_streaming()
907  * Return: 0 if successful, error code otherwise.
920  * Return: 0 if successful, error code otherwise.
944 	return 0;  in imx335_set_stream()
958  * Return: 0 if successful, -EIO if sensor id does not match
975 	return 0;  in imx335_detect()
982  * Return: 0 if successful, error code otherwise.
1007 	for (i = 0; i < ARRAY_SIZE(imx335_supply_name); i++)  in imx335_parse_hw_config()
1095  * Return: 0 if successful, error code otherwise.
1113 	gpiod_set_value_cansleep(imx335->reset_gpio, 0);  in imx335_power_on()
1123 	return 0;  in imx335_power_on()
1136  * Return: 0 if successful, error code otherwise.
1147 	return 0;  in imx335_power_off()
1154  * Return: 0 if successful, error code otherwise.
1189 	 * from 0.0dB (0) to 30.0dB (100) apply analog gain only, higher values  in imx335_init_controls()
1215 				     0, 0, imx335_tpg_menu);  in imx335_init_controls()
1253 	return 0;  in imx335_init_controls()
1260  * Return: 0 if successful, error code otherwise.
1305 	imx335->cur_mbus_code = imx335_mbus_codes[0];  in imx335_probe()
1327 	if (ret < 0) {  in imx335_probe()
1337 	return 0;  in imx335_probe()
1355  * Return: 0 if successful, error code otherwise.